forked from OSchip/llvm-project
[AArch64] Basic Sched Model for Cortex-A57.
Patch by Dave Estes<cestes@codeaurora.org> Differential Revision: http://reviews.llvm.org/D4008 llvm-svn: 210705
This commit is contained in:
Chad Rosier
parent
7b0d7cf96b
commit
2205d4ef05
|
|
@ -60,6 +60,7 @@ def AArch64InstrInfo : InstrInfo;
|
|||
// AArch64 Processors supported.
|
||||
//
|
||||
include "AArch64SchedA53.td"
|
||||
include "AArch64SchedA57.td"
|
||||
include "AArch64SchedCyclone.td"
|
||||
|
||||
def ProcA53 : SubtargetFeature<"a53", "ARMProcFamily", "CortexA53",
|
||||
|
|
@ -89,7 +90,7 @@ def : ProcessorModel<"generic", NoSchedModel, [FeatureFPARMv8,
|
|||
FeatureCRC]>;
|
||||
|
||||
def : ProcessorModel<"cortex-a53", CortexA53Model, [ProcA53]>;
|
||||
def : ProcessorModel<"cortex-a57", NoSchedModel, [ProcA57]>;
|
||||
def : ProcessorModel<"cortex-a57", CortexA57Model, [ProcA57]>;
|
||||
def : ProcessorModel<"cyclone", CycloneModel, [ProcCyclone]>;
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
|
|
|||
|
|
@ -0,0 +1,304 @@
|
|||
//=- AArch64SchedA57.td - ARM Cortex-A57 Scheduling Defs -----*- tablegen -*-=//
|
||||
//
|
||||
// The LLVM Compiler Infrastructure
|
||||
//
|
||||
// This file is distributed under the University of Illinois Open Source
|
||||
// License. See LICENSE.TXT for details.
|
||||
//
|
||||
//===----------------------------------------------------------------------===//
|
||||
//
|
||||
// This file defines the machine model for ARM Cortex-A57 to support
|
||||
// instruction scheduling and other instruction cost heuristics.
|
||||
//
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
def CortexA57Model : SchedMachineModel {
|
||||
let IssueWidth = 8; // 3-way decode and 8-way issue
|
||||
let MicroOpBufferSize = 128; // 128 micro-op re-order buffer
|
||||
let LoadLatency = 4; // Optimistic load latency
|
||||
let MispredictPenalty = 14; // Fetch + Decode/Rename/Dispatch + Branch
|
||||
}
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// Define each kind of processor resource and number available on Cortex-A57.
|
||||
// Cortex A-57 has 8 pipelines that each has its own 8-entry queue where
|
||||
// micro-ops wait for their operands and then issue out-of-order.
|
||||
|
||||
def A57UnitB : ProcResource<1> { let BufferSize = 8; } // Type B micro-ops
|
||||
def A57UnitI : ProcResource<2> { let BufferSize = 8; } // Type I micro-ops
|
||||
def A57UnitM : ProcResource<1> { let BufferSize = 8; } // Type M micro-ops
|
||||
def A57UnitL : ProcResource<1> { let BufferSize = 8; } // Type L micro-ops
|
||||
def A57UnitS : ProcResource<1> { let BufferSize = 8; } // Type S micro-ops
|
||||
def A57UnitX : ProcResource<1> { let BufferSize = 8; } // Type X micro-ops
|
||||
def A57UnitW : ProcResource<1> { let BufferSize = 8; } // Type W micro-ops
|
||||
let SchedModel = CortexA57Model in {
|
||||
def A57UnitV : ProcResGroup<[A57UnitX, A57UnitW]>; // Type V micro-ops
|
||||
}
|
||||
|
||||
|
||||
let SchedModel = CortexA57Model in {
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// Define customized scheduler read/write types specific to the Cortex-A57.
|
||||
|
||||
include "AArch64SchedA57WriteRes.td"
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// Map the target-defined scheduler read/write resources and latency for
|
||||
// Cortex-A57. The Cortex-A57 types are directly associated with resources, so
|
||||
// defining the aliases precludes the need for mapping them using WriteRes. The
|
||||
// aliases are sufficient for creating a coarse, working model. As the model
|
||||
// evolves, InstRWs will be used to override these SchedAliases.
|
||||
|
||||
def : SchedAlias<WriteImm, A57Write_1cyc_1I>;
|
||||
def : SchedAlias<WriteI, A57Write_1cyc_1I>;
|
||||
def : SchedAlias<WriteISReg, A57Write_2cyc_1M>;
|
||||
def : SchedAlias<WriteIEReg, A57Write_2cyc_1M>;
|
||||
def : SchedAlias<WriteExtr, A57Write_1cyc_1I>;
|
||||
def : SchedAlias<WriteIS, A57Write_1cyc_1I>;
|
||||
def : SchedAlias<WriteID32, A57Write_19cyc_1M>;
|
||||
def : SchedAlias<WriteID64, A57Write_35cyc_1M>;
|
||||
def : SchedAlias<WriteIM32, A57Write_3cyc_1M>;
|
||||
def : SchedAlias<WriteIM64, A57Write_5cyc_1M>;
|
||||
def : SchedAlias<WriteBr, A57Write_1cyc_1B>;
|
||||
def : SchedAlias<WriteBrReg, A57Write_1cyc_1B>;
|
||||
def : SchedAlias<WriteLD, A57Write_4cyc_1L>;
|
||||
def : SchedAlias<WriteST, A57Write_1cyc_1S>;
|
||||
def : SchedAlias<WriteSTP, A57Write_1cyc_1S>;
|
||||
def : SchedAlias<WriteAdr, A57Write_1cyc_1I>;
|
||||
def : SchedAlias<WriteLDIdx, A57Write_4cyc_1I_1L>;
|
||||
def : SchedAlias<WriteSTIdx, A57Write_1cyc_1I_1S>;
|
||||
def : SchedAlias<WriteF, A57Write_3cyc_1V>;
|
||||
def : SchedAlias<WriteFCmp, A57Write_3cyc_1V>;
|
||||
def : SchedAlias<WriteFCvt, A57Write_5cyc_1V>;
|
||||
def : SchedAlias<WriteFCopy, A57Write_3cyc_1V>;
|
||||
def : SchedAlias<WriteFImm, A57Write_3cyc_1V>;
|
||||
def : SchedAlias<WriteFMul, A57Write_5cyc_1V>;
|
||||
def : SchedAlias<WriteFDiv, A57Write_18cyc_1X>;
|
||||
def : SchedAlias<WriteV, A57Write_3cyc_1V>;
|
||||
def : SchedAlias<WriteVLD, A57Write_5cyc_1L>;
|
||||
def : SchedAlias<WriteVST, A57Write_1cyc_1S>;
|
||||
|
||||
def : WriteRes<WriteSys, []> { let Latency = 1; }
|
||||
def : WriteRes<WriteBarrier, []> { let Latency = 1; }
|
||||
def : WriteRes<WriteHint, []> { let Latency = 1; }
|
||||
|
||||
def : WriteRes<WriteLDHi, []> { let Latency = 4; }
|
||||
|
||||
// Forwarding logic is not [yet] explicitly modeled beyond what is captured
|
||||
// in the latencies of the A57 Generic SchedWriteRes's.
|
||||
def : ReadAdvance<ReadI, 0>;
|
||||
def : ReadAdvance<ReadISReg, 0>;
|
||||
def : ReadAdvance<ReadIEReg, 0>;
|
||||
def : ReadAdvance<ReadIM, 0>;
|
||||
def : ReadAdvance<ReadIMA, 0>;
|
||||
def : ReadAdvance<ReadID, 0>;
|
||||
def : ReadAdvance<ReadExtrHi, 0>;
|
||||
def : ReadAdvance<ReadAdrBase, 0>;
|
||||
def : ReadAdvance<ReadVLD, 0>;
|
||||
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// Specialize the coarse model by associating instruction groups with the
|
||||
// subtarget-defined types. As the modeled is refined, this will override most
|
||||
// of the above ShchedAlias mappings.
|
||||
|
||||
// Miscellaneous
|
||||
// -----------------------------------------------------------------------------
|
||||
|
||||
def : InstRW<[WriteI], (instrs COPY)>;
|
||||
|
||||
|
||||
// Branch Instructions
|
||||
// -----------------------------------------------------------------------------
|
||||
|
||||
def : InstRW<[A57Write_1cyc_1B_1I], (instrs BL)>;
|
||||
def : InstRW<[A57Write_2cyc_1B_1I], (instrs BLR)>;
|
||||
|
||||
|
||||
// Divide and Multiply Instructions
|
||||
// -----------------------------------------------------------------------------
|
||||
|
||||
// Multiply high
|
||||
def : InstRW<[A57Write_6cyc_1M], (instrs SMULHrr, UMULHrr)>;
|
||||
|
||||
|
||||
// Miscellaneous Data-Processing Instructions
|
||||
// -----------------------------------------------------------------------------
|
||||
|
||||
def : InstRW<[A57Write_1cyc_1I], (instrs EXTRWrri)>;
|
||||
def : InstRW<[A57Write_3cyc_1I_1M], (instrs EXTRXrri)>;
|
||||
def : InstRW<[A57Write_2cyc_1M], (instregex "BFM")>;
|
||||
|
||||
|
||||
// Cryptography Extensions
|
||||
// -----------------------------------------------------------------------------
|
||||
|
||||
def : InstRW<[A57Write_3cyc_1W], (instregex "CRC32")>;
|
||||
|
||||
|
||||
// Vector Load
|
||||
// -----------------------------------------------------------------------------
|
||||
|
||||
def : InstRW<[A57Write_8cyc_1L_1V], (instregex "LD1i(8|16|32)$")>;
|
||||
def : InstRW<[A57Write_8cyc_1L_1V, WriteAdr], (instregex "LD1i(8|16|32)_POST$")>;
|
||||
def : InstRW<[A57Write_5cyc_1L], (instregex "LD1i(64)$")>;
|
||||
def : InstRW<[A57Write_5cyc_1L, WriteAdr], (instregex "LD1i(64)_POST$")>;
|
||||
|
||||
def : InstRW<[A57Write_8cyc_1L_1V], (instregex "LD1Rv(8b|4h|2s)$")>;
|
||||
def : InstRW<[A57Write_8cyc_1L_1V, WriteAdr], (instregex "LD1Rv(8b|4h|2s)_POST$")>;
|
||||
def : InstRW<[A57Write_5cyc_1L], (instregex "LD1Rv(1d)$")>;
|
||||
def : InstRW<[A57Write_5cyc_1L, WriteAdr], (instregex "LD1Rv(1d)_POST$")>;
|
||||
def : InstRW<[A57Write_8cyc_1L_1V], (instregex "LD1Rv(16b|8h|4s|2d)$")>;
|
||||
def : InstRW<[A57Write_8cyc_1L_1V, WriteAdr], (instregex "LD1Rv(16b|8h|4s|2d)_POST$")>;
|
||||
|
||||
def : InstRW<[A57Write_5cyc_1L], (instregex "LD1Onev(8b|4h|2s|1d)$")>;
|
||||
def : InstRW<[A57Write_5cyc_1L, WriteAdr], (instregex "LD1Onev(8b|4h|2s|1d)_POST$")>;
|
||||
def : InstRW<[A57Write_5cyc_1L], (instregex "LD1Onev(16b|8h|4s|2d)$")>;
|
||||
def : InstRW<[A57Write_5cyc_1L, WriteAdr], (instregex "LD1Onev(16b|8h|4s|2d)_POST$")>;
|
||||
def : InstRW<[A57Write_5cyc_1L], (instregex "LD1Twov(8b|4h|2s|1d)$")>;
|
||||
def : InstRW<[A57Write_5cyc_1L, WriteAdr], (instregex "LD1Twov(8b|4h|2s|1d)_POST$")>;
|
||||
def : InstRW<[A57Write_6cyc_2L], (instregex "LD1Twov(16b|8h|4s|2d)$")>;
|
||||
def : InstRW<[A57Write_6cyc_2L, WriteAdr], (instregex "LD1Twov(16b|8h|4s|2d)_POST$")>;
|
||||
def : InstRW<[A57Write_6cyc_2L], (instregex "LD1Threev(8b|4h|2s|1d)$")>;
|
||||
def : InstRW<[A57Write_6cyc_2L, WriteAdr], (instregex "LD1Threev(8b|4h|2s|1d)_POST$")>;
|
||||
def : InstRW<[A57Write_7cyc_3L], (instregex "LD1Threev(16b|8h|4s|2d)$")>;
|
||||
def : InstRW<[A57Write_7cyc_3L, WriteAdr], (instregex "LD1Threev(16b|8h|4s|2d)_POST$")>;
|
||||
def : InstRW<[A57Write_6cyc_2L], (instregex "LD1Fourv(8b|4h|2s|1d)$")>;
|
||||
def : InstRW<[A57Write_6cyc_2L, WriteAdr], (instregex "LD1Fourv(8b|4h|2s|1d)_POST$")>;
|
||||
def : InstRW<[A57Write_8cyc_4L], (instregex "LD1Fourv(16b|8h|4s|2d)$")>;
|
||||
def : InstRW<[A57Write_8cyc_4L, WriteAdr], (instregex "LD1Fourv(16b|8h|4s|2d)_POST$")>;
|
||||
|
||||
def : InstRW<[A57Write_8cyc_1L_2V], (instregex "LD2i(8|16)$")>;
|
||||
def : InstRW<[A57Write_8cyc_1L_2V, WriteAdr], (instregex "LD2i(8|16)_POST$")>;
|
||||
def : InstRW<[A57Write_6cyc_2L], (instregex "LD2i(32)$")>;
|
||||
def : InstRW<[A57Write_6cyc_2L, WriteAdr], (instregex "LD2i(32)_POST$")>;
|
||||
def : InstRW<[A57Write_8cyc_1L_1V], (instregex "LD2i(64)$")>;
|
||||
def : InstRW<[A57Write_8cyc_1L_1V, WriteAdr], (instregex "LD2i(64)_POST$")>;
|
||||
|
||||
def : InstRW<[A57Write_8cyc_1L_1V], (instregex "LD2Rv(8b|4h|2s)$")>;
|
||||
def : InstRW<[A57Write_8cyc_1L_1V, WriteAdr], (instregex "LD2Rv(8b|4h|2s)_POST$")>;
|
||||
def : InstRW<[A57Write_5cyc_1L], (instregex "LD2Rv(1d)$")>;
|
||||
def : InstRW<[A57Write_5cyc_1L, WriteAdr], (instregex "LD2Rv(1d)_POST$")>;
|
||||
def : InstRW<[A57Write_8cyc_1L_2V], (instregex "LD2Rv(16b|8h|4s|2d)$")>;
|
||||
def : InstRW<[A57Write_8cyc_1L_2V, WriteAdr], (instregex "LD2Rv(16b|8h|4s|2d)_POST$")>;
|
||||
|
||||
def : InstRW<[A57Write_8cyc_1L_1V], (instregex "LD2Twov(8b|4h|2s)$")>;
|
||||
def : InstRW<[A57Write_8cyc_1L_1V, WriteAdr], (instregex "LD2Twov(8b|4h|2s)_POST$")>;
|
||||
def : InstRW<[A57Write_9cyc_2L_2V], (instregex "LD2Twov(16b|8h|4s)$")>;
|
||||
def : InstRW<[A57Write_9cyc_2L_2V, WriteAdr], (instregex "LD2Twov(16b|8h|4s)_POST$")>;
|
||||
def : InstRW<[A57Write_6cyc_2L], (instregex "LD2Twov(2d)$")>;
|
||||
def : InstRW<[A57Write_6cyc_2L, WriteAdr], (instregex "LD2Twov(2d)_POST$")>;
|
||||
|
||||
def : InstRW<[A57Write_9cyc_1L_3V], (instregex "LD3i(8|16)$")>;
|
||||
def : InstRW<[A57Write_9cyc_1L_3V, WriteAdr], (instregex "LD3i(8|16)_POST$")>;
|
||||
def : InstRW<[A57Write_8cyc_1L_2V], (instregex "LD3i(32)$")>;
|
||||
def : InstRW<[A57Write_8cyc_1L_2V, WriteAdr], (instregex "LD3i(32)_POST$")>;
|
||||
def : InstRW<[A57Write_6cyc_2L], (instregex "LD3i(64)$")>;
|
||||
def : InstRW<[A57Write_6cyc_2L, WriteAdr], (instregex "LD3i(64)_POST$")>;
|
||||
|
||||
def : InstRW<[A57Write_8cyc_1L_2V], (instregex "LD3Rv(8b|4h|2s)$")>;
|
||||
def : InstRW<[A57Write_8cyc_1L_2V, WriteAdr], (instregex "LD3Rv(8b|4h|2s)_POST$")>;
|
||||
def : InstRW<[A57Write_6cyc_2L], (instregex "LD3Rv(1d)$")>;
|
||||
def : InstRW<[A57Write_6cyc_2L, WriteAdr], (instregex "LD3Rv(1d)_POST$")>;
|
||||
def : InstRW<[A57Write_9cyc_1L_3V], (instregex "LD3Rv(16b|8h|4s)$")>;
|
||||
def : InstRW<[A57Write_9cyc_1L_3V, WriteAdr], (instregex "LD3Rv(16b|8h|4s)_POST$")>;
|
||||
def : InstRW<[A57Write_9cyc_2L_3V], (instregex "LD3Rv(2d)$")>;
|
||||
def : InstRW<[A57Write_9cyc_2L_3V, WriteAdr], (instregex "LD3Rv(2d)_POST$")>;
|
||||
|
||||
def : InstRW<[A57Write_9cyc_2L_2V], (instregex "LD3Threev(8b|4h|2s)$")>;
|
||||
def : InstRW<[A57Write_9cyc_2L_2V, WriteAdr], (instregex "LD3Threev(8b|4h|2s)_POST$")>;
|
||||
def : InstRW<[A57Write_10cyc_3L_4V], (instregex "LD3Threev(16b|8h|4s)$")>;
|
||||
def : InstRW<[A57Write_10cyc_3L_4V, WriteAdr], (instregex "LD3Threev(16b|8h|4s)_POST$")>;
|
||||
def : InstRW<[A57Write_8cyc_4L], (instregex "LD3Threev(2d)$")>;
|
||||
def : InstRW<[A57Write_8cyc_4L, WriteAdr], (instregex "LD3Threev(2d)_POST$")>;
|
||||
|
||||
def : InstRW<[A57Write_9cyc_2L_3V], (instregex "LD4i(8|16)$")>;
|
||||
def : InstRW<[A57Write_9cyc_2L_3V, WriteAdr], (instregex "LD4i(8|16)_POST$")>;
|
||||
def : InstRW<[A57Write_8cyc_1L_2V], (instregex "LD4i(32)$")>;
|
||||
def : InstRW<[A57Write_8cyc_1L_2V, WriteAdr], (instregex "LD4i(32)_POST$")>;
|
||||
def : InstRW<[A57Write_9cyc_2L_3V], (instregex "LD4i(64)$")>;
|
||||
def : InstRW<[A57Write_9cyc_2L_3V, WriteAdr], (instregex "LD4i(64)_POST$")>;
|
||||
|
||||
def : InstRW<[A57Write_8cyc_1L_2V], (instregex "LD4Rv(8b|4h|2s)$")>;
|
||||
def : InstRW<[A57Write_8cyc_1L_2V, WriteAdr], (instregex "LD4Rv(8b|4h|2s)_POST$")>;
|
||||
def : InstRW<[A57Write_6cyc_2L], (instregex "LD4Rv(1d)$")>;
|
||||
def : InstRW<[A57Write_6cyc_2L, WriteAdr], (instregex "LD4Rv(1d)_POST$")>;
|
||||
def : InstRW<[A57Write_9cyc_2L_3V], (instregex "LD4Rv(16b|8h|4s)$")>;
|
||||
def : InstRW<[A57Write_9cyc_2L_3V, WriteAdr], (instregex "LD4Rv(16b|8h|4s)_POST$")>;
|
||||
def : InstRW<[A57Write_9cyc_2L_4V], (instregex "LD4Rv(2d)$")>;
|
||||
def : InstRW<[A57Write_9cyc_2L_4V, WriteAdr], (instregex "LD4Rv(2d)_POST$")>;
|
||||
|
||||
def : InstRW<[A57Write_9cyc_2L_2V], (instregex "LD4Fourv(8b|4h|2s)$")>;
|
||||
def : InstRW<[A57Write_9cyc_2L_2V, WriteAdr], (instregex "LD4Fourv(8b|4h|2s)_POST$")>;
|
||||
def : InstRW<[A57Write_11cyc_4L_4V], (instregex "LD4Fourv(16b|8h|4s)$")>;
|
||||
def : InstRW<[A57Write_11cyc_4L_4V, WriteAdr], (instregex "LD4Fourv(16b|8h|4s)_POST$")>;
|
||||
def : InstRW<[A57Write_8cyc_4L], (instregex "LD4Fourv(2d)$")>;
|
||||
def : InstRW<[A57Write_8cyc_4L, WriteAdr], (instregex "LD4Fourv(2d)_POST$")>;
|
||||
|
||||
// Vector Store
|
||||
// -----------------------------------------------------------------------------
|
||||
|
||||
def : InstRW<[A57Write_1cyc_1S], (instregex "ST1i(8|16|32)$")>;
|
||||
def : InstRW<[A57Write_1cyc_1S, WriteAdr], (instregex "ST1i(8|16|32)_POST$")>;
|
||||
def : InstRW<[A57Write_3cyc_1S_1V], (instregex "ST1i(64)$")>;
|
||||
def : InstRW<[A57Write_3cyc_1S_1V, WriteAdr], (instregex "ST1i(64)_POST$")>;
|
||||
|
||||
def : InstRW<[A57Write_1cyc_1S], (instregex "ST1Onev(8b|4h|2s|1d)$")>;
|
||||
def : InstRW<[A57Write_1cyc_1S, WriteAdr], (instregex "ST1Onev(8b|4h|2s|1d)_POST$")>;
|
||||
def : InstRW<[A57Write_2cyc_2S], (instregex "ST1Onev(16b|8h|4s|2d)$")>;
|
||||
def : InstRW<[A57Write_2cyc_2S, WriteAdr], (instregex "ST1Onev(16b|8h|4s|2d)_POST$")>;
|
||||
def : InstRW<[A57Write_2cyc_2S], (instregex "ST1Twov(8b|4h|2s|1d)$")>;
|
||||
def : InstRW<[A57Write_2cyc_2S, WriteAdr], (instregex "ST1Twov(8b|4h|2s|1d)_POST$")>;
|
||||
def : InstRW<[A57Write_4cyc_4S], (instregex "ST1Twov(16b|8h|4s|2d)$")>;
|
||||
def : InstRW<[A57Write_4cyc_4S, WriteAdr], (instregex "ST1Twov(16b|8h|4s|2d)_POST$")>;
|
||||
def : InstRW<[A57Write_3cyc_3S], (instregex "ST1Threev(8b|4h|2s|1d)$")>;
|
||||
def : InstRW<[A57Write_3cyc_3S, WriteAdr], (instregex "ST1Threev(8b|4h|2s|1d)_POST$")>;
|
||||
def : InstRW<[A57Write_6cyc_6S], (instregex "ST1Threev(16b|8h|4s|2d)$")>;
|
||||
def : InstRW<[A57Write_6cyc_6S, WriteAdr], (instregex "ST1Threev(16b|8h|4s|2d)_POST$")>;
|
||||
def : InstRW<[A57Write_4cyc_4S], (instregex "ST1Fourv(8b|4h|2s|1d)$")>;
|
||||
def : InstRW<[A57Write_4cyc_4S, WriteAdr], (instregex "ST1Fourv(8b|4h|2s|1d)_POST$")>;
|
||||
def : InstRW<[A57Write_8cyc_8S], (instregex "ST1Fourv(16b|8h|4s|2d)$")>;
|
||||
def : InstRW<[A57Write_8cyc_8S, WriteAdr], (instregex "ST1Fourv(16b|8h|4s|2d)_POST$")>;
|
||||
|
||||
def : InstRW<[A57Write_3cyc_1S_1V], (instregex "ST2i(8|16|32)$")>;
|
||||
def : InstRW<[A57Write_3cyc_1S_1V, WriteAdr], (instregex "ST2i(8|16|32)_POST$")>;
|
||||
def : InstRW<[A57Write_2cyc_2S], (instregex "ST2i(64)$")>;
|
||||
def : InstRW<[A57Write_2cyc_2S, WriteAdr], (instregex "ST2i(64)_POST$")>;
|
||||
|
||||
def : InstRW<[A57Write_3cyc_2S_1V], (instregex "ST2Twov(8b|4h|2s)$")>;
|
||||
def : InstRW<[A57Write_3cyc_2S_1V, WriteAdr], (instregex "ST2Twov(8b|4h|2s)_POST$")>;
|
||||
def : InstRW<[A57Write_4cyc_4S_2V], (instregex "ST2Twov(16b|8h|4s)$")>;
|
||||
def : InstRW<[A57Write_4cyc_4S_2V, WriteAdr], (instregex "ST2Twov(16b|8h|4s)_POST$")>;
|
||||
def : InstRW<[A57Write_4cyc_4S], (instregex "ST2Twov(2d)$")>;
|
||||
def : InstRW<[A57Write_4cyc_4S, WriteAdr], (instregex "ST2Twov(2d)_POST$")>;
|
||||
|
||||
def : InstRW<[A57Write_3cyc_1S_1V], (instregex "ST3i(8|16)$")>;
|
||||
def : InstRW<[A57Write_3cyc_1S_1V, WriteAdr], (instregex "ST3i(8|16)_POST$")>;
|
||||
def : InstRW<[A57Write_3cyc_3S], (instregex "ST3i(32)$")>;
|
||||
def : InstRW<[A57Write_3cyc_3S, WriteAdr], (instregex "ST3i(32)_POST$")>;
|
||||
def : InstRW<[A57Write_3cyc_2S_1V], (instregex "ST3i(64)$")>;
|
||||
def : InstRW<[A57Write_3cyc_2S_1V, WriteAdr], (instregex "ST3i(64)_POST$")>;
|
||||
|
||||
def : InstRW<[A57Write_3cyc_3S_2V], (instregex "ST3Threev(8b|4h|2s)$")>;
|
||||
def : InstRW<[A57Write_3cyc_3S_2V, WriteAdr], (instregex "ST3Threev(8b|4h|2s)_POST$")>;
|
||||
def : InstRW<[A57Write_6cyc_6S_4V], (instregex "ST3Threev(16b|8h|4s)$")>;
|
||||
def : InstRW<[A57Write_6cyc_6S_4V, WriteAdr], (instregex "ST3Threev(16b|8h|4s)_POST$")>;
|
||||
def : InstRW<[A57Write_6cyc_6S], (instregex "ST3Threev(2d)$")>;
|
||||
def : InstRW<[A57Write_6cyc_6S, WriteAdr], (instregex "ST3Threev(2d)_POST$")>;
|
||||
|
||||
def : InstRW<[A57Write_3cyc_1S_1V], (instregex "ST4i(8|16)$")>;
|
||||
def : InstRW<[A57Write_3cyc_1S_1V, WriteAdr], (instregex "ST4i(8|16)_POST$")>;
|
||||
def : InstRW<[A57Write_4cyc_4S], (instregex "ST4i(32)$")>;
|
||||
def : InstRW<[A57Write_4cyc_4S, WriteAdr], (instregex "ST4i(32)_POST$")>;
|
||||
def : InstRW<[A57Write_3cyc_2S_1V], (instregex "ST4i(64)$")>;
|
||||
def : InstRW<[A57Write_3cyc_2S_1V, WriteAdr], (instregex "ST4i(64)_POST$")>;
|
||||
|
||||
def : InstRW<[A57Write_4cyc_4S_2V], (instregex "ST4Fourv(8b|4h|2s)$")>;
|
||||
def : InstRW<[A57Write_4cyc_4S_2V, WriteAdr], (instregex "ST4Fourv(8b|4h|2s)_POST$")>;
|
||||
def : InstRW<[A57Write_8cyc_8S_4V], (instregex "ST4Fourv(16b|8h|4s)$")>;
|
||||
def : InstRW<[A57Write_8cyc_8S_4V, WriteAdr], (instregex "ST4Fourv(16b|8h|4s)_POST$")>;
|
||||
def : InstRW<[A57Write_8cyc_8S], (instregex "ST4Fourv(2d)$")>;
|
||||
def : InstRW<[A57Write_8cyc_8S, WriteAdr], (instregex "ST4Fourv(2d)_POST$")>;
|
||||
|
||||
} // SchedModel = CortexA57Model
|
||||
|
|
@ -0,0 +1,512 @@
|
|||
//=- AArch64SchedA57WriteRes.td - ARM Cortex-A57 Write Res ---*- tablegen -*-=//
|
||||
//
|
||||
// The LLVM Compiler Infrastructure
|
||||
//
|
||||
// This file is distributed under the University of Illinois Open Source
|
||||
// License. See LICENSE.TXT for details.
|
||||
//
|
||||
//===----------------------------------------------------------------------===//
|
||||
//
|
||||
// Contains all of the Cortex-A57 specific SchedWriteRes types. The approach
|
||||
// below is to define a generic SchedWriteRes for every combination of
|
||||
// latency and microOps. The naming conventions is to use a prefix, one field
|
||||
// for latency, and one or more microOp count/type designators.
|
||||
// Prefix: A57Write
|
||||
// Latency: #cyc
|
||||
// MicroOp Count/Types: #(B|I|M|L|S|X|W|V)
|
||||
//
|
||||
// e.g. A57Write_6cyc_1I_6S_4V means the total latency is 6 and there are
|
||||
// 11 micro-ops to be issued down one I pipe, six S pipes and four V pipes.
|
||||
//
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// Define Generic 1 micro-op types
|
||||
|
||||
def A57Write_5cyc_1L : SchedWriteRes<[A57UnitL]> { let Latency = 5; }
|
||||
def A57Write_5cyc_1M : SchedWriteRes<[A57UnitM]> { let Latency = 5; }
|
||||
def A57Write_5cyc_1V : SchedWriteRes<[A57UnitV]> { let Latency = 5; }
|
||||
def A57Write_5cyc_1W : SchedWriteRes<[A57UnitW]> { let Latency = 5; }
|
||||
def A57Write_10cyc_1V : SchedWriteRes<[A57UnitV]> { let Latency = 10; }
|
||||
def A57Write_18cyc_1X : SchedWriteRes<[A57UnitX]> { let Latency = 18; }
|
||||
def A57Write_19cyc_1M : SchedWriteRes<[A57UnitM]> { let Latency = 19; }
|
||||
def A57Write_1cyc_1B : SchedWriteRes<[A57UnitB]> { let Latency = 1; }
|
||||
def A57Write_1cyc_1I : SchedWriteRes<[A57UnitI]> { let Latency = 1; }
|
||||
def A57Write_1cyc_1S : SchedWriteRes<[A57UnitS]> { let Latency = 1; }
|
||||
def A57Write_2cyc_1M : SchedWriteRes<[A57UnitM]> { let Latency = 2; }
|
||||
def A57Write_32cyc_1X : SchedWriteRes<[A57UnitX]> { let Latency = 32; }
|
||||
def A57Write_35cyc_1M : SchedWriteRes<[A57UnitM]> { let Latency = 35; }
|
||||
def A57Write_3cyc_1M : SchedWriteRes<[A57UnitM]> { let Latency = 3; }
|
||||
def A57Write_3cyc_1V : SchedWriteRes<[A57UnitV]> { let Latency = 3; }
|
||||
def A57Write_3cyc_1W : SchedWriteRes<[A57UnitW]> { let Latency = 3; }
|
||||
def A57Write_3cyc_1X : SchedWriteRes<[A57UnitX]> { let Latency = 3; }
|
||||
def A57Write_4cyc_1L : SchedWriteRes<[A57UnitL]> { let Latency = 4; }
|
||||
def A57Write_4cyc_1X : SchedWriteRes<[A57UnitX]> { let Latency = 4; }
|
||||
def A57Write_9cyc_1V : SchedWriteRes<[A57UnitV]> { let Latency = 9; }
|
||||
def A57Write_6cyc_1M : SchedWriteRes<[A57UnitM]> { let Latency = 6; }
|
||||
def A57Write_6cyc_1V : SchedWriteRes<[A57UnitV]> { let Latency = 6; }
|
||||
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// Define Generic 2 micro-op types
|
||||
|
||||
def A57Write_64cyc_2X : SchedWriteRes<[A57UnitX, A57UnitX]> {
|
||||
let Latency = 64;
|
||||
let NumMicroOps = 2;
|
||||
}
|
||||
def A57Write_6cyc_1I_1L : SchedWriteRes<[A57UnitI,
|
||||
A57UnitL]> {
|
||||
let Latency = 6;
|
||||
let NumMicroOps = 2;
|
||||
}
|
||||
def A57Write_7cyc_1V_1X : SchedWriteRes<[A57UnitV,
|
||||
A57UnitX]> {
|
||||
let Latency = 7;
|
||||
let NumMicroOps = 2;
|
||||
}
|
||||
def A57Write_8cyc_1L_1V : SchedWriteRes<[A57UnitL,
|
||||
A57UnitV]> {
|
||||
let Latency = 8;
|
||||
let NumMicroOps = 2;
|
||||
}
|
||||
def A57Write_9cyc_2V : SchedWriteRes<[A57UnitV, A57UnitV]> {
|
||||
let Latency = 9;
|
||||
let NumMicroOps = 2;
|
||||
}
|
||||
def A57Write_8cyc_2X : SchedWriteRes<[A57UnitX, A57UnitX]> {
|
||||
let Latency = 8;
|
||||
let NumMicroOps = 2;
|
||||
}
|
||||
def A57Write_6cyc_2L : SchedWriteRes<[A57UnitL, A57UnitL]> {
|
||||
let Latency = 6;
|
||||
let NumMicroOps = 2;
|
||||
}
|
||||
def A57Write_6cyc_2V : SchedWriteRes<[A57UnitV, A57UnitV]> {
|
||||
let Latency = 6;
|
||||
let NumMicroOps = 2;
|
||||
}
|
||||
def A57Write_6cyc_2W : SchedWriteRes<[A57UnitW, A57UnitW]> {
|
||||
let Latency = 6;
|
||||
let NumMicroOps = 2;
|
||||
}
|
||||
def A57Write_5cyc_1I_1L : SchedWriteRes<[A57UnitI,
|
||||
A57UnitL]> {
|
||||
let Latency = 5;
|
||||
let NumMicroOps = 2;
|
||||
}
|
||||
def A57Write_5cyc_2V : SchedWriteRes<[A57UnitV, A57UnitV]> {
|
||||
let Latency = 5;
|
||||
let NumMicroOps = 2;
|
||||
}
|
||||
def A57Write_5cyc_2X : SchedWriteRes<[A57UnitX, A57UnitX]> {
|
||||
let Latency = 5;
|
||||
let NumMicroOps = 2;
|
||||
}
|
||||
def A57Write_10cyc_1L_1V : SchedWriteRes<[A57UnitL,
|
||||
A57UnitV]> {
|
||||
let Latency = 10;
|
||||
let NumMicroOps = 2;
|
||||
}
|
||||
def A57Write_10cyc_2V : SchedWriteRes<[A57UnitV, A57UnitV]> {
|
||||
let Latency = 10;
|
||||
let NumMicroOps = 2;
|
||||
}
|
||||
def A57Write_1cyc_1B_1I : SchedWriteRes<[A57UnitB,
|
||||
A57UnitI]> {
|
||||
let Latency = 1;
|
||||
let NumMicroOps = 2;
|
||||
}
|
||||
def A57Write_1cyc_1I_1S : SchedWriteRes<[A57UnitI,
|
||||
A57UnitS]> {
|
||||
let Latency = 1;
|
||||
let NumMicroOps = 2;
|
||||
}
|
||||
def A57Write_2cyc_1B_1I : SchedWriteRes<[A57UnitB,
|
||||
A57UnitI]> {
|
||||
let Latency = 2;
|
||||
let NumMicroOps = 2;
|
||||
}
|
||||
def A57Write_2cyc_2S : SchedWriteRes<[A57UnitS, A57UnitS]> {
|
||||
let Latency = 2;
|
||||
let NumMicroOps = 2;
|
||||
}
|
||||
def A57Write_2cyc_2V : SchedWriteRes<[A57UnitV, A57UnitV]> {
|
||||
let Latency = 2;
|
||||
let NumMicroOps = 2;
|
||||
}
|
||||
def A57Write_36cyc_2X : SchedWriteRes<[A57UnitX, A57UnitX]> {
|
||||
let Latency = 36;
|
||||
let NumMicroOps = 2;
|
||||
}
|
||||
def A57Write_3cyc_1I_1M : SchedWriteRes<[A57UnitI,
|
||||
A57UnitM]> {
|
||||
let Latency = 3;
|
||||
let NumMicroOps = 2;
|
||||
}
|
||||
def A57Write_3cyc_1I_1S : SchedWriteRes<[A57UnitI,
|
||||
A57UnitS]> {
|
||||
let Latency = 3;
|
||||
let NumMicroOps = 2;
|
||||
}
|
||||
def A57Write_3cyc_1S_1V : SchedWriteRes<[A57UnitS,
|
||||
A57UnitV]> {
|
||||
let Latency = 3;
|
||||
let NumMicroOps = 2;
|
||||
}
|
||||
def A57Write_4cyc_1I_1L : SchedWriteRes<[A57UnitI,
|
||||
A57UnitL]> {
|
||||
let Latency = 4;
|
||||
let NumMicroOps = 2;
|
||||
}
|
||||
def A57Write_4cyc_2X : SchedWriteRes<[A57UnitX, A57UnitX]> {
|
||||
let Latency = 4;
|
||||
let NumMicroOps = 2;
|
||||
}
|
||||
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// Define Generic 3 micro-op types
|
||||
|
||||
def A57Write_10cyc_3V : SchedWriteRes<[A57UnitV, A57UnitV, A57UnitV]> {
|
||||
let Latency = 10;
|
||||
let NumMicroOps = 3;
|
||||
}
|
||||
def A57Write_2cyc_1I_2S : SchedWriteRes<[A57UnitI,
|
||||
A57UnitS, A57UnitS]> {
|
||||
let Latency = 2;
|
||||
let NumMicroOps = 3;
|
||||
}
|
||||
def A57Write_3cyc_1I_1S_1V : SchedWriteRes<[A57UnitI,
|
||||
A57UnitS,
|
||||
A57UnitV]> {
|
||||
let Latency = 3;
|
||||
let NumMicroOps = 3;
|
||||
}
|
||||
def A57Write_3cyc_1M_2S : SchedWriteRes<[A57UnitM,
|
||||
A57UnitS, A57UnitS]> {
|
||||
let Latency = 3;
|
||||
let NumMicroOps = 3;
|
||||
}
|
||||
def A57Write_3cyc_3S : SchedWriteRes<[A57UnitS, A57UnitS, A57UnitS]> {
|
||||
let Latency = 3;
|
||||
let NumMicroOps = 3;
|
||||
}
|
||||
def A57Write_3cyc_2S_1V : SchedWriteRes<[A57UnitS, A57UnitS,
|
||||
A57UnitV]> {
|
||||
let Latency = 3;
|
||||
let NumMicroOps = 3;
|
||||
}
|
||||
def A57Write_5cyc_1I_2L : SchedWriteRes<[A57UnitI,
|
||||
A57UnitL, A57UnitL]> {
|
||||
let Latency = 5;
|
||||
let NumMicroOps = 3;
|
||||
}
|
||||
def A57Write_6cyc_1I_2L : SchedWriteRes<[A57UnitI,
|
||||
A57UnitL, A57UnitL]> {
|
||||
let Latency = 6;
|
||||
let NumMicroOps = 3;
|
||||
}
|
||||
def A57Write_6cyc_3V : SchedWriteRes<[A57UnitV, A57UnitV, A57UnitV]> {
|
||||
let Latency = 6;
|
||||
let NumMicroOps = 3;
|
||||
}
|
||||
def A57Write_7cyc_3L : SchedWriteRes<[A57UnitL, A57UnitL, A57UnitL]> {
|
||||
let Latency = 7;
|
||||
let NumMicroOps = 3;
|
||||
}
|
||||
def A57Write_8cyc_1I_1L_1V : SchedWriteRes<[A57UnitI,
|
||||
A57UnitL,
|
||||
A57UnitV]> {
|
||||
let Latency = 8;
|
||||
let NumMicroOps = 3;
|
||||
}
|
||||
def A57Write_8cyc_1L_2V : SchedWriteRes<[A57UnitL,
|
||||
A57UnitV, A57UnitV]> {
|
||||
let Latency = 8;
|
||||
let NumMicroOps = 3;
|
||||
}
|
||||
def A57Write_8cyc_3V : SchedWriteRes<[A57UnitV, A57UnitV, A57UnitV]> {
|
||||
let Latency = 8;
|
||||
let NumMicroOps = 3;
|
||||
}
|
||||
def A57Write_9cyc_3V : SchedWriteRes<[A57UnitV, A57UnitV, A57UnitV]> {
|
||||
let Latency = 9;
|
||||
let NumMicroOps = 3;
|
||||
}
|
||||
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// Define Generic 4 micro-op types
|
||||
|
||||
def A57Write_2cyc_2I_2S : SchedWriteRes<[A57UnitI, A57UnitI,
|
||||
A57UnitS, A57UnitS]> {
|
||||
let Latency = 2;
|
||||
let NumMicroOps = 4;
|
||||
}
|
||||
def A57Write_3cyc_2I_2S : SchedWriteRes<[A57UnitI, A57UnitI,
|
||||
A57UnitS, A57UnitS]> {
|
||||
let Latency = 3;
|
||||
let NumMicroOps = 4;
|
||||
}
|
||||
def A57Write_3cyc_1I_3S : SchedWriteRes<[A57UnitI,
|
||||
A57UnitS, A57UnitS, A57UnitS]> {
|
||||
let Latency = 3;
|
||||
let NumMicroOps = 4;
|
||||
}
|
||||
def A57Write_3cyc_1I_2S_1V : SchedWriteRes<[A57UnitI,
|
||||
A57UnitS, A57UnitS,
|
||||
A57UnitV]> {
|
||||
let Latency = 3;
|
||||
let NumMicroOps = 4;
|
||||
}
|
||||
def A57Write_4cyc_4S : SchedWriteRes<[A57UnitS, A57UnitS,
|
||||
A57UnitS, A57UnitS]> {
|
||||
let Latency = 4;
|
||||
let NumMicroOps = 4;
|
||||
}
|
||||
def A57Write_7cyc_1I_3L : SchedWriteRes<[A57UnitI,
|
||||
A57UnitL, A57UnitL, A57UnitL]> {
|
||||
let Latency = 7;
|
||||
let NumMicroOps = 4;
|
||||
}
|
||||
def A57Write_5cyc_2I_2L : SchedWriteRes<[A57UnitI, A57UnitI,
|
||||
A57UnitL, A57UnitL]> {
|
||||
let Latency = 5;
|
||||
let NumMicroOps = 4;
|
||||
}
|
||||
def A57Write_8cyc_1I_1L_2V : SchedWriteRes<[A57UnitI,
|
||||
A57UnitL,
|
||||
A57UnitV, A57UnitV]> {
|
||||
let Latency = 8;
|
||||
let NumMicroOps = 4;
|
||||
}
|
||||
def A57Write_8cyc_4L : SchedWriteRes<[A57UnitL, A57UnitL,
|
||||
A57UnitL, A57UnitL]> {
|
||||
let Latency = 8;
|
||||
let NumMicroOps = 4;
|
||||
}
|
||||
def A57Write_9cyc_2L_2V : SchedWriteRes<[A57UnitL, A57UnitL,
|
||||
A57UnitV, A57UnitV]> {
|
||||
let Latency = 9;
|
||||
let NumMicroOps = 4;
|
||||
}
|
||||
def A57Write_9cyc_1L_3V : SchedWriteRes<[A57UnitL,
|
||||
A57UnitV, A57UnitV, A57UnitV]> {
|
||||
let Latency = 9;
|
||||
let NumMicroOps = 4;
|
||||
}
|
||||
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// Define Generic 5 micro-op types
|
||||
|
||||
def A57Write_3cyc_3S_2V : SchedWriteRes<[A57UnitS, A57UnitS, A57UnitS,
|
||||
A57UnitV, A57UnitV]> {
|
||||
let Latency = 3;
|
||||
let NumMicroOps = 5;
|
||||
}
|
||||
def A57Write_8cyc_1I_4L : SchedWriteRes<[A57UnitI,
|
||||
A57UnitL, A57UnitL,
|
||||
A57UnitL, A57UnitL]> {
|
||||
let Latency = 8;
|
||||
let NumMicroOps = 5;
|
||||
}
|
||||
def A57Write_4cyc_1I_4S : SchedWriteRes<[A57UnitI,
|
||||
A57UnitS, A57UnitS,
|
||||
A57UnitS, A57UnitS]> {
|
||||
let Latency = 4;
|
||||
let NumMicroOps = 5;
|
||||
}
|
||||
def A57Write_9cyc_1I_2L_2V : SchedWriteRes<[A57UnitI,
|
||||
A57UnitL, A57UnitL,
|
||||
A57UnitV, A57UnitV]> {
|
||||
let Latency = 9;
|
||||
let NumMicroOps = 5;
|
||||
}
|
||||
def A57Write_9cyc_1I_1L_3V : SchedWriteRes<[A57UnitI,
|
||||
A57UnitL,
|
||||
A57UnitV, A57UnitV, A57UnitV]> {
|
||||
let Latency = 9;
|
||||
let NumMicroOps = 5;
|
||||
}
|
||||
def A57Write_9cyc_2L_3V : SchedWriteRes<[A57UnitL, A57UnitL,
|
||||
A57UnitV, A57UnitV, A57UnitV]> {
|
||||
let Latency = 9;
|
||||
let NumMicroOps = 5;
|
||||
}
|
||||
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// Define Generic 6 micro-op types
|
||||
|
||||
def A57Write_3cyc_1I_3S_2V : SchedWriteRes<[A57UnitI,
|
||||
A57UnitS, A57UnitS, A57UnitS,
|
||||
A57UnitV, A57UnitV]> {
|
||||
let Latency = 3;
|
||||
let NumMicroOps = 6;
|
||||
}
|
||||
def A57Write_4cyc_2I_4S : SchedWriteRes<[A57UnitI, A57UnitI,
|
||||
A57UnitS, A57UnitS,
|
||||
A57UnitS, A57UnitS]> {
|
||||
let Latency = 4;
|
||||
let NumMicroOps = 6;
|
||||
}
|
||||
def A57Write_4cyc_4S_2V : SchedWriteRes<[A57UnitS, A57UnitS,
|
||||
A57UnitS, A57UnitS,
|
||||
A57UnitV, A57UnitV]> {
|
||||
let Latency = 4;
|
||||
let NumMicroOps = 6;
|
||||
}
|
||||
def A57Write_6cyc_6S : SchedWriteRes<[A57UnitS, A57UnitS, A57UnitS,
|
||||
A57UnitS, A57UnitS, A57UnitS]> {
|
||||
let Latency = 6;
|
||||
let NumMicroOps = 6;
|
||||
}
|
||||
def A57Write_9cyc_1I_2L_3V : SchedWriteRes<[A57UnitI,
|
||||
A57UnitL, A57UnitL,
|
||||
A57UnitV, A57UnitV, A57UnitV]> {
|
||||
let Latency = 9;
|
||||
let NumMicroOps = 6;
|
||||
}
|
||||
def A57Write_9cyc_1I_1L_4V : SchedWriteRes<[A57UnitI,
|
||||
A57UnitL,
|
||||
A57UnitV, A57UnitV,
|
||||
A57UnitV, A57UnitV]> {
|
||||
let Latency = 9;
|
||||
let NumMicroOps = 6;
|
||||
}
|
||||
def A57Write_9cyc_2L_4V : SchedWriteRes<[A57UnitL, A57UnitL,
|
||||
A57UnitV, A57UnitV,
|
||||
A57UnitV, A57UnitV]> {
|
||||
let Latency = 9;
|
||||
let NumMicroOps = 6;
|
||||
}
|
||||
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// Define Generic 7 micro-op types
|
||||
|
||||
def A57Write_10cyc_3L_4V : SchedWriteRes<[A57UnitL, A57UnitL, A57UnitL,
|
||||
A57UnitV, A57UnitV,
|
||||
A57UnitV, A57UnitV]> {
|
||||
let Latency = 10;
|
||||
let NumMicroOps = 7;
|
||||
}
|
||||
def A57Write_4cyc_1I_4S_2V : SchedWriteRes<[A57UnitI,
|
||||
A57UnitS, A57UnitS,
|
||||
A57UnitS, A57UnitS,
|
||||
A57UnitV, A57UnitV]> {
|
||||
let Latency = 4;
|
||||
let NumMicroOps = 7;
|
||||
}
|
||||
def A57Write_6cyc_1I_6S : SchedWriteRes<[A57UnitI,
|
||||
A57UnitS, A57UnitS, A57UnitS,
|
||||
A57UnitS, A57UnitS, A57UnitS]> {
|
||||
let Latency = 6;
|
||||
let NumMicroOps = 7;
|
||||
}
|
||||
def A57Write_9cyc_1I_2L_4V : SchedWriteRes<[A57UnitI,
|
||||
A57UnitL, A57UnitL,
|
||||
A57UnitV, A57UnitV,
|
||||
A57UnitV, A57UnitV]> {
|
||||
let Latency = 9;
|
||||
let NumMicroOps = 7;
|
||||
}
|
||||
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// Define Generic 8 micro-op types
|
||||
|
||||
def A57Write_10cyc_1I_3L_4V : SchedWriteRes<[A57UnitI,
|
||||
A57UnitL, A57UnitL, A57UnitL,
|
||||
A57UnitV, A57UnitV,
|
||||
A57UnitV, A57UnitV]> {
|
||||
let Latency = 10;
|
||||
let NumMicroOps = 8;
|
||||
}
|
||||
def A57Write_11cyc_4L_4V : SchedWriteRes<[A57UnitL, A57UnitL,
|
||||
A57UnitL, A57UnitL,
|
||||
A57UnitV, A57UnitV,
|
||||
A57UnitV, A57UnitV]> {
|
||||
let Latency = 11;
|
||||
let NumMicroOps = 8;
|
||||
}
|
||||
def A57Write_8cyc_8S : SchedWriteRes<[A57UnitS, A57UnitS,
|
||||
A57UnitS, A57UnitS,
|
||||
A57UnitS, A57UnitS,
|
||||
A57UnitS, A57UnitS]> {
|
||||
let Latency = 8;
|
||||
let NumMicroOps = 8;
|
||||
}
|
||||
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// Define Generic 9 micro-op types
|
||||
|
||||
def A57Write_8cyc_1I_8S : SchedWriteRes<[A57UnitI,
|
||||
A57UnitS, A57UnitS,
|
||||
A57UnitS, A57UnitS,
|
||||
A57UnitS, A57UnitS,
|
||||
A57UnitS, A57UnitS]> {
|
||||
let Latency = 8;
|
||||
let NumMicroOps = 9;
|
||||
}
|
||||
def A57Write_11cyc_1I_4L_4V : SchedWriteRes<[A57UnitI,
|
||||
A57UnitL, A57UnitL,
|
||||
A57UnitL, A57UnitL,
|
||||
A57UnitV, A57UnitV,
|
||||
A57UnitV, A57UnitV]> {
|
||||
let Latency = 11;
|
||||
let NumMicroOps = 9;
|
||||
}
|
||||
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// Define Generic 10 micro-op types
|
||||
|
||||
def A57Write_6cyc_6S_4V : SchedWriteRes<[A57UnitS, A57UnitS, A57UnitS,
|
||||
A57UnitS, A57UnitS, A57UnitS,
|
||||
A57UnitV, A57UnitV,
|
||||
A57UnitV, A57UnitV]> {
|
||||
let Latency = 6;
|
||||
let NumMicroOps = 10;
|
||||
}
|
||||
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// Define Generic 11 micro-op types
|
||||
|
||||
def A57Write_6cyc_1I_6S_4V : SchedWriteRes<[A57UnitI,
|
||||
A57UnitS, A57UnitS, A57UnitS,
|
||||
A57UnitS, A57UnitS, A57UnitS,
|
||||
A57UnitV, A57UnitV,
|
||||
A57UnitV, A57UnitV]> {
|
||||
let Latency = 6;
|
||||
let NumMicroOps = 11;
|
||||
}
|
||||
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// Define Generic 12 micro-op types
|
||||
|
||||
def A57Write_8cyc_8S_4V : SchedWriteRes<[A57UnitS, A57UnitS, A57UnitS, A57UnitS,
|
||||
A57UnitS, A57UnitS, A57UnitS, A57UnitS,
|
||||
A57UnitV, A57UnitV,
|
||||
A57UnitV, A57UnitV]> {
|
||||
let Latency = 8;
|
||||
let NumMicroOps = 12;
|
||||
}
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// Define Generic 13 micro-op types
|
||||
|
||||
def A57Write_8cyc_1I_8S_4V : SchedWriteRes<[A57UnitI,
|
||||
A57UnitS, A57UnitS, A57UnitS,
|
||||
A57UnitS, A57UnitS, A57UnitS,
|
||||
A57UnitS, A57UnitS,
|
||||
A57UnitV, A57UnitV,
|
||||
A57UnitV, A57UnitV]> {
|
||||
let Latency = 8;
|
||||
let NumMicroOps = 13;
|
||||
}
|
||||
|
||||
|
|
@ -0,0 +1,112 @@
|
|||
; REQUIRES: asserts
|
||||
;
|
||||
; The Cortext-A57 machine model will avoid scheduling load instructions in
|
||||
; succession because loads on the A57 have a latency of 4 cycles and they all
|
||||
; issue to the same pipeline. Instead, it will move other instructions between
|
||||
; the loads to avoid unnecessary stalls. The generic machine model schedules 4
|
||||
; loads consecutively for this case and will cause stalls.
|
||||
;
|
||||
; RUN: llc < %s -mtriple=arm64-linux-gnu -mcpu=cortex-a57 -enable-misched -verify-misched -debug-only=misched -o - 2>&1 > /dev/null | FileCheck %s
|
||||
; CHECK: ********** MI Scheduling **********
|
||||
; CHECK: main:BB#2
|
||||
; CHECK LDR
|
||||
; CHECK Latency : 4
|
||||
; CHECK: *** Final schedule for BB#2 ***
|
||||
; CHECK: LDR
|
||||
; CHECK: LDR
|
||||
; CHECK-NOT: LDR
|
||||
; CHECK: {{.*}}
|
||||
; CHECK: ********** MI Scheduling **********
|
||||
|
||||
@main.x = private unnamed_addr constant [8 x i32] [i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1], align 4
|
||||
@main.y = private unnamed_addr constant [8 x i32] [i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2], align 4
|
||||
|
||||
; Function Attrs: nounwind
|
||||
define i32 @main() #0 {
|
||||
entry:
|
||||
%retval = alloca i32, align 4
|
||||
%x = alloca [8 x i32], align 4
|
||||
%y = alloca [8 x i32], align 4
|
||||
%i = alloca i32, align 4
|
||||
%xx = alloca i32, align 4
|
||||
%yy = alloca i32, align 4
|
||||
store i32 0, i32* %retval
|
||||
%0 = bitcast [8 x i32]* %x to i8*
|
||||
call void @llvm.memcpy.p0i8.p0i8.i64(i8* %0, i8* bitcast ([8 x i32]* @main.x to i8*), i64 32, i32 4, i1 false)
|
||||
%1 = bitcast [8 x i32]* %y to i8*
|
||||
call void @llvm.memcpy.p0i8.p0i8.i64(i8* %1, i8* bitcast ([8 x i32]* @main.y to i8*), i64 32, i32 4, i1 false)
|
||||
store i32 0, i32* %xx, align 4
|
||||
store i32 0, i32* %yy, align 4
|
||||
store i32 0, i32* %i, align 4
|
||||
br label %for.cond
|
||||
|
||||
for.cond: ; preds = %for.inc, %entry
|
||||
%2 = load i32* %i, align 4
|
||||
%cmp = icmp slt i32 %2, 8
|
||||
br i1 %cmp, label %for.body, label %for.end
|
||||
|
||||
for.body: ; preds = %for.cond
|
||||
%3 = load i32* %yy, align 4
|
||||
%4 = load i32* %i, align 4
|
||||
%idxprom = sext i32 %4 to i64
|
||||
%arrayidx = getelementptr inbounds [8 x i32]* %x, i32 0, i64 %idxprom
|
||||
%5 = load i32* %arrayidx, align 4
|
||||
%add = add nsw i32 %5, 1
|
||||
store i32 %add, i32* %xx, align 4
|
||||
%6 = load i32* %xx, align 4
|
||||
%add1 = add nsw i32 %6, 12
|
||||
store i32 %add1, i32* %xx, align 4
|
||||
%7 = load i32* %xx, align 4
|
||||
%add2 = add nsw i32 %7, 23
|
||||
store i32 %add2, i32* %xx, align 4
|
||||
%8 = load i32* %xx, align 4
|
||||
%add3 = add nsw i32 %8, 34
|
||||
store i32 %add3, i32* %xx, align 4
|
||||
%9 = load i32* %i, align 4
|
||||
%idxprom4 = sext i32 %9 to i64
|
||||
%arrayidx5 = getelementptr inbounds [8 x i32]* %y, i32 0, i64 %idxprom4
|
||||
%10 = load i32* %arrayidx5, align 4
|
||||
|
||||
%add4 = add nsw i32 %9, %add
|
||||
%add5 = add nsw i32 %10, %add1
|
||||
%add6 = add nsw i32 %add4, %add5
|
||||
|
||||
%add7 = add nsw i32 %9, %add3
|
||||
%add8 = add nsw i32 %10, %add4
|
||||
%add9 = add nsw i32 %add7, %add8
|
||||
|
||||
%add10 = add nsw i32 %9, %add6
|
||||
%add11 = add nsw i32 %10, %add7
|
||||
%add12 = add nsw i32 %add10, %add11
|
||||
|
||||
%add13 = add nsw i32 %9, %add9
|
||||
%add14 = add nsw i32 %10, %add10
|
||||
%add15 = add nsw i32 %add13, %add14
|
||||
|
||||
store i32 %add15, i32* %xx, align 4
|
||||
|
||||
%div = sdiv i32 %4, %5
|
||||
|
||||
store i32 %div, i32* %yy, align 4
|
||||
|
||||
br label %for.inc
|
||||
|
||||
for.inc: ; preds = %for.body
|
||||
%11 = load i32* %i, align 4
|
||||
%inc = add nsw i32 %11, 1
|
||||
store i32 %inc, i32* %i, align 4
|
||||
br label %for.cond
|
||||
|
||||
for.end: ; preds = %for.cond
|
||||
%12 = load i32* %xx, align 4
|
||||
%13 = load i32* %yy, align 4
|
||||
%add67 = add nsw i32 %12, %13
|
||||
ret i32 %add67
|
||||
}
|
||||
|
||||
|
||||
; Function Attrs: nounwind
|
||||
declare void @llvm.memcpy.p0i8.p0i8.i64(i8* nocapture, i8* nocapture readonly, i64, i32, i1) #1
|
||||
|
||||
attributes #0 = { nounwind "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" }
|
||||
attributes #1 = { nounwind }
|
||||
Loading…
Reference in New Issue