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[AArch64] Add fallback in FastISel fp16 conversions 

Summary:
- Fix assertion failures on F16 to/from int types in FastISel by falling
  back to regular ISel
- Add a testcase of various conversion cases with FastISel (-O0)

Reviewers: kristof.beyls, jmolloy, SjoerdMeijer

Reviewed By: SjoerdMeijer

Subscribers: SjoerdMeijer, llvm-commits, srhines, pirama, aemerson, rengolin, javed.absar, kristof.beyls

Differential Revision: https://reviews.llvm.org/D33734

llvm-svn: 305127
This commit is contained in:
I-Jui (Ray) Sung 2017-06-09 22:40:50 +00:00
parent 01e4a7f29b
commit 21fde385fa
2 changed files with 136 additions and 1 deletions
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6
llvm/lib/Target/AArch64/AArch64FastISel.cpp
View File

@ -2827,7 +2827,7 @@ bool AArch64FastISel::selectFPToInt(const Instruction *I, bool Signed) {
return false;
EVT SrcVT = TLI.getValueType(DL, I->getOperand(0)->getType(), true);
if (SrcVT == MVT::f128)
if (SrcVT == MVT::f128 || SrcVT == MVT::f16)
return false;
unsigned Opc;
@ -2854,6 +2854,10 @@ bool AArch64FastISel::selectIntToFP(const Instruction *I, bool Signed) {
MVT DestVT;
if (!isTypeLegal(I->getType(), DestVT) || DestVT.isVector())
return false;
// Let regular ISEL handle FP16
if (DestVT == MVT::f16)
return false;
assert((DestVT == MVT::f32 || DestVT == MVT::f64) &&
"Unexpected value type.");

131
llvm/test/CodeGen/AArch64/arm64-fast-isel-conversion-fallback.ll Normal file
View File

@ -0,0 +1,131 @@
; RUN: llc -O0 -verify-machineinstrs -mtriple=arm64-eabi < %s | FileCheck --enable-var-scope %s
; Test fptosi
define i32 @fptosi_wh(half %a) nounwind ssp {
entry:
; CHECK-LABEL: fptosi_wh
; CHECK: fcvt s1, h0
; CHECK: fcvtzs [[REG:w[0-9]+]], s1
; CHECK: mov w0, [[REG]]
%conv = fptosi half %a to i32
ret i32 %conv
}
; Test fptoui
define i32 @fptoui_swh(half %a) nounwind ssp {
entry:
; CHECK-LABEL: fptoui_swh
; CHECK: fcvt s1, h0
; CHECK: fcvtzu [[REG:w[0-9]+]], s1
; CHECK: mov w0, [[REG]]
%conv = fptoui half %a to i32
ret i32 %conv
}
; Test sitofp
define half @sitofp_hw_i1(i1 %a) nounwind ssp {
entry:
; CHECK-LABEL: sitofp_hw_i1
; CHECK: sbfx w0, w0, #0, #1
; CHECK: scvtf s0, w0
; CHECK: fcvt h0, s0
%conv = sitofp i1 %a to half
ret half %conv
}
; Test sitofp
define half @sitofp_hw_i8(i8 %a) nounwind ssp {
entry:
; CHECK-LABEL: sitofp_hw_i8
; CHECK: sxtb w0, w0
; CHECK: scvtf s0, w0
; CHECK: fcvt h0, s0
%conv = sitofp i8 %a to half
ret half %conv
}
; Test sitofp
define half @sitofp_hw_i16(i16 %a) nounwind ssp {
entry:
; CHECK-LABEL: sitofp_hw_i16
; CHECK: sxth w0, w0
; CHECK: scvtf s0, w0
; CHECK: fcvt h0, s0
%conv = sitofp i16 %a to half
ret half %conv
}
; Test sitofp
define half @sitofp_hw_i32(i32 %a) nounwind ssp {
entry:
; CHECK-LABEL: sitofp_hw_i32
; CHECK: scvtf s0, w0
; CHECK: fcvt h0, s0
%conv = sitofp i32 %a to half
ret half %conv
}
; Test sitofp
define half @sitofp_hx(i64 %a) nounwind ssp {
entry:
; CHECK-LABEL: sitofp_hx
; CHECK: scvtf s0, x0
; CHECK: fcvt h0, s0
%conv = sitofp i64 %a to half
ret half %conv
}
; Test uitofp
define half @uitofp_hw_i1(i1 %a) nounwind ssp {
entry:
; CHECK-LABEL: uitofp_hw_i1
; CHECK: and w0, w0, #0x1
; CHECK: ucvtf s0, w0
; CHECK: fcvt h0, s0
%conv = uitofp i1 %a to half
ret half %conv
}
; Test uitofp
define half @uitofp_hw_i8(i8 %a) nounwind ssp {
entry:
; CHECK-LABEL: uitofp_hw_i8
; CHECK: and w0, w0, #0xff
; CHECK: ucvtf s0, w0
; CHECK: fcvt h0, s0
%conv = uitofp i8 %a to half
ret half %conv
}
; Test uitofp
define half @uitofp_hw_i16(i16 %a) nounwind ssp {
entry:
; CHECK-LABEL: uitofp_hw_i16
; CHECK: and w0, w0, #0xffff
; CHECK: ucvtf s0, w0
; CHECK: fcvt h0, s0
%conv = uitofp i16 %a to half
ret half %conv
}
; Test uitofp
define half @uitofp_hw_i32(i32 %a) nounwind ssp {
entry:
; CHECK-LABEL: uitofp_hw_i32
; CHECK: ucvtf s0, w0
; CHECK: fcvt h0, s0
%conv = uitofp i32 %a to half
ret half %conv
}
; Test uitofp
define half @uitofp_hx(i64 %a) nounwind ssp {
entry:
; CHECK-LABEL: uitofp_hx
; CHECK: ucvtf s0, x0
; CHECK: fcvt h0, s0
%conv = uitofp i64 %a to half
ret half %conv
}