forked from OSchip/llvm-project
[Hexagon] Adding XTYPE/ALU vector instructions. Organizing test files.
llvm-svn: 227598
This commit is contained in:
Colin LeMahieu
parent
07b7c03805
commit
21fbc94777
|
|
@ -876,14 +876,14 @@ class T_VectALU_64 <string opc, bits<3> majOp, bits<3> minOp,
|
|||
|
||||
// ALU64 - Vector add
|
||||
// Rdd=vadd[u][bhw](Rss,Rtt)
|
||||
let Itinerary = ALU64_tc_1_SLOT23 in {
|
||||
let Itinerary = ALU64_tc_1_SLOT23, isCodeGenOnly = 0 in {
|
||||
def A2_vaddub : T_VectALU_64 < "vaddub", 0b000, 0b000, 0, 0, 0, 0>;
|
||||
def A2_vaddh : T_VectALU_64 < "vaddh", 0b000, 0b010, 0, 0, 0, 0>;
|
||||
def A2_vaddw : T_VectALU_64 < "vaddw", 0b000, 0b101, 0, 0, 0, 0>;
|
||||
}
|
||||
|
||||
// Rdd=vadd[u][bhw](Rss,Rtt):sat
|
||||
let Defs = [USR_OVF] in {
|
||||
let Defs = [USR_OVF], isCodeGenOnly = 0 in {
|
||||
def A2_vaddubs : T_VectALU_64 < "vaddub", 0b000, 0b001, 1, 0, 0, 0>;
|
||||
def A2_vaddhs : T_VectALU_64 < "vaddh", 0b000, 0b011, 1, 0, 0, 0>;
|
||||
def A2_vadduhs : T_VectALU_64 < "vadduh", 0b000, 0b100, 1, 0, 0, 0>;
|
||||
|
|
@ -892,7 +892,7 @@ let Defs = [USR_OVF] in {
|
|||
|
||||
// ALU64 - Vector average
|
||||
// Rdd=vavg[u][bhw](Rss,Rtt)
|
||||
let Itinerary = ALU64_tc_1_SLOT23 in {
|
||||
let Itinerary = ALU64_tc_1_SLOT23, isCodeGenOnly = 0 in {
|
||||
def A2_vavgub : T_VectALU_64 < "vavgub", 0b010, 0b000, 0, 0, 0, 0>;
|
||||
def A2_vavgh : T_VectALU_64 < "vavgh", 0b010, 0b010, 0, 0, 0, 0>;
|
||||
def A2_vavguh : T_VectALU_64 < "vavguh", 0b010, 0b101, 0, 0, 0, 0>;
|
||||
|
|
@ -901,23 +901,27 @@ let Itinerary = ALU64_tc_1_SLOT23 in {
|
|||
}
|
||||
|
||||
// Rdd=vavg[u][bhw](Rss,Rtt)[:rnd|:crnd]
|
||||
let isCodeGenOnly = 0 in {
|
||||
def A2_vavgubr : T_VectALU_64 < "vavgub", 0b010, 0b001, 0, 1, 0, 0>;
|
||||
def A2_vavghr : T_VectALU_64 < "vavgh", 0b010, 0b011, 0, 1, 0, 0>;
|
||||
def A2_vavghcr : T_VectALU_64 < "vavgh", 0b010, 0b100, 0, 0, 1, 0>;
|
||||
def A2_vavguhr : T_VectALU_64 < "vavguh", 0b010, 0b110, 0, 1, 0, 0>;
|
||||
}
|
||||
|
||||
let isCodeGenOnly = 0 in {
|
||||
def A2_vavgwr : T_VectALU_64 < "vavgw", 0b011, 0b001, 0, 1, 0, 0>;
|
||||
def A2_vavgwcr : T_VectALU_64 < "vavgw", 0b011, 0b010, 0, 0, 1, 0>;
|
||||
def A2_vavguwr : T_VectALU_64 < "vavguw", 0b011, 0b100, 0, 1, 0, 0>;
|
||||
}
|
||||
|
||||
// Rdd=vnavg[bh](Rss,Rtt)
|
||||
let Itinerary = ALU64_tc_1_SLOT23 in {
|
||||
let Itinerary = ALU64_tc_1_SLOT23, isCodeGenOnly = 0 in {
|
||||
def A2_vnavgh : T_VectALU_64 < "vnavgh", 0b100, 0b000, 0, 0, 0, 1>;
|
||||
def A2_vnavgw : T_VectALU_64 < "vnavgw", 0b100, 0b011, 0, 0, 0, 1>;
|
||||
}
|
||||
|
||||
// Rdd=vnavg[bh](Rss,Rtt)[:rnd|:crnd]:sat
|
||||
let Defs = [USR_OVF] in {
|
||||
let Defs = [USR_OVF], isCodeGenOnly = 0 in {
|
||||
def A2_vnavghr : T_VectALU_64 < "vnavgh", 0b100, 0b001, 1, 1, 0, 1>;
|
||||
def A2_vnavghcr : T_VectALU_64 < "vnavgh", 0b100, 0b010, 1, 0, 1, 1>;
|
||||
def A2_vnavgwr : T_VectALU_64 < "vnavgw", 0b100, 0b100, 1, 1, 0, 1>;
|
||||
|
|
@ -925,14 +929,14 @@ let Defs = [USR_OVF] in {
|
|||
}
|
||||
|
||||
// Rdd=vsub[u][bh](Rss,Rtt)
|
||||
let Itinerary = ALU64_tc_1_SLOT23 in {
|
||||
let Itinerary = ALU64_tc_1_SLOT23, isCodeGenOnly = 0 in {
|
||||
def A2_vsubub : T_VectALU_64 < "vsubub", 0b001, 0b000, 0, 0, 0, 1>;
|
||||
def A2_vsubh : T_VectALU_64 < "vsubh", 0b001, 0b010, 0, 0, 0, 1>;
|
||||
def A2_vsubw : T_VectALU_64 < "vsubw", 0b001, 0b101, 0, 0, 0, 1>;
|
||||
}
|
||||
|
||||
// Rdd=vsub[u][bh](Rss,Rtt):sat
|
||||
let Defs = [USR_OVF] in {
|
||||
let Defs = [USR_OVF], isCodeGenOnly = 0 in {
|
||||
def A2_vsububs : T_VectALU_64 < "vsubub", 0b001, 0b001, 1, 0, 0, 1>;
|
||||
def A2_vsubhs : T_VectALU_64 < "vsubh", 0b001, 0b011, 1, 0, 0, 1>;
|
||||
def A2_vsubuhs : T_VectALU_64 < "vsubuh", 0b001, 0b100, 1, 0, 0, 1>;
|
||||
|
|
@ -940,20 +944,24 @@ let Defs = [USR_OVF] in {
|
|||
}
|
||||
|
||||
// Rdd=vmax[u][bhw](Rss,Rtt)
|
||||
let isCodeGenOnly = 0 in {
|
||||
def A2_vmaxb : T_VectALU_64 < "vmaxb", 0b110, 0b110, 0, 0, 0, 1>;
|
||||
def A2_vmaxub : T_VectALU_64 < "vmaxub", 0b110, 0b000, 0, 0, 0, 1>;
|
||||
def A2_vmaxh : T_VectALU_64 < "vmaxh", 0b110, 0b001, 0, 0, 0, 1>;
|
||||
def A2_vmaxuh : T_VectALU_64 < "vmaxuh", 0b110, 0b010, 0, 0, 0, 1>;
|
||||
def A2_vmaxw : T_VectALU_64 < "vmaxw", 0b110, 0b011, 0, 0, 0, 1>;
|
||||
def A2_vmaxuw : T_VectALU_64 < "vmaxuw", 0b101, 0b101, 0, 0, 0, 1>;
|
||||
}
|
||||
|
||||
// Rdd=vmin[u][bhw](Rss,Rtt)
|
||||
let isCodeGenOnly = 0 in {
|
||||
def A2_vminb : T_VectALU_64 < "vminb", 0b110, 0b111, 0, 0, 0, 1>;
|
||||
def A2_vminub : T_VectALU_64 < "vminub", 0b101, 0b000, 0, 0, 0, 1>;
|
||||
def A2_vminh : T_VectALU_64 < "vminh", 0b101, 0b001, 0, 0, 0, 1>;
|
||||
def A2_vminuh : T_VectALU_64 < "vminuh", 0b101, 0b010, 0, 0, 0, 1>;
|
||||
def A2_vminw : T_VectALU_64 < "vminw", 0b101, 0b011, 0, 0, 0, 1>;
|
||||
def A2_vminuw : T_VectALU_64 < "vminuw", 0b101, 0b100, 0, 0, 0, 1>;
|
||||
}
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// Template class for vector compare
|
||||
|
|
@ -2099,6 +2107,31 @@ let hasNewValue = 1, accessSize = WordAccess, opNewValue = 0, isCodeGenOnly = 0
|
|||
def L2_loadw_locked : T_load_locked <"memw_locked", IntRegs>;
|
||||
let accessSize = DoubleWordAccess, isCodeGenOnly = 0 in
|
||||
def L4_loadd_locked : T_load_locked <"memd_locked", DoubleRegs>;
|
||||
|
||||
// S[24]_store[wd]_locked: Store word/double conditionally.
|
||||
let isSoloAX = 1, isPredicateLate = 1 in
|
||||
class T_store_locked <string mnemonic, RegisterClass RC>
|
||||
: ST0Inst <(outs PredRegs:$Pd), (ins IntRegs:$Rs, RC:$Rt),
|
||||
mnemonic#"($Rs, $Pd) = $Rt"> {
|
||||
bits<2> Pd;
|
||||
bits<5> Rs;
|
||||
bits<5> Rt;
|
||||
|
||||
let IClass = 0b1010;
|
||||
let Inst{27-23} = 0b00001;
|
||||
let Inst{22} = !if (!eq(mnemonic, "memw_locked"), 0b0, 0b1);
|
||||
let Inst{21} = 0b1;
|
||||
let Inst{20-16} = Rs;
|
||||
let Inst{12-8} = Rt;
|
||||
let Inst{1-0} = Pd;
|
||||
}
|
||||
|
||||
let accessSize = WordAccess, isCodeGenOnly = 0 in
|
||||
def S2_storew_locked : T_store_locked <"memw_locked", IntRegs>;
|
||||
|
||||
let accessSize = DoubleWordAccess, isCodeGenOnly = 0 in
|
||||
def S4_stored_locked : T_store_locked <"memd_locked", DoubleRegs>;
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// Bit-reversed loads with auto-increment register
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
|
@ -2474,6 +2507,9 @@ class T_MType_rr2 <string mnemonic, bits<3> MajOp, bits<3> MinOp,
|
|||
bit isSat = 0, bit isRnd = 0, string op2str = "" >
|
||||
: T_MType_mpy<mnemonic, 0b1101, IntRegs, MajOp, MinOp, isSat, isRnd, op2str>;
|
||||
|
||||
let isCodeGenOnly = 0 in
|
||||
def M2_vradduh : T_MType_dd <"vradduh", 0b000, 0b001, 0, 0>;
|
||||
|
||||
let CextOpcode = "mpyi", InputType = "reg", isCodeGenOnly = 0 in
|
||||
def M2_mpyi : T_MType_rr1 <"mpyi", 0b000, 0b000>, ImmRegRel;
|
||||
|
||||
|
|
@ -2492,6 +2528,7 @@ def M2_hmmpyl_rs1 : T_MType_rr2 <"mpy", 0b111, 0b100, 1, 1, ".l">;
|
|||
|
||||
// V4 Instructions
|
||||
let isCodeGenOnly = 0 in {
|
||||
def M2_vraddh : T_MType_dd <"vraddh", 0b001, 0b111, 0>;
|
||||
def M2_mpysu_up : T_MType_rr1 <"mpysu", 0b011, 0b001, 0>;
|
||||
def M2_mpy_up_s1 : T_MType_rr1 <"mpy", 0b101, 0b010, 0>;
|
||||
def M2_mpy_up_s1_sat : T_MType_rr1 <"mpy", 0b111, 0b000, 1>;
|
||||
|
|
@ -2649,6 +2686,81 @@ def : T_MType_acc_pat1 <M2_macsin, mul, sub, u8ExtPred>;
|
|||
|
||||
def : T_MType_acc_pat1 <M2_naccii, add, sub, s8_16ExtPred>;
|
||||
def : T_MType_acc_pat2 <M2_nacci, add, sub>;
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// Template Class -- XType Vector Instructions
|
||||
//===----------------------------------------------------------------------===//
|
||||
class T_XTYPE_Vect < string opc, bits<3> MajOp, bits<3> MinOp, bit isConj >
|
||||
: MInst <(outs DoubleRegs:$Rdd), (ins DoubleRegs:$Rss, DoubleRegs:$Rtt),
|
||||
"$Rdd = "#opc#"($Rss, $Rtt"#!if(isConj,"*)",")"),
|
||||
[] > {
|
||||
bits<5> Rdd;
|
||||
bits<5> Rss;
|
||||
bits<5> Rtt;
|
||||
|
||||
let IClass = 0b1110;
|
||||
|
||||
let Inst{27-24} = 0b1000;
|
||||
let Inst{23-21} = MajOp;
|
||||
let Inst{7-5} = MinOp;
|
||||
let Inst{4-0} = Rdd;
|
||||
let Inst{20-16} = Rss;
|
||||
let Inst{12-8} = Rtt;
|
||||
}
|
||||
|
||||
class T_XTYPE_Vect_acc < string opc, bits<3> MajOp, bits<3> MinOp, bit isConj >
|
||||
: MInst <(outs DoubleRegs:$Rdd),
|
||||
(ins DoubleRegs:$dst2, DoubleRegs:$Rss, DoubleRegs:$Rtt),
|
||||
"$Rdd += "#opc#"($Rss, $Rtt"#!if(isConj,"*)",")"),
|
||||
[], "$dst2 = $Rdd",M_tc_3x_SLOT23 > {
|
||||
bits<5> Rdd;
|
||||
bits<5> Rss;
|
||||
bits<5> Rtt;
|
||||
|
||||
let IClass = 0b1110;
|
||||
|
||||
let Inst{27-24} = 0b1010;
|
||||
let Inst{23-21} = MajOp;
|
||||
let Inst{7-5} = MinOp;
|
||||
let Inst{4-0} = Rdd;
|
||||
let Inst{20-16} = Rss;
|
||||
let Inst{12-8} = Rtt;
|
||||
}
|
||||
|
||||
class T_XTYPE_Vect_diff < bits<3> MajOp, string opc >
|
||||
: MInst <(outs DoubleRegs:$Rdd), (ins DoubleRegs:$Rtt, DoubleRegs:$Rss),
|
||||
"$Rdd = "#opc#"($Rtt, $Rss)",
|
||||
[], "",M_tc_2_SLOT23 > {
|
||||
bits<5> Rdd;
|
||||
bits<5> Rss;
|
||||
bits<5> Rtt;
|
||||
|
||||
let IClass = 0b1110;
|
||||
|
||||
let Inst{27-24} = 0b1000;
|
||||
let Inst{23-21} = MajOp;
|
||||
let Inst{7-5} = 0b000;
|
||||
let Inst{4-0} = Rdd;
|
||||
let Inst{20-16} = Rss;
|
||||
let Inst{12-8} = Rtt;
|
||||
}
|
||||
|
||||
// Vector reduce add unsigned bytes: Rdd32=vrmpybu(Rss32,Rtt32)
|
||||
let isCodeGenOnly = 0 in {
|
||||
def A2_vraddub: T_XTYPE_Vect <"vraddub", 0b010, 0b001, 0>;
|
||||
def A2_vraddub_acc: T_XTYPE_Vect_acc <"vraddub", 0b010, 0b001, 0>;
|
||||
}
|
||||
|
||||
// Vector sum of absolute differences unsigned bytes: Rdd=vrsadub(Rss,Rtt)
|
||||
let isCodeGenOnly = 0 in {
|
||||
def A2_vrsadub: T_XTYPE_Vect <"vrsadub", 0b010, 0b010, 0>;
|
||||
def A2_vrsadub_acc: T_XTYPE_Vect_acc <"vrsadub", 0b010, 0b010, 0>;
|
||||
}
|
||||
|
||||
// Vector absolute difference: Rdd=vabsdiffh(Rtt,Rss)
|
||||
let isCodeGenOnly = 0 in
|
||||
def M2_vabsdiffh: T_XTYPE_Vect_diff<0b011, "vabsdiffh">;
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// Template Class -- Multiply signed/unsigned halfwords with and without
|
||||
// saturation and rounding
|
||||
|
|
@ -3629,6 +3741,19 @@ def S2_interleave : T_S2op_3 <"interleave", 0b11, 0b101>;
|
|||
def S2_deinterleave : T_S2op_3 <"deinterleave", 0b11, 0b100>;
|
||||
}
|
||||
|
||||
// Vector absolute value halfwords with and without saturation
|
||||
// Rdd64=vabsh(Rss64)[:sat]
|
||||
let isCodeGenOnly = 0 in {
|
||||
def A2_vabsh : T_S2op_3 <"vabsh", 0b01, 0b100>;
|
||||
def A2_vabshsat : T_S2op_3 <"vabsh", 0b01, 0b101, 1>;
|
||||
}
|
||||
|
||||
// Vector absolute value words with and without saturation
|
||||
let isCodeGenOnly = 0 in {
|
||||
def A2_vabsw : T_S2op_3 <"vabsw", 0b01, 0b110>;
|
||||
def A2_vabswsat : T_S2op_3 <"vabsw", 0b01, 0b111, 1>;
|
||||
}
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// STYPE/BIT +
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
|
|
|||
|
|
@ -1768,7 +1768,29 @@ def M4_xor_xacc
|
|||
let Inst{12-8} = Rtt;
|
||||
let Inst{4-0} = Rxx;
|
||||
}
|
||||
|
||||
|
||||
|
||||
// Vector reduce conditional negate halfwords
|
||||
let hasSideEffects = 0, isCodeGenOnly = 0 in
|
||||
def S2_vrcnegh
|
||||
: SInst <(outs DoubleRegs:$Rxx),
|
||||
(ins DoubleRegs:$dst2, DoubleRegs:$Rss, IntRegs:$Rt),
|
||||
"$Rxx += vrcnegh($Rss, $Rt)", [],
|
||||
"$dst2 = $Rxx", S_3op_tc_3x_SLOT23> {
|
||||
bits<5> Rxx;
|
||||
bits<5> Rss;
|
||||
bits<5> Rt;
|
||||
|
||||
let IClass = 0b1100;
|
||||
|
||||
let Inst{27-21} = 0b1011001;
|
||||
let Inst{20-16} = Rss;
|
||||
let Inst{13} = 0b1;
|
||||
let Inst{12-8} = Rt;
|
||||
let Inst{7-5} = 0b111;
|
||||
let Inst{4-0} = Rxx;
|
||||
}
|
||||
|
||||
// Split bitfield
|
||||
let isCodeGenOnly = 0 in
|
||||
def A4_bitspliti : T_S2op_2_di <"bitsplit", 0b110, 0b100>;
|
||||
|
|
@ -2246,6 +2268,10 @@ defm S4_ori : T_ShiftOperate<"or", or, 0b01, ALU64_tc_1_SLOT23>;
|
|||
let isCodeGenOnly = 0 in
|
||||
defm S4_subi : T_ShiftOperate<"sub", sub, 0b11, ALU64_tc_1_SLOT23>;
|
||||
|
||||
// Vector conditional negate
|
||||
// Rdd=vcnegh(Rss,Rt)
|
||||
let Defs = [USR_OVF], Itinerary = S_3op_tc_2_SLOT23, isCodeGenOnly = 0 in
|
||||
def S2_vcnegh : T_S3op_shiftVect < "vcnegh", 0b11, 0b01>;
|
||||
|
||||
// Rd=[cround|round](Rs,Rt)
|
||||
let hasNewValue = 1, Itinerary = S_3op_tc_2_SLOT23, isCodeGenOnly = 0 in {
|
||||
|
|
@ -2285,6 +2311,52 @@ def A4_addp_c : T_S3op_carry < "add", 0b110 >;
|
|||
def A4_subp_c : T_S3op_carry < "sub", 0b111 >;
|
||||
}
|
||||
|
||||
let Itinerary = S_3op_tc_3_SLOT23, hasSideEffects = 0 in
|
||||
class T_S3op_6 <string mnemonic, bits<3> MinOp, bit isUnsigned>
|
||||
: SInst <(outs DoubleRegs:$Rxx),
|
||||
(ins DoubleRegs:$dst2, DoubleRegs:$Rss, IntRegs:$Ru),
|
||||
"$Rxx = "#mnemonic#"($Rss, $Ru)" ,
|
||||
[] , "$dst2 = $Rxx"> {
|
||||
bits<5> Rxx;
|
||||
bits<5> Rss;
|
||||
bits<5> Ru;
|
||||
|
||||
let IClass = 0b1100;
|
||||
|
||||
let Inst{27-21} = 0b1011001;
|
||||
let Inst{20-16} = Rss;
|
||||
let Inst{13} = isUnsigned;
|
||||
let Inst{12-8} = Rxx;
|
||||
let Inst{7-5} = MinOp;
|
||||
let Inst{4-0} = Ru;
|
||||
}
|
||||
|
||||
// Vector reduce maximum halfwords
|
||||
// Rxx=vrmax[u]h(Rss,Ru)
|
||||
let isCodeGenOnly = 0 in {
|
||||
def A4_vrmaxh : T_S3op_6 < "vrmaxh", 0b001, 0>;
|
||||
def A4_vrmaxuh : T_S3op_6 < "vrmaxuh", 0b001, 1>;
|
||||
}
|
||||
// Vector reduce maximum words
|
||||
// Rxx=vrmax[u]w(Rss,Ru)
|
||||
let isCodeGenOnly = 0 in {
|
||||
def A4_vrmaxw : T_S3op_6 < "vrmaxw", 0b010, 0>;
|
||||
def A4_vrmaxuw : T_S3op_6 < "vrmaxuw", 0b010, 1>;
|
||||
}
|
||||
// Vector reduce minimum halfwords
|
||||
// Rxx=vrmin[u]h(Rss,Ru)
|
||||
let isCodeGenOnly = 0 in {
|
||||
def A4_vrminh : T_S3op_6 < "vrminh", 0b101, 0>;
|
||||
def A4_vrminuh : T_S3op_6 < "vrminuh", 0b101, 1>;
|
||||
}
|
||||
|
||||
// Vector reduce minimum words
|
||||
// Rxx=vrmin[u]w(Rss,Ru)
|
||||
let isCodeGenOnly = 0 in {
|
||||
def A4_vrminw : T_S3op_6 < "vrminw", 0b110, 0>;
|
||||
def A4_vrminuw : T_S3op_6 < "vrminuw", 0b110, 1>;
|
||||
}
|
||||
|
||||
// Shift an immediate left by register amount.
|
||||
let hasNewValue = 1, hasSideEffects = 0, isCodeGenOnly = 0 in
|
||||
def S4_lsli: SInst <(outs IntRegs:$Rd), (ins s6Imm:$s6, IntRegs:$Rt),
|
||||
|
|
|
|||
|
|
@ -15,6 +15,14 @@
|
|||
// XTYPE/MPY
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
// Vector multiply bytes
|
||||
// Rdd=vmpyb[s]u(Rs,Rt)
|
||||
let Predicates = [HasV5T], isCodeGenOnly = 0 in {
|
||||
// Rd=vaddhub(Rss,Rtt):sat
|
||||
let hasNewValue = 1, opNewValue = 0 in
|
||||
def A5_vaddhubs: T_S3op_1 <"vaddhub", IntRegs, 0b01, 0b001, 0, 1>;
|
||||
}
|
||||
|
||||
let isCodeGenOnly = 0 in
|
||||
def S2_asr_i_p_rnd : S_2OpInstImm<"asr", 0b110, 0b111, u6Imm,
|
||||
[(set I64:$dst,
|
||||
|
|
|
|||
|
|
@ -1,5 +1,7 @@
|
|||
# RUN: llvm-mc --triple hexagon -disassemble < %s | FileCheck %s
|
||||
# RUN: llvm-mc -triple=hexagon -disassemble < %s | FileCheck %s
|
||||
# Hexagon Programmer's Reference Manual 11.6 MEMOP
|
||||
|
||||
# Operation on memory byte
|
||||
0x95 0xd9 0x11 0x3e
|
||||
# CHECK: memb(r17+#51) += r21
|
||||
0xb5 0xd9 0x11 0x3e
|
||||
|
|
@ -16,6 +18,8 @@
|
|||
# CHECK: memb(r17+#51) = clrbit(#21)
|
||||
0xf5 0xd9 0x11 0x3f
|
||||
# CHECK: memb(r17+#51) = setbit(#21)
|
||||
|
||||
# Operation on memory halfword
|
||||
0x95 0xd9 0x31 0x3e
|
||||
# CHECK: memh(r17+#102) += r21
|
||||
0xb5 0xd9 0x31 0x3e
|
||||
|
|
@ -32,6 +36,8 @@
|
|||
# CHECK: memh(r17+#102) = clrbit(#21)
|
||||
0xf5 0xd9 0x31 0x3f
|
||||
# CHECK: memh(r17+#102) = setbit(#21)
|
||||
|
||||
# Operation on memory word
|
||||
0x95 0xd9 0x51 0x3e
|
||||
# CHECK: memw(r17+#204) += r21
|
||||
0xb5 0xd9 0x51 0x3e
|
||||
|
|
|
|||
|
|
@ -1,5 +1,7 @@
|
|||
# RUN: llvm-mc --triple hexagon -disassemble < %s | FileCheck %s
|
||||
# RUN: llvm-mc -triple=hexagon -disassemble < %s | FileCheck %s
|
||||
# Hexagon Programmer's Reference Manual 11.7.1 NV/J
|
||||
|
||||
# Jump to address conditioned on new register value
|
||||
0x11 0x40 0x71 0x70 0x92 0xd5 0x02 0x20
|
||||
# CHECK: r17 = r17
|
||||
# CHECK-NEXT: if (cmp.eq(r2.new, r21)) jump:nt
|
||||
|
|
|
|||
|
|
@ -1,5 +1,7 @@
|
|||
# RUN: llvm-mc --triple hexagon -disassemble < %s | FileCheck %s
|
||||
# RUN: llvm-mc -triple=hexagon -disassemble < %s | FileCheck %s
|
||||
# Hexagon Programmer's Reference Manual 11.7.2 NV/ST
|
||||
|
||||
# Store new-value byte
|
||||
0x1f 0x40 0x7f 0x70 0x82 0xf5 0xb1 0x3b
|
||||
# CHECK: r31 = r31
|
||||
# CHECK-NEXT: memb(r17 + r21<<#3) = r2.new
|
||||
|
|
@ -21,6 +23,8 @@
|
|||
0x1f 0x40 0x7f 0x70 0x00 0xe2 0xb1 0xaf
|
||||
# CHECK: r31 = r31
|
||||
# CHECK-NEXT: memb(r17 ++ m1:brev) = r2.new
|
||||
|
||||
# Store new-value byte conditionally
|
||||
0x1f 0x40 0x7f 0x70 0xe2 0xf5 0xb1 0x34
|
||||
# CHECK: r31 = r31
|
||||
# CHECK-NEXT: if (p3) memb(r17+r21<<#3) = r2.new
|
||||
|
|
@ -64,6 +68,7 @@
|
|||
# CHECK-NEXT: r31 = r31
|
||||
# CHECK-NEXT: if (!p3.new) memb(r17++#5) = r2.new
|
||||
|
||||
# Store new-value halfword
|
||||
0x1f 0x40 0x7f 0x70 0x8a 0xf5 0xb1 0x3b
|
||||
# CHECK: r31 = r31
|
||||
# CHECK-NEXT: memh(r17 + r21<<#3) = r2.new
|
||||
|
|
@ -85,6 +90,8 @@
|
|||
0x1f 0x40 0x7f 0x70 0x00 0xea 0xb1 0xaf
|
||||
# CHECK: r31 = r31
|
||||
# CHECK-NEXT: memh(r17 ++ m1:brev) = r2.new
|
||||
|
||||
# Store new-value halfword conditionally
|
||||
0x1f 0x40 0x7f 0x70 0xea 0xf5 0xb1 0x34
|
||||
# CHECK: r31 = r31
|
||||
# CHECK-NEXT: if (p3) memh(r17+r21<<#3) = r2.new
|
||||
|
|
@ -128,6 +135,7 @@
|
|||
# CHECK-NEXT: r31 = r31
|
||||
# CHECK-NEXT: if (!p3.new) memh(r17++#10) = r2.new
|
||||
|
||||
# Store new-value word
|
||||
0x1f 0x40 0x7f 0x70 0x92 0xf5 0xb1 0x3b
|
||||
# CHECK: r31 = r31
|
||||
# CHECK-NEXT: memw(r17 + r21<<#3) = r2.new
|
||||
|
|
@ -149,6 +157,8 @@
|
|||
0x1f 0x40 0x7f 0x70 0x00 0xf2 0xb1 0xaf
|
||||
# CHECK: r31 = r31
|
||||
# CHECK-NEXT: memw(r17 ++ m1:brev) = r2.new
|
||||
|
||||
# Store new-value word conditionally
|
||||
0x1f 0x40 0x7f 0x70 0xf2 0xf5 0xb1 0x34
|
||||
# CHECK: r31 = r31
|
||||
# CHECK-NEXT: if (p3) memw(r17+r21<<#3) = r2.new
|
||||
|
|
|
|||
|
|
@ -1,5 +1,7 @@
|
|||
# RUN: llvm-mc --triple hexagon -disassemble < %s | FileCheck %s
|
||||
# RUN: llvm-mc -triple=hexagon -disassemble < %s | FileCheck %s
|
||||
# Hexagon Programmer's Reference Manual 11.8 ST
|
||||
|
||||
# Store doubleword
|
||||
0x9e 0xf5 0xd1 0x3b
|
||||
# CHECK: memd(r17 + r21<<#3) = r31:30
|
||||
0x28 0xd4 0xc0 0x48
|
||||
|
|
@ -16,6 +18,8 @@
|
|||
# CHECK: memd(r17++m1) = r21:20
|
||||
0x00 0xf4 0xd1 0xaf
|
||||
# CHECK: memd(r17 ++ m1:brev) = r21:20
|
||||
|
||||
# Store doubleword conditionally
|
||||
0xfe 0xf5 0xd1 0x34
|
||||
# CHECK: if (p3) memd(r17+r21<<#3) = r31:30
|
||||
0xfe 0xf5 0xd1 0x35
|
||||
|
|
@ -47,6 +51,7 @@
|
|||
# CHECK: p3 = r5
|
||||
# CHECK-NEXT: if (!p3.new) memd(r17++#40) = r21:20
|
||||
|
||||
# Store byte
|
||||
0x9f 0xf5 0x11 0x3b
|
||||
# CHECK: memb(r17 + r21<<#3) = r31
|
||||
0x9f 0xca 0x11 0x3c
|
||||
|
|
@ -65,6 +70,8 @@
|
|||
# CHECK: memb(r17++m1) = r21
|
||||
0x00 0xf5 0x11 0xaf
|
||||
# CHECK: memb(r17 ++ m1:brev) = r21
|
||||
|
||||
# Store byte conditionally
|
||||
0xff 0xf5 0x11 0x34
|
||||
# CHECK: if (p3) memb(r17+r21<<#3) = r31
|
||||
0xff 0xf5 0x11 0x35
|
||||
|
|
@ -106,6 +113,7 @@
|
|||
# CHECK: p3 = r5
|
||||
# CHECK-NEXT: if (!p3.new) memb(r17++#5) = r21
|
||||
|
||||
# Store halfword
|
||||
0x9f 0xf5 0x51 0x3b
|
||||
# CHECK: memh(r17 + r21<<#3) = r31
|
||||
0x9f 0xf5 0x71 0x3b
|
||||
|
|
@ -140,6 +148,8 @@
|
|||
# CHECK: memh(r17 ++ m1:brev) = r21
|
||||
0x00 0xf5 0x71 0xaf
|
||||
# CHECK: memh(r17 ++ m1:brev) = r21.h
|
||||
|
||||
# Store halfword conditionally
|
||||
0xff 0xf5 0x51 0x34
|
||||
# CHECK: if (p3) memh(r17+r21<<#3) = r31
|
||||
0xff 0xf5 0x71 0x34
|
||||
|
|
@ -211,6 +221,7 @@
|
|||
# CHECK: p3 = r5
|
||||
# CHECK-NEXT: if (!p3.new) memh(r17++#10) = r21.h
|
||||
|
||||
# Store word
|
||||
0x9f 0xf5 0x91 0x3b
|
||||
# CHECK: memw(r17 + r21<<#3) = r31
|
||||
0x9f 0xca 0x51 0x3c
|
||||
|
|
@ -229,6 +240,8 @@
|
|||
# CHECK: memw(r17++m1) = r21
|
||||
0x00 0xf5 0x91 0xaf
|
||||
# CHECK: memw(r17 ++ m1:brev) = r21
|
||||
|
||||
# Store word conditionally
|
||||
0xff 0xf5 0x91 0x34
|
||||
# CHECK: if (p3) memw(r17+r21<<#3) = r31
|
||||
0xff 0xf5 0x91 0x35
|
||||
|
|
@ -270,5 +283,6 @@
|
|||
# CHECK: p3 = r5
|
||||
# CHECK-NEXT: if (p3.new) memw(r17++#20) = r21
|
||||
|
||||
# Allocate stack frame
|
||||
0x1f 0xc0 0x9d 0xa0
|
||||
# CHECK: allocframe(#248)
|
||||
|
|
@ -1,12 +1,26 @@
|
|||
# RUN: llvm-mc --triple hexagon -disassemble < %s | FileCheck %s
|
||||
# RUN: llvm-mc -triple=hexagon -disassemble < %s | FileCheck %s
|
||||
# Hexagon Programmer's Reference Manual 11.9.1 SYSTEM/USER
|
||||
|
||||
# Load locked
|
||||
0x11 0xc0 0x15 0x92
|
||||
# CHECK: r17 = memw_locked(r21)
|
||||
0x10 0xd0 0x15 0x92
|
||||
# CHECK: r17:16 = memd_locked(r21)
|
||||
|
||||
# Store conditional
|
||||
0x03 0xd5 0xb1 0xa0
|
||||
# CHECK: memw_locked(r17, p3) = r21
|
||||
0x03 0xd4 0xf1 0xa0
|
||||
# CHECK: memd_locked(r17, p3) = r21:20
|
||||
|
||||
# Memory barrier
|
||||
0x00 0xc0 0x00 0xa8
|
||||
# CHECK: barrier
|
||||
|
||||
# Data cache prefetch
|
||||
0x15 0xc0 0x11 0x94
|
||||
# CHECK: dcfetch(r17 + #168)
|
||||
|
||||
# Send value to ETM trace
|
||||
0x00 0xc0 0x51 0x62
|
||||
# CHECK: trace(r17)
|
||||
|
|
|
|||
|
|
@ -1,11 +1,15 @@
|
|||
# RUN: llvm-mc --triple hexagon -disassemble < %s | FileCheck %s
|
||||
# RUN: llvm-mc -triple=hexagon -disassemble < %s | FileCheck %s
|
||||
# Hexagon Programmer's Reference Manual 11.10.1 XTYPE/ALU
|
||||
|
||||
# Absolute value doubleword
|
||||
0xd0 0xc0 0x94 0x80
|
||||
# CHECK: r17:16 = abs(r21:20)
|
||||
0x91 0xc0 0x95 0x8c
|
||||
# CHECK: r17 = abs(r21)
|
||||
0xb1 0xc0 0x95 0x8c
|
||||
# CHECK: r17 = abs(r21):sat
|
||||
|
||||
# Add and accumulate
|
||||
0xff 0xd1 0x35 0xdb
|
||||
# CHECK: r17 = add(r21, add(r31, #23))
|
||||
0xff 0xd1 0xb5 0xdb
|
||||
|
|
@ -18,8 +22,18 @@
|
|||
# CHECK: r17 += add(r21, r31)
|
||||
0x31 0xdf 0x95 0xef
|
||||
# CHECK: r17 -= add(r21, r31)
|
||||
|
||||
# Add doublewords
|
||||
0xf0 0xde 0x14 0xd3
|
||||
# CHECK: r17:16 = add(r21:20, r31:30)
|
||||
0xb0 0xde 0x74 0xd3
|
||||
# CHECK: r17:16 = add(r21:20, r31:30):sat
|
||||
0xd0 0xde 0x74 0xd3
|
||||
# CHECK: r17:16 = add(r21:20, r31:30):raw:lo
|
||||
0xf0 0xde 0x74 0xd3
|
||||
# CHECK: r17:16 = add(r21:20, r31:30):raw:hi
|
||||
|
||||
# Add halfword
|
||||
0x11 0xd5 0x1f 0xd5
|
||||
# CHECK: r17 = add(r21.l, r31.l)
|
||||
0x51 0xd5 0x1f 0xd5
|
||||
|
|
@ -44,20 +58,16 @@
|
|||
# CHECK: r17 = add(r21.h, r31.l):sat:<<16
|
||||
0xf1 0xd5 0x5f 0xd5
|
||||
# CHECK: r17 = add(r21.h, r31.h):sat:<<16
|
||||
|
||||
# Add or subtract doublewords with carry
|
||||
0x70 0xde 0xd4 0xc2
|
||||
# CHECK: r17:16 = add(r21:20, r31:30, p3):carry
|
||||
0x70 0xde 0xf4 0xc2
|
||||
# CHECK: r17:16 = sub(r21:20, r31:30, p3):carry
|
||||
|
||||
# Logical doublewords
|
||||
0x90 0xc0 0x94 0x80
|
||||
# CHECK: r17:16 = not(r21:20)
|
||||
0xf0 0xde 0x14 0xd3
|
||||
# CHECK: r17:16 = add(r21:20, r31:30)
|
||||
0xb0 0xde 0x74 0xd3
|
||||
# CHECK: r17:16 = add(r21:20, r31:30):sat
|
||||
0xd0 0xde 0x74 0xd3
|
||||
# CHECK: r17:16 = add(r21:20, r31:30):raw:lo
|
||||
0xf0 0xde 0x74 0xd3
|
||||
# CHECK: r17:16 = add(r21:20, r31:30):raw:hi
|
||||
0x10 0xde 0xf4 0xd3
|
||||
# CHECK: r17:16 = and(r21:20, r31:30)
|
||||
0x30 0xd4 0xfe 0xd3
|
||||
|
|
@ -66,8 +76,14 @@
|
|||
# CHECK: r17:16 = or(r21:20, r31:30)
|
||||
0x70 0xd4 0xfe 0xd3
|
||||
# CHECK: r17:16 = or(r21:20, ~r31:30)
|
||||
0x90 0xde 0xf4 0xd3
|
||||
# CHECK: r17:16 = xor(r21:20, r31:30)
|
||||
|
||||
# Logical-logical doublewords
|
||||
0x10 0xde 0x94 0xca
|
||||
# CHECK: r17:16 ^= xor(r21:20, r31:30)
|
||||
|
||||
# Logical-logical words
|
||||
0xf1 0xc3 0x15 0xda
|
||||
# CHECK: r17 |= and(r21, #31)
|
||||
0xf5 0xc3 0x51 0xda
|
||||
|
|
@ -98,28 +114,42 @@
|
|||
# CHECK: r17 ^= and(r21, r31)
|
||||
0x71 0xdf 0xd5 0xef
|
||||
# CHECK: r17 ^= or(r21, r31)
|
||||
|
||||
# Maximum words
|
||||
0x11 0xdf 0xd5 0xd5
|
||||
# CHECK: r17 = max(r21, r31)
|
||||
0x91 0xdf 0xd5 0xd5
|
||||
# CHECK: r17 = maxu(r21, r31)
|
||||
|
||||
# Maximum doublewords
|
||||
0x90 0xde 0xd4 0xd3
|
||||
# CHECK: r17:16 = max(r21:20, r31:30)
|
||||
0xb0 0xde 0xd4 0xd3
|
||||
# CHECK: r17:16 = maxu(r21:20, r31:30)
|
||||
|
||||
# Minimum words
|
||||
0x11 0xd5 0xbf 0xd5
|
||||
# CHECK: r17 = min(r21, r31)
|
||||
0x91 0xd5 0xbf 0xd5
|
||||
# CHECK: r17 = minu(r21, r31)
|
||||
|
||||
# Minimum doublewords
|
||||
0xd0 0xd4 0xbe 0xd3
|
||||
# CHECK: r17:16 = min(r21:20, r31:30)
|
||||
0xf0 0xd4 0xbe 0xd3
|
||||
# CHECK: r17:16 = minu(r21:20, r31:30)
|
||||
|
||||
# Module wrap
|
||||
0xf1 0xdf 0xf5 0xd3
|
||||
# CHECK: r17 = modwrap(r21, r31)
|
||||
|
||||
# Negate
|
||||
0xb0 0xc0 0x94 0x80
|
||||
# CHECK: r17:16 = neg(r21:20)
|
||||
0xd1 0xc0 0x95 0x8c
|
||||
# CHECK: r17 = neg(r21):sat
|
||||
|
||||
# Round
|
||||
0x31 0xc0 0xd4 0x88
|
||||
# CHECK: r17 = round(r21:20):sat
|
||||
0x11 0xdf 0xf5 0x8c
|
||||
|
|
@ -134,8 +164,16 @@
|
|||
# CHECK: r17 = round(r21, r31)
|
||||
0xd1 0xdf 0xd5 0xc6
|
||||
# CHECK: r17 = round(r21, r31):sat
|
||||
|
||||
# Subtract doublewords
|
||||
0xf0 0xd4 0x3e 0xd3
|
||||
# CHECK: r17:16 = sub(r21:20, r31:30)
|
||||
|
||||
# Subtract and accumulate words
|
||||
0x71 0xd5 0x1f 0xef
|
||||
# CHECK: r17 += sub(r21, r31)
|
||||
|
||||
# Subtract halfword
|
||||
0x11 0xd5 0x3f 0xd5
|
||||
# CHECK: r17 = sub(r21.l, r31.l)
|
||||
0x51 0xd5 0x3f 0xd5
|
||||
|
|
@ -160,7 +198,194 @@
|
|||
# CHECK: r17 = sub(r21.h, r31.l):sat:<<16
|
||||
0xf1 0xd5 0x7f 0xd5
|
||||
# CHECK: r17 = sub(r21.h, r31.h):sat:<<16
|
||||
|
||||
# Sign extend word to doubleword
|
||||
0x10 0xc0 0x55 0x84
|
||||
# CHECK: r17:16 = sxtw(r21)
|
||||
0x90 0xde 0xf4 0xd3
|
||||
# CHECK: r17:16 = xor(r21:20, r31:30)
|
||||
|
||||
# Vector absolute value halfwords
|
||||
0x90 0xc0 0x54 0x80
|
||||
# CHECK: r17:16 = vabsh(r21:20)
|
||||
0xb0 0xc0 0x54 0x80
|
||||
# CHECK: r17:16 = vabsh(r21:20):sat
|
||||
|
||||
# Vector absolute value words
|
||||
0xd0 0xc0 0x54 0x80
|
||||
# CHECK: r17:16 = vabsw(r21:20)
|
||||
0xf0 0xc0 0x54 0x80
|
||||
# CHECK: r17:16 = vabsw(r21:20):sat
|
||||
|
||||
# Vector absolute difference halfwords
|
||||
0x10 0xd4 0x7e 0xe8
|
||||
# CHECK: r17:16 = vabsdiffh(r21:20, r31:30)
|
||||
|
||||
# Vector add halfwords
|
||||
0x50 0xde 0x14 0xd3
|
||||
# CHECK: r17:16 = vaddh(r21:20, r31:30)
|
||||
0x70 0xde 0x14 0xd3
|
||||
# CHECK: r17:16 = vaddh(r21:20, r31:30):sat
|
||||
0x90 0xde 0x14 0xd3
|
||||
# CHECK: r17:16 = vadduh(r21:20, r31:30):sat
|
||||
|
||||
# Vector add halfwords with saturate and pack to unsigned bytes
|
||||
0x31 0xde 0x54 0xc1
|
||||
# CHECK: r17 = vaddhub(r21:20, r31:30):sat
|
||||
|
||||
# Vector reduce add unsigned bytes
|
||||
0x30 0xde 0x54 0xe8
|
||||
# CHECK: r17:16 = vraddub(r21:20, r31:30)
|
||||
0x30 0xde 0x54 0xea
|
||||
# CHECK: r17:16 += vraddub(r21:20, r31:30)
|
||||
|
||||
# Vector reduce add halfwords
|
||||
0x31 0xde 0x14 0xe9
|
||||
# CHECK: r17 = vradduh(r21:20, r31:30)
|
||||
0xf1 0xde 0x34 0xe9
|
||||
# CHECK: r17 = vraddh(r21:20, r31:30)
|
||||
|
||||
# Vector add bytes
|
||||
0x10 0xde 0x14 0xd3
|
||||
# CHECK: r17:16 = vaddub(r21:20, r31:30)
|
||||
0x30 0xde 0x14 0xd3
|
||||
# CHECK: r17:16 = vaddub(r21:20, r31:30):sat
|
||||
|
||||
# Vector add words
|
||||
0xb0 0xde 0x14 0xd3
|
||||
# CHECK: r17:16 = vaddw(r21:20, r31:30)
|
||||
0xd0 0xde 0x14 0xd3
|
||||
# CHECK: r17:16 = vaddw(r21:20, r31:30):sat
|
||||
|
||||
# Vector average halfwords
|
||||
0x50 0xde 0x54 0xd3
|
||||
# CHECK: r17:16 = vavgh(r21:20, r31:30)
|
||||
0x70 0xde 0x54 0xd3
|
||||
# CHECK: r17:16 = vavgh(r21:20, r31:30):rnd
|
||||
0x90 0xde 0x54 0xd3
|
||||
# CHECK: r17:16 = vavgh(r21:20, r31:30):crnd
|
||||
0xb0 0xde 0x54 0xd3
|
||||
# CHECK: r17:16 = vavguh(r21:20, r31:30)
|
||||
0xd0 0xde 0x54 0xd3
|
||||
# CHECK: r17:16 = vavguh(r21:20, r31:30):rnd
|
||||
0x10 0xd4 0x9e 0xd3
|
||||
# CHECK: r17:16 = vnavgh(r21:20, r31:30)
|
||||
0x30 0xd4 0x9e 0xd3
|
||||
# CHECK: r17:16 = vnavgh(r21:20, r31:30):rnd:sat
|
||||
0x50 0xd4 0x9e 0xd3
|
||||
# CHECK: r17:16 = vnavgh(r21:20, r31:30):crnd:sat
|
||||
|
||||
# Vector average unsigned bytes
|
||||
0x10 0xde 0x54 0xd3
|
||||
# CHECK: r17:16 = vavgub(r21:20, r31:30)
|
||||
0x30 0xde 0x54 0xd3
|
||||
# CHECK: r17:16 = vavgub(r21:20, r31:30):rnd
|
||||
|
||||
# Vector average words
|
||||
0x10 0xde 0x74 0xd3
|
||||
# CHECK: r17:16 = vavgw(r21:20, r31:30)
|
||||
0x30 0xde 0x74 0xd3
|
||||
# CHECK: r17:16 = vavgw(r21:20, r31:30):rnd
|
||||
0x50 0xde 0x74 0xd3
|
||||
# CHECK: r17:16 = vavgw(r21:20, r31:30):crnd
|
||||
0x70 0xde 0x74 0xd3
|
||||
# CHECK: r17:16 = vavguw(r21:20, r31:30)
|
||||
0x90 0xde 0x74 0xd3
|
||||
# CHECK: r17:16 = vavguw(r21:20, r31:30):rnd
|
||||
0x70 0xd4 0x9e 0xd3
|
||||
# CHECK: r17:16 = vnavgw(r21:20, r31:30)
|
||||
0x90 0xd4 0x9e 0xd3
|
||||
# CHECK: r17:16 = vnavgw(r21:20, r31:30):rnd:sat
|
||||
0xd0 0xd4 0x9e 0xd3
|
||||
# CHECK: r17:16 = vnavgw(r21:20, r31:30):crnd:sat
|
||||
|
||||
# Vector conditional negate
|
||||
0x50 0xdf 0xd4 0xc3
|
||||
# CHECK: r17:16 = vcnegh(r21:20, r31)
|
||||
|
||||
0xf0 0xff 0x34 0xcb
|
||||
# CHECK: r17:16 += vrcnegh(r21:20, r31)
|
||||
|
||||
# Vector maximum bytes
|
||||
0x10 0xd4 0xde 0xd3
|
||||
# CHECK: r17:16 = vmaxub(r21:20, r31:30)
|
||||
0xd0 0xd4 0xde 0xd3
|
||||
# CHECK: r17:16 = vmaxb(r21:20, r31:30)
|
||||
|
||||
# Vector maximum halfwords
|
||||
0x30 0xd4 0xde 0xd3
|
||||
# CHECK: r17:16 = vmaxh(r21:20, r31:30)
|
||||
0x50 0xd4 0xde 0xd3
|
||||
# CHECK: r17:16 = vmaxuh(r21:20, r31:30)
|
||||
|
||||
# Vector reduce maximum halfwords
|
||||
0x3f 0xd0 0x34 0xcb
|
||||
# CHECK: r17:16 = vrmaxh(r21:20, r31)
|
||||
0x3f 0xf0 0x34 0xcb
|
||||
# CHECK: r17:16 = vrmaxuh(r21:20, r31)
|
||||
|
||||
# Vector reduce maximum words
|
||||
0x5f 0xd0 0x34 0xcb
|
||||
# CHECK: r17:16 = vrmaxw(r21:20, r31)
|
||||
0x5f 0xf0 0x34 0xcb
|
||||
# CHECK: r17:16 = vrmaxuw(r21:20, r31)
|
||||
|
||||
# Vector maximum words
|
||||
0xb0 0xd4 0xbe 0xd3
|
||||
# CHECK: r17:16 = vmaxuw(r21:20, r31:30)
|
||||
0x70 0xd4 0xde 0xd3
|
||||
# CHECK: r17:16 = vmaxw(r21:20, r31:30)
|
||||
|
||||
# Vector minimum bytes
|
||||
0x10 0xd4 0xbe 0xd3
|
||||
# CHECK: r17:16 = vminub(r21:20, r31:30)
|
||||
0xf0 0xd4 0xde 0xd3
|
||||
# CHECK: r17:16 = vminb(r21:20, r31:30)
|
||||
|
||||
# Vector minimum halfwords
|
||||
0x30 0xd4 0xbe 0xd3
|
||||
# CHECK: r17:16 = vminh(r21:20, r31:30)
|
||||
0x50 0xd4 0xbe 0xd3
|
||||
# CHECK: r17:16 = vminuh(r21:20, r31:30)
|
||||
|
||||
# Vector reduce minimum halfwords
|
||||
0xbf 0xd0 0x34 0xcb
|
||||
# CHECK: r17:16 = vrminh(r21:20, r31)
|
||||
0xbf 0xf0 0x34 0xcb
|
||||
# CHECK: r17:16 = vrminuh(r21:20, r31)
|
||||
|
||||
# Vector reduce minimum words
|
||||
0xdf 0xd0 0x34 0xcb
|
||||
# CHECK: r17:16 = vrminw(r21:20, r31)
|
||||
0xdf 0xf0 0x34 0xcb
|
||||
# CHECK: r17:16 = vrminuw(r21:20, r31)
|
||||
|
||||
# Vector minimum words
|
||||
0x70 0xd4 0xbe 0xd3
|
||||
# CHECK: r17:16 = vminw(r21:20, r31:30)
|
||||
0x90 0xd4 0xbe 0xd3
|
||||
# CHECK: r17:16 = vminuw(r21:20, r31:30)
|
||||
|
||||
# Vector sum of absolute differences unsigned bytes
|
||||
0x50 0xde 0x54 0xe8
|
||||
# CHECK: r17:16 = vrsadub(r21:20, r31:30)
|
||||
0x50 0xde 0x54 0xea
|
||||
# CHECK: r17:16 += vrsadub(r21:20, r31:30)
|
||||
|
||||
# Vector subtract halfwords
|
||||
0x50 0xd4 0x3e 0xd3
|
||||
# CHECK: r17:16 = vsubh(r21:20, r31:30)
|
||||
0x70 0xd4 0x3e 0xd3
|
||||
# CHECK: r17:16 = vsubh(r21:20, r31:30):sat
|
||||
0x90 0xd4 0x3e 0xd3
|
||||
# CHECK: r17:16 = vsubuh(r21:20, r31:30):sat
|
||||
|
||||
# Vector subtract bytes
|
||||
0x10 0xd4 0x3e 0xd3
|
||||
# CHECK: r17:16 = vsubub(r21:20, r31:30)
|
||||
0x30 0xd4 0x3e 0xd3
|
||||
# CHECK: r17:16 = vsubub(r21:20, r31:30):sat
|
||||
|
||||
# Vector subtract words
|
||||
0xb0 0xd4 0x3e 0xd3
|
||||
# CHECK: r17:16 = vsubw(r21:20, r31:30)
|
||||
0xd0 0xd4 0x3e 0xd3
|
||||
# CHECK: r17:16 = vsubw(r21:20, r31:30):sat
|
||||
|
|
|
|||
Loading…
Reference in New Issue