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[X86] Add common CHECK prefix to shift combine tests 

llvm-svn: 324638
This commit is contained in:
Simon Pilgrim 2018-02-08 19:23:47 +00:00
parent ae6873f91c
commit 21fb6bccc4
3 changed files with 59 additions and 125 deletions
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69
llvm/test/CodeGen/X86/combine-shl.ll
View File

@ -1,31 +1,22 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse4.1 | FileCheck %s --check-prefix=SSE
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx2 | FileCheck %s --check-prefixes=AVX,AVX-SLOW
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx2,+fast-variable-shuffle | FileCheck %s --check-prefixes=AVX,AVX-FAST
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse4.1 | FileCheck %s --check-prefixes=CHECK,SSE
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx2 | FileCheck %s --check-prefixes=CHECK,AVX,AVX-SLOW
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx2,+fast-variable-shuffle | FileCheck %s --check-prefixes=CHECK,AVX,AVX-FAST
; fold (shl undef, x) -> 0
define i32 @combine_shl_undef0(i32 %x) {
; SSE-LABEL: combine_shl_undef0:
; SSE: # %bb.0:
; SSE-NEXT: xorl %eax, %eax
; SSE-NEXT: retq
;
; AVX-LABEL: combine_shl_undef0:
; AVX: # %bb.0:
; AVX-NEXT: xorl %eax, %eax
; AVX-NEXT: retq
; CHECK-LABEL: combine_shl_undef0:
; CHECK: # %bb.0:
; CHECK-NEXT: xorl %eax, %eax
; CHECK-NEXT: retq
%1 = shl i32 undef, %x
ret i32 %1
}
define <4 x i32> @combine_vec_shl_undef0(<4 x i32> %x) {
; SSE-LABEL: combine_vec_shl_undef0:
; SSE: # %bb.0:
; SSE-NEXT: retq
;
; AVX-LABEL: combine_vec_shl_undef0:
; AVX: # %bb.0:
; AVX-NEXT: retq
; CHECK-LABEL: combine_vec_shl_undef0:
; CHECK: # %bb.0:
; CHECK-NEXT: retq
%1 = shl <4 x i32> undef, %x
ret <4 x i32> %1
}
@ -47,37 +38,25 @@ define <4 x i32> @combine_vec_shl_zero(<4 x i32> %x) {
; fold (shl x, c >= size(x)) -> undef
define <4 x i32> @combine_vec_shl_outofrange0(<4 x i32> %x) {
; SSE-LABEL: combine_vec_shl_outofrange0:
; SSE: # %bb.0:
; SSE-NEXT: retq
;
; AVX-LABEL: combine_vec_shl_outofrange0:
; AVX: # %bb.0:
; AVX-NEXT: retq
; CHECK-LABEL: combine_vec_shl_outofrange0:
; CHECK: # %bb.0:
; CHECK-NEXT: retq
%1 = shl <4 x i32> %x, <i32 33, i32 33, i32 33, i32 33>
ret <4 x i32> %1
}
define <4 x i32> @combine_vec_shl_outofrange1(<4 x i32> %x) {
; SSE-LABEL: combine_vec_shl_outofrange1:
; SSE: # %bb.0:
; SSE-NEXT: retq
;
; AVX-LABEL: combine_vec_shl_outofrange1:
; AVX: # %bb.0:
; AVX-NEXT: retq
; CHECK-LABEL: combine_vec_shl_outofrange1:
; CHECK: # %bb.0:
; CHECK-NEXT: retq
%1 = shl <4 x i32> %x, <i32 33, i32 34, i32 35, i32 36>
ret <4 x i32> %1
}
define <4 x i32> @combine_vec_shl_outofrange2(<4 x i32> %a0) {
; SSE-LABEL: combine_vec_shl_outofrange2:
; SSE: # %bb.0:
; SSE-NEXT: retq
;
; AVX-LABEL: combine_vec_shl_outofrange2:
; AVX: # %bb.0:
; AVX-NEXT: retq
; CHECK-LABEL: combine_vec_shl_outofrange2:
; CHECK: # %bb.0:
; CHECK-NEXT: retq
%1 = and <4 x i32> %a0, <i32 2147483647, i32 2147483647, i32 2147483647, i32 2147483647>
%2 = shl <4 x i32> %1, <i32 33, i32 33, i32 33, i32 33>
ret <4 x i32> %2
@ -85,13 +64,9 @@ define <4 x i32> @combine_vec_shl_outofrange2(<4 x i32> %a0) {
; fold (shl x, 0) -> x
define <4 x i32> @combine_vec_shl_by_zero(<4 x i32> %x) {
; SSE-LABEL: combine_vec_shl_by_zero:
; SSE: # %bb.0:
; SSE-NEXT: retq
;
; AVX-LABEL: combine_vec_shl_by_zero:
; AVX: # %bb.0:
; AVX-NEXT: retq
; CHECK-LABEL: combine_vec_shl_by_zero:
; CHECK: # %bb.0:
; CHECK-NEXT: retq
%1 = shl <4 x i32> %x, zeroinitializer
ret <4 x i32> %1
}

56
llvm/test/CodeGen/X86/combine-sra.ll
View File

@ -1,29 +1,21 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse4.1 | FileCheck %s --check-prefix=SSE
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx2 | FileCheck %s --check-prefixes=AVX,AVX2-SLOW
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx2,+fast-variable-shuffle | FileCheck %s --check-prefixes=AVX,AVX2-FAST
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse4.1 | FileCheck %s --check-prefixes=CHECK,SSE
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx2 | FileCheck %s --check-prefixes=CHECK,AVX,AVX2-SLOW
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx2,+fast-variable-shuffle | FileCheck %s --check-prefixes=CHECK,AVX,AVX2-FAST
; fold (sra undef, x) -> undef
define i32 @combine_lshr_undef0(i32 %x) {
; SSE-LABEL: combine_lshr_undef0:
; SSE: # %bb.0:
; SSE-NEXT: retq
;
; AVX-LABEL: combine_lshr_undef0:
; AVX: # %bb.0:
; AVX-NEXT: retq
; CHECK-LABEL: combine_lshr_undef0:
; CHECK: # %bb.0:
; CHECK-NEXT: retq
%1 = ashr i32 undef, %x
ret i32 %1
}
define <4 x i32> @combine_vec_ashr_undef0(<4 x i32> %x) {
; SSE-LABEL: combine_vec_ashr_undef0:
; SSE: # %bb.0:
; SSE-NEXT: retq
;
; AVX-LABEL: combine_vec_ashr_undef0:
; AVX: # %bb.0:
; AVX-NEXT: retq
; CHECK-LABEL: combine_vec_ashr_undef0:
; CHECK: # %bb.0:
; CHECK-NEXT: retq
%1 = ashr <4 x i32> undef, %x
ret <4 x i32> %1
}
@ -60,38 +52,26 @@ define <4 x i32> @combine_vec_ashr_allones(<4 x i32> %x) {
; fold (sra x, c >= size(x)) -> undef
define <4 x i32> @combine_vec_ashr_outofrange0(<4 x i32> %x) {
; SSE-LABEL: combine_vec_ashr_outofrange0:
; SSE: # %bb.0:
; SSE-NEXT: retq
;
; AVX-LABEL: combine_vec_ashr_outofrange0:
; AVX: # %bb.0:
; AVX-NEXT: retq
; CHECK-LABEL: combine_vec_ashr_outofrange0:
; CHECK: # %bb.0:
; CHECK-NEXT: retq
%1 = ashr <4 x i32> %x, <i32 33, i32 33, i32 33, i32 33>
ret <4 x i32> %1
}
define <4 x i32> @combine_vec_ashr_outofrange1(<4 x i32> %x) {
; SSE-LABEL: combine_vec_ashr_outofrange1:
; SSE: # %bb.0:
; SSE-NEXT: retq
;
; AVX-LABEL: combine_vec_ashr_outofrange1:
; AVX: # %bb.0:
; AVX-NEXT: retq
; CHECK-LABEL: combine_vec_ashr_outofrange1:
; CHECK: # %bb.0:
; CHECK-NEXT: retq
%1 = ashr <4 x i32> %x, <i32 33, i32 34, i32 35, i32 36>
ret <4 x i32> %1
}
; fold (sra x, 0) -> x
define <4 x i32> @combine_vec_ashr_by_zero(<4 x i32> %x) {
; SSE-LABEL: combine_vec_ashr_by_zero:
; SSE: # %bb.0:
; SSE-NEXT: retq
;
; AVX-LABEL: combine_vec_ashr_by_zero:
; AVX: # %bb.0:
; AVX-NEXT: retq
; CHECK-LABEL: combine_vec_ashr_by_zero:
; CHECK: # %bb.0:
; CHECK-NEXT: retq
%1 = ashr <4 x i32> %x, zeroinitializer
ret <4 x i32> %1
}

59
llvm/test/CodeGen/X86/combine-srl.ll
View File

@ -1,31 +1,22 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse4.1 | FileCheck %s --check-prefix=SSE
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx2 | FileCheck %s --check-prefixes=AVX,AVX2-SLOW
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx2,+fast-variable-shuffle | FileCheck %s --check-prefixes=AVX,AVX2-FAST
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse4.1 | FileCheck %s --check-prefixes=CHECK,SSE
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx2 | FileCheck %s --check-prefixes=CHECK,AVX,AVX2-SLOW
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx2,+fast-variable-shuffle | FileCheck %s --check-prefixes=CHECK,AVX,AVX2-FAST
; fold (srl undef, x) -> 0
define i32 @combine_lshr_undef0(i32 %x) {
; SSE-LABEL: combine_lshr_undef0:
; SSE: # %bb.0:
; SSE-NEXT: xorl %eax, %eax
; SSE-NEXT: retq
;
; AVX-LABEL: combine_lshr_undef0:
; AVX: # %bb.0:
; AVX-NEXT: xorl %eax, %eax
; AVX-NEXT: retq
; CHECK-LABEL: combine_lshr_undef0:
; CHECK: # %bb.0:
; CHECK-NEXT: xorl %eax, %eax
; CHECK-NEXT: retq
%1 = lshr i32 undef, %x
ret i32 %1
}
define <4 x i32> @combine_vec_lshr_undef0(<4 x i32> %x) {
; SSE-LABEL: combine_vec_lshr_undef0:
; SSE: # %bb.0:
; SSE-NEXT: retq
;
; AVX-LABEL: combine_vec_lshr_undef0:
; AVX: # %bb.0:
; AVX-NEXT: retq
; CHECK-LABEL: combine_vec_lshr_undef0:
; CHECK: # %bb.0:
; CHECK-NEXT: retq
%1 = lshr <4 x i32> undef, %x
ret <4 x i32> %1
}
@ -47,38 +38,26 @@ define <4 x i32> @combine_vec_lshr_zero(<4 x i32> %x) {
; fold (srl x, c >= size(x)) -> undef
define <4 x i32> @combine_vec_lshr_outofrange0(<4 x i32> %x) {
; SSE-LABEL: combine_vec_lshr_outofrange0:
; SSE: # %bb.0:
; SSE-NEXT: retq
;
; AVX-LABEL: combine_vec_lshr_outofrange0:
; AVX: # %bb.0:
; AVX-NEXT: retq
; CHECK-LABEL: combine_vec_lshr_outofrange0:
; CHECK: # %bb.0:
; CHECK-NEXT: retq
%1 = lshr <4 x i32> %x, <i32 33, i32 33, i32 33, i32 33>
ret <4 x i32> %1
}
define <4 x i32> @combine_vec_lshr_outofrange1(<4 x i32> %x) {
; SSE-LABEL: combine_vec_lshr_outofrange1:
; SSE: # %bb.0:
; SSE-NEXT: retq
;
; AVX-LABEL: combine_vec_lshr_outofrange1:
; AVX: # %bb.0:
; AVX-NEXT: retq
; CHECK-LABEL: combine_vec_lshr_outofrange1:
; CHECK: # %bb.0:
; CHECK-NEXT: retq
%1 = lshr <4 x i32> %x, <i32 33, i32 34, i32 35, i32 36>
ret <4 x i32> %1
}
; fold (srl x, 0) -> x
define <4 x i32> @combine_vec_lshr_by_zero(<4 x i32> %x) {
; SSE-LABEL: combine_vec_lshr_by_zero:
; SSE: # %bb.0:
; SSE-NEXT: retq
;
; AVX-LABEL: combine_vec_lshr_by_zero:
; AVX: # %bb.0:
; AVX-NEXT: retq
; CHECK-LABEL: combine_vec_lshr_by_zero:
; CHECK: # %bb.0:
; CHECK-NEXT: retq
%1 = lshr <4 x i32> %x, zeroinitializer
ret <4 x i32> %1
}