forked from OSchip/llvm-project
parent
5aa1cc4065
commit
21dca9cbb1
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@ -6441,22 +6441,18 @@ void SelectionDAGLegalize::ExpandOp(SDValue Op, SDValue &Lo, SDValue &Hi){
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LoOps[1] = RHSL;
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HiOps[0] = LHSH;
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HiOps[1] = RHSH;
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//cascaded check to see if any smaller size has a a carry flag.
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unsigned OpV = Node->getOpcode() == ISD::ADD ? ISD::ADDC : ISD::SUBC;
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bool hasCarry = false;
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if (NVT == MVT::i64)
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hasCarry = TLI.isOperationLegal(OpV, MVT::i64)
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| TLI.isOperationLegal(OpV, MVT::i32)
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| TLI.isOperationLegal(OpV, MVT::i16)
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| TLI.isOperationLegal(OpV, MVT::i8);
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if (NVT == MVT::i32)
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hasCarry = TLI.isOperationLegal(OpV, MVT::i32)
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| TLI.isOperationLegal(OpV, MVT::i16)
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| TLI.isOperationLegal(OpV, MVT::i8);
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if (NVT == MVT::i16)
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hasCarry = TLI.isOperationLegal(OpV, MVT::i16)
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| TLI.isOperationLegal(OpV, MVT::i8);
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for (unsigned BitSize = NVT.getSizeInBits(); BitSize != 0; BitSize /= 2) {
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MVT AVT = MVT::getIntegerVT(BitSize);
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if (TLI.isOperationLegal(OpV, AVT)) {
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hasCarry = true;
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break;
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}
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}
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if(hasCarry) {
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if (Node->getOpcode() == ISD::ADD) {
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Lo = DAG.getNode(ISD::ADDC, VTList, LoOps, 2);
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