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Use const qualifiers with TargetLowering. This eliminates several 

const_casts, and it reinforces the design of the Target classes being
immutable.

SelectionDAGISel::IsLegalToFold is now a static member function, because
PIC16 uses it in an unconventional way. There is more room for API
cleanup here.

And PIC16's AsmPrinter no longer uses TargetLowering.

llvm-svn: 101635
This commit is contained in:
Dan Gohman 2010-04-17 15:26:15 +00:00
parent 31ae586c74
commit 21cea8ac2e
70 changed files with 755 additions and 690 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
llvm/include/llvm/CodeGen/SelectionDAG.h
View File

@ -117,7 +117,7 @@ void checkForCycles(const SelectionDAG *DAG);
/// linear form. /// linear form.
/// ///
class SelectionDAG { class SelectionDAG {
TargetLowering &TLI; const TargetLowering &TLI;
MachineFunction *MF; MachineFunction *MF;
FunctionLoweringInfo &FLI; FunctionLoweringInfo &FLI;
LLVMContext *Context; LLVMContext *Context;
@ -172,7 +172,7 @@ class SelectionDAG {
SelectionDAG(const SelectionDAG&); // Do not implement. SelectionDAG(const SelectionDAG&); // Do not implement.
public: public:
SelectionDAG(TargetLowering &tli, FunctionLoweringInfo &fli); SelectionDAG(const TargetLowering &tli, FunctionLoweringInfo &fli);
~SelectionDAG(); ~SelectionDAG();
/// init - Prepare this SelectionDAG to process code in the given /// init - Prepare this SelectionDAG to process code in the given
@ -187,7 +187,7 @@ public:
MachineFunction &getMachineFunction() const { return *MF; } MachineFunction &getMachineFunction() const { return *MF; }
const TargetMachine &getTarget() const; const TargetMachine &getTarget() const;
TargetLowering &getTargetLoweringInfo() const { return TLI; } const TargetLowering &getTargetLoweringInfo() const { return TLI; }
FunctionLoweringInfo &getFunctionLoweringInfo() const { return FLI; } FunctionLoweringInfo &getFunctionLoweringInfo() const { return FLI; }
LLVMContext *getContext() const {return Context; } LLVMContext *getContext() const {return Context; }

11
llvm/include/llvm/CodeGen/SelectionDAGISel.h
View File

@ -40,7 +40,7 @@ namespace llvm {
class SelectionDAGISel : public MachineFunctionPass { class SelectionDAGISel : public MachineFunctionPass {
public: public:
const TargetMachine &TM; const TargetMachine &TM;
TargetLowering &TLI; const TargetLowering &TLI;
FunctionLoweringInfo *FuncInfo; FunctionLoweringInfo *FuncInfo;
MachineFunction *MF; MachineFunction *MF;
MachineRegisterInfo *RegInfo; MachineRegisterInfo *RegInfo;
@ -56,7 +56,7 @@ public:
CodeGenOpt::Level OL = CodeGenOpt::Default); CodeGenOpt::Level OL = CodeGenOpt::Default);
virtual ~SelectionDAGISel(); virtual ~SelectionDAGISel();
TargetLowering &getTargetLowering() { return TLI; } const TargetLowering &getTargetLowering() { return TLI; }
virtual void getAnalysisUsage(AnalysisUsage &AU) const; virtual void getAnalysisUsage(AnalysisUsage &AU) const;
@ -92,8 +92,11 @@ public:
/// IsLegalToFold - Returns true if the specific operand node N of /// IsLegalToFold - Returns true if the specific operand node N of
/// U can be folded during instruction selection that starts at Root. /// U can be folded during instruction selection that starts at Root.
bool IsLegalToFold(SDValue N, SDNode *U, SDNode *Root, /// FIXME: This is a static member function because the PIC16 target,
bool IgnoreChains = false) const; /// which uses it during lowering.
static bool IsLegalToFold(SDValue N, SDNode *U, SDNode *Root,
CodeGenOpt::Level OptLevel,
bool IgnoreChains = false);
/// CreateTargetHazardRecognizer - Return a newly allocated hazard recognizer /// CreateTargetHazardRecognizer - Return a newly allocated hazard recognizer
/// to use for this target when scheduling the DAG. /// to use for this target when scheduling the DAG.

29
llvm/include/llvm/Target/TargetLowering.h
View File

@ -309,7 +309,7 @@ public:
}; };
virtual bool getTgtMemIntrinsic(IntrinsicInfo &Info, virtual bool getTgtMemIntrinsic(IntrinsicInfo &Info,
const CallInst &I, unsigned Intrinsic) { const CallInst &I, unsigned Intrinsic) const {
return false; return false;
} }
@ -1094,7 +1094,7 @@ protected:
public: public:
virtual const TargetSubtarget *getSubtarget() { virtual const TargetSubtarget *getSubtarget() const {
assert(0 && "Not Implemented"); assert(0 && "Not Implemented");
return NULL; // this is here to silence compiler errors return NULL; // this is here to silence compiler errors
} }
@ -1115,7 +1115,7 @@ public:
CallingConv::ID CallConv, bool isVarArg, CallingConv::ID CallConv, bool isVarArg,
const SmallVectorImpl<ISD::InputArg> &Ins, const SmallVectorImpl<ISD::InputArg> &Ins,
DebugLoc dl, SelectionDAG &DAG, DebugLoc dl, SelectionDAG &DAG,
SmallVectorImpl<SDValue> &InVals) { SmallVectorImpl<SDValue> &InVals) const {
assert(0 && "Not Implemented"); assert(0 && "Not Implemented");
return SDValue(); // this is here to silence compiler errors return SDValue(); // this is here to silence compiler errors
} }
@ -1145,7 +1145,7 @@ public:
bool isVarArg, bool isInreg, unsigned NumFixedArgs, bool isVarArg, bool isInreg, unsigned NumFixedArgs,
CallingConv::ID CallConv, bool isTailCall, CallingConv::ID CallConv, bool isTailCall,
bool isReturnValueUsed, SDValue Callee, ArgListTy &Args, bool isReturnValueUsed, SDValue Callee, ArgListTy &Args,
SelectionDAG &DAG, DebugLoc dl); SelectionDAG &DAG, DebugLoc dl) const;
/// LowerCall - This hook must be implemented to lower calls into the /// LowerCall - This hook must be implemented to lower calls into the
/// the specified DAG. The outgoing arguments to the call are described /// the specified DAG. The outgoing arguments to the call are described
@ -1159,7 +1159,7 @@ public:
const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<ISD::OutputArg> &Outs,
const SmallVectorImpl<ISD::InputArg> &Ins, const SmallVectorImpl<ISD::InputArg> &Ins,
DebugLoc dl, SelectionDAG &DAG, DebugLoc dl, SelectionDAG &DAG,
SmallVectorImpl<SDValue> &InVals) { SmallVectorImpl<SDValue> &InVals) const {
assert(0 && "Not Implemented"); assert(0 && "Not Implemented");
return SDValue(); // this is here to silence compiler errors return SDValue(); // this is here to silence compiler errors
} }
@ -1171,11 +1171,12 @@ public:
virtual bool CanLowerReturn(CallingConv::ID CallConv, bool isVarArg, virtual bool CanLowerReturn(CallingConv::ID CallConv, bool isVarArg,
const SmallVectorImpl<EVT> &OutTys, const SmallVectorImpl<EVT> &OutTys,
const SmallVectorImpl<ISD::ArgFlagsTy> &ArgsFlags, const SmallVectorImpl<ISD::ArgFlagsTy> &ArgsFlags,
SelectionDAG &DAG) SelectionDAG &DAG) const
{ {
// Return true by default to get preexisting behavior. // Return true by default to get preexisting behavior.
return true; return true;
} }
/// LowerReturn - This hook must be implemented to lower outgoing /// LowerReturn - This hook must be implemented to lower outgoing
/// return values, described by the Outs array, into the specified /// return values, described by the Outs array, into the specified
/// DAG. The implementation should return the resulting token chain /// DAG. The implementation should return the resulting token chain
@ -1184,7 +1185,7 @@ public:
virtual SDValue virtual SDValue
LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<ISD::OutputArg> &Outs,
DebugLoc dl, SelectionDAG &DAG) { DebugLoc dl, SelectionDAG &DAG) const {
assert(0 && "Not Implemented"); assert(0 && "Not Implemented");
return SDValue(); // this is here to silence compiler errors return SDValue(); // this is here to silence compiler errors
} }
@ -1209,7 +1210,7 @@ public:
SDValue Op3, unsigned Align, bool isVolatile, SDValue Op3, unsigned Align, bool isVolatile,
bool AlwaysInline, bool AlwaysInline,
const Value *DstSV, uint64_t DstOff, const Value *DstSV, uint64_t DstOff,
const Value *SrcSV, uint64_t SrcOff) { const Value *SrcSV, uint64_t SrcOff) const {
return SDValue(); return SDValue();
} }
@ -1225,7 +1226,7 @@ public:
SDValue Op1, SDValue Op2, SDValue Op1, SDValue Op2,
SDValue Op3, unsigned Align, bool isVolatile, SDValue Op3, unsigned Align, bool isVolatile,
const Value *DstSV, uint64_t DstOff, const Value *DstSV, uint64_t DstOff,
const Value *SrcSV, uint64_t SrcOff) { const Value *SrcSV, uint64_t SrcOff) const {
return SDValue(); return SDValue();
} }
@ -1240,7 +1241,7 @@ public:
SDValue Chain, SDValue Chain,
SDValue Op1, SDValue Op2, SDValue Op1, SDValue Op2,
SDValue Op3, unsigned Align, bool isVolatile, SDValue Op3, unsigned Align, bool isVolatile,
const Value *DstSV, uint64_t DstOff) { const Value *DstSV, uint64_t DstOff) const {
return SDValue(); return SDValue();
} }
@ -1258,14 +1259,14 @@ public:
/// The default implementation calls LowerOperation. /// The default implementation calls LowerOperation.
virtual void LowerOperationWrapper(SDNode *N, virtual void LowerOperationWrapper(SDNode *N,
SmallVectorImpl<SDValue> &Results, SmallVectorImpl<SDValue> &Results,
SelectionDAG &DAG); SelectionDAG &DAG) const;
/// LowerOperation - This callback is invoked for operations that are /// LowerOperation - This callback is invoked for operations that are
/// unsupported by the target, which are registered to use 'custom' lowering, /// unsupported by the target, which are registered to use 'custom' lowering,
/// and whose defined values are all legal. /// and whose defined values are all legal.
/// If the target has no operations that require custom lowering, it need not /// If the target has no operations that require custom lowering, it need not
/// implement this. The default implementation of this aborts. /// implement this. The default implementation of this aborts.
virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG); virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
/// ReplaceNodeResults - This callback is invoked when a node result type is /// ReplaceNodeResults - This callback is invoked when a node result type is
/// illegal for the target, and the operation was registered to use 'custom' /// illegal for the target, and the operation was registered to use 'custom'
@ -1277,7 +1278,7 @@ public:
/// If the target has no operations that require custom lowering, it need not /// If the target has no operations that require custom lowering, it need not
/// implement this. The default implementation aborts. /// implement this. The default implementation aborts.
virtual void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue> &Results, virtual void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue> &Results,
SelectionDAG &DAG) { SelectionDAG &DAG) const {
assert(0 && "ReplaceNodeResults not implemented for this target!"); assert(0 && "ReplaceNodeResults not implemented for this target!");
} }
@ -1295,7 +1296,7 @@ public:
#ifndef NDEBUG #ifndef NDEBUG
, SmallSet<const Instruction *, 8> &CatchInfoLost , SmallSet<const Instruction *, 8> &CatchInfoLost
#endif #endif
) { ) const {
return 0; return 0;
} }

4
llvm/include/llvm/Target/TargetMachine.h
View File

@ -106,8 +106,8 @@ public:
// //
virtual const TargetInstrInfo *getInstrInfo() const { return 0; } virtual const TargetInstrInfo *getInstrInfo() const { return 0; }
virtual const TargetFrameInfo *getFrameInfo() const { return 0; } virtual const TargetFrameInfo *getFrameInfo() const { return 0; }
virtual TargetLowering *getTargetLowering() const { return 0; } virtual const TargetLowering *getTargetLowering() const { return 0; }
virtual TargetSelectionDAGInfo *getSelectionDAGInfo() const{ return 0; } virtual const TargetSelectionDAGInfo *getSelectionDAGInfo() const{ return 0; }
virtual const TargetData *getTargetData() const { return 0; } virtual const TargetData *getTargetData() const { return 0; }
/// getMCAsmInfo - Return target specific asm information. /// getMCAsmInfo - Return target specific asm information.

2
llvm/lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp
View File

@ -152,7 +152,7 @@ static bool isOnlyUsedInEntryBlock(const Argument *A, bool EnableFastISel) {
return true; return true;
} }
FunctionLoweringInfo::FunctionLoweringInfo(TargetLowering &tli) FunctionLoweringInfo::FunctionLoweringInfo(const TargetLowering &tli)
: TLI(tli) { : TLI(tli) {
} }

4
llvm/lib/CodeGen/SelectionDAG/FunctionLoweringInfo.h
View File

@ -47,7 +47,7 @@ class Value;
/// ///
class FunctionLoweringInfo { class FunctionLoweringInfo {
public: public:
TargetLowering &TLI; const TargetLowering &TLI;
const Function *Fn; const Function *Fn;
MachineFunction *MF; MachineFunction *MF;
MachineRegisterInfo *RegInfo; MachineRegisterInfo *RegInfo;
@ -88,7 +88,7 @@ public:
/// register number offset by 'FirstVirtualRegister'. /// register number offset by 'FirstVirtualRegister'.
std::vector<LiveOutInfo> LiveOutRegInfo; std::vector<LiveOutInfo> LiveOutRegInfo;
explicit FunctionLoweringInfo(TargetLowering &TLI); explicit FunctionLoweringInfo(const TargetLowering &TLI);
/// set - Initialize this FunctionLoweringInfo with the given Function /// set - Initialize this FunctionLoweringInfo with the given Function
/// and its associated MachineFunction. /// and its associated MachineFunction.

2
llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
View File

@ -53,7 +53,7 @@ using namespace llvm;
/// ///
namespace { namespace {
class SelectionDAGLegalize { class SelectionDAGLegalize {
TargetLowering &TLI; const TargetLowering &TLI;
SelectionDAG &DAG; SelectionDAG &DAG;
CodeGenOpt::Level OptLevel; CodeGenOpt::Level OptLevel;

2
llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h
View File

@ -33,7 +33,7 @@ namespace llvm {
/// into small values. /// into small values.
/// ///
class VISIBILITY_HIDDEN DAGTypeLegalizer { class VISIBILITY_HIDDEN DAGTypeLegalizer {
TargetLowering &TLI; const TargetLowering &TLI;
SelectionDAG &DAG; SelectionDAG &DAG;
public: public:
// NodeIdFlags - This pass uses the NodeId on the SDNodes to hold information // NodeIdFlags - This pass uses the NodeId on the SDNodes to hold information

2
llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp
View File

@ -34,7 +34,7 @@ using namespace llvm;
namespace { namespace {
class VectorLegalizer { class VectorLegalizer {
SelectionDAG& DAG; SelectionDAG& DAG;
TargetLowering& TLI; const TargetLowering &TLI;
bool Changed; // Keep track of whether anything changed bool Changed; // Keep track of whether anything changed
/// LegalizedNodes - For nodes that are of legal width, and that have more /// LegalizedNodes - For nodes that are of legal width, and that have more

2
llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
View File

@ -792,7 +792,7 @@ unsigned SelectionDAG::getEVTAlignment(EVT VT) const {
} }
// EntryNode could meaningfully have debug info if we can find it... // EntryNode could meaningfully have debug info if we can find it...
SelectionDAG::SelectionDAG(TargetLowering &tli, FunctionLoweringInfo &fli) SelectionDAG::SelectionDAG(const TargetLowering &tli, FunctionLoweringInfo &fli)
: TLI(tli), FLI(fli), : TLI(tli), FLI(fli),
EntryNode(ISD::EntryToken, DebugLoc(), getVTList(MVT::Other)), EntryNode(ISD::EntryToken, DebugLoc(), getVTList(MVT::Other)),
Root(getEntryNode()), Ordering(0) { Root(getEntryNode()), Ordering(0) {

9
llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
View File

@ -757,7 +757,7 @@ SDValue SelectionDAGBuilder::getValue(const Value *V) {
static void getReturnInfo(const Type* ReturnType, static void getReturnInfo(const Type* ReturnType,
Attributes attr, SmallVectorImpl<EVT> &OutVTs, Attributes attr, SmallVectorImpl<EVT> &OutVTs,
SmallVectorImpl<ISD::ArgFlagsTy> &OutFlags, SmallVectorImpl<ISD::ArgFlagsTy> &OutFlags,
TargetLowering &TLI, const TargetLowering &TLI,
SmallVectorImpl<uint64_t> *Offsets = 0) { SmallVectorImpl<uint64_t> *Offsets = 0) {
SmallVector<EVT, 4> ValueVTs; SmallVector<EVT, 4> ValueVTs;
ComputeValueVTs(TLI, ReturnType, ValueVTs); ComputeValueVTs(TLI, ReturnType, ValueVTs);
@ -5648,7 +5648,8 @@ TargetLowering::LowerCallTo(SDValue Chain, const Type *RetTy,
CallingConv::ID CallConv, bool isTailCall, CallingConv::ID CallConv, bool isTailCall,
bool isReturnValueUsed, bool isReturnValueUsed,
SDValue Callee, SDValue Callee,
ArgListTy &Args, SelectionDAG &DAG, DebugLoc dl) { ArgListTy &Args, SelectionDAG &DAG,
DebugLoc dl) const {
// Handle all of the outgoing arguments. // Handle all of the outgoing arguments.
SmallVector<ISD::OutputArg, 32> Outs; SmallVector<ISD::OutputArg, 32> Outs;
for (unsigned i = 0, e = Args.size(); i != e; ++i) { for (unsigned i = 0, e = Args.size(); i != e; ++i) {
@ -5799,13 +5800,13 @@ TargetLowering::LowerCallTo(SDValue Chain, const Type *RetTy,
void TargetLowering::LowerOperationWrapper(SDNode *N, void TargetLowering::LowerOperationWrapper(SDNode *N,
SmallVectorImpl<SDValue> &Results, SmallVectorImpl<SDValue> &Results,
SelectionDAG &DAG) { SelectionDAG &DAG) const {
SDValue Res = LowerOperation(SDValue(N, 0), DAG); SDValue Res = LowerOperation(SDValue(N, 0), DAG);
if (Res.getNode()) if (Res.getNode())
Results.push_back(Res); Results.push_back(Res);
} }
SDValue TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) { SDValue TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
llvm_unreachable("LowerOperation not implemented for this target!"); llvm_unreachable("LowerOperation not implemented for this target!");
return SDValue(); return SDValue();
} }

4
llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.h
View File

@ -257,7 +257,7 @@ public:
// TLI - This is information that describes the available target features we // TLI - This is information that describes the available target features we
// need for lowering. This indicates when operations are unavailable, // need for lowering. This indicates when operations are unavailable,
// implemented with a libcall, etc. // implemented with a libcall, etc.
TargetLowering &TLI; const TargetLowering &TLI;
SelectionDAG &DAG; SelectionDAG &DAG;
const TargetData *TD; const TargetData *TD;
AliasAnalysis *AA; AliasAnalysis *AA;
@ -303,7 +303,7 @@ public:
LLVMContext *Context; LLVMContext *Context;
SelectionDAGBuilder(SelectionDAG &dag, TargetLowering &tli, SelectionDAGBuilder(SelectionDAG &dag, const TargetLowering &tli,
FunctionLoweringInfo &funcinfo, FunctionLoweringInfo &funcinfo,
CodeGenOpt::Level ol) CodeGenOpt::Level ol)
: SDNodeOrder(0), TLI(tli), DAG(dag), FuncInfo(funcinfo), OptLevel(ol), : SDNodeOrder(0), TLI(tli), DAG(dag), FuncInfo(funcinfo), OptLevel(ol),

6
llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
View File

@ -1304,7 +1304,8 @@ bool SelectionDAGISel::IsProfitableToFold(SDValue N, SDNode *U,
/// IsLegalToFold - Returns true if the specific operand node N of /// IsLegalToFold - Returns true if the specific operand node N of
/// U can be folded during instruction selection that starts at Root. /// U can be folded during instruction selection that starts at Root.
bool SelectionDAGISel::IsLegalToFold(SDValue N, SDNode *U, SDNode *Root, bool SelectionDAGISel::IsLegalToFold(SDValue N, SDNode *U, SDNode *Root,
bool IgnoreChains) const { CodeGenOpt::Level OptLevel,
bool IgnoreChains) {
if (OptLevel == CodeGenOpt::None) return false; if (OptLevel == CodeGenOpt::None) return false;
// If Root use can somehow reach N through a path that that doesn't contain // If Root use can somehow reach N through a path that that doesn't contain
@ -2255,7 +2256,8 @@ SelectCodeCommon(SDNode *NodeToMatch, const unsigned char *MatcherTable,
if (!IsProfitableToFold(N, NodeStack[NodeStack.size()-2].getNode(), if (!IsProfitableToFold(N, NodeStack[NodeStack.size()-2].getNode(),
NodeToMatch) || NodeToMatch) ||
!IsLegalToFold(N, NodeStack[NodeStack.size()-2].getNode(), !IsLegalToFold(N, NodeStack[NodeStack.size()-2].getNode(),
NodeToMatch, true/*We validate our own chains*/)) NodeToMatch, OptLevel,
true/*We validate our own chains*/))
break; break;
continue; continue;

1
llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
View File

@ -13,7 +13,6 @@
#include "ARM.h" #include "ARM.h"
#include "ARMAddressingModes.h" #include "ARMAddressingModes.h"
#include "ARMISelLowering.h"
#include "ARMTargetMachine.h" #include "ARMTargetMachine.h"
#include "llvm/CallingConv.h" #include "llvm/CallingConv.h"
#include "llvm/Constants.h" #include "llvm/Constants.h"

63
llvm/lib/Target/ARM/ARMISelLowering.cpp
View File

@ -788,7 +788,7 @@ ARMTargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
CallingConv::ID CallConv, bool isVarArg, CallingConv::ID CallConv, bool isVarArg,
const SmallVectorImpl<ISD::InputArg> &Ins, const SmallVectorImpl<ISD::InputArg> &Ins,
DebugLoc dl, SelectionDAG &DAG, DebugLoc dl, SelectionDAG &DAG,
SmallVectorImpl<SDValue> &InVals) { SmallVectorImpl<SDValue> &InVals) const {
// Assign locations to each value returned by this call. // Assign locations to each value returned by this call.
SmallVector<CCValAssign, 16> RVLocs; SmallVector<CCValAssign, 16> RVLocs;
@ -876,7 +876,7 @@ ARMTargetLowering::LowerMemOpCallTo(SDValue Chain,
SDValue StackPtr, SDValue Arg, SDValue StackPtr, SDValue Arg,
DebugLoc dl, SelectionDAG &DAG, DebugLoc dl, SelectionDAG &DAG,
const CCValAssign &VA, const CCValAssign &VA,
ISD::ArgFlagsTy Flags) { ISD::ArgFlagsTy Flags) const {
unsigned LocMemOffset = VA.getLocMemOffset(); unsigned LocMemOffset = VA.getLocMemOffset();
SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset); SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff); PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
@ -894,7 +894,7 @@ void ARMTargetLowering::PassF64ArgInRegs(DebugLoc dl, SelectionDAG &DAG,
CCValAssign &VA, CCValAssign &NextVA, CCValAssign &VA, CCValAssign &NextVA,
SDValue &StackPtr, SDValue &StackPtr,
SmallVector<SDValue, 8> &MemOpChains, SmallVector<SDValue, 8> &MemOpChains,
ISD::ArgFlagsTy Flags) { ISD::ArgFlagsTy Flags) const {
SDValue fmrrd = DAG.getNode(ARMISD::VMOVRRD, dl, SDValue fmrrd = DAG.getNode(ARMISD::VMOVRRD, dl,
DAG.getVTList(MVT::i32, MVT::i32), Arg); DAG.getVTList(MVT::i32, MVT::i32), Arg);
@ -923,7 +923,7 @@ ARMTargetLowering::LowerCall(SDValue Chain, SDValue Callee,
const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<ISD::OutputArg> &Outs,
const SmallVectorImpl<ISD::InputArg> &Ins, const SmallVectorImpl<ISD::InputArg> &Ins,
DebugLoc dl, SelectionDAG &DAG, DebugLoc dl, SelectionDAG &DAG,
SmallVectorImpl<SDValue> &InVals) { SmallVectorImpl<SDValue> &InVals) const {
// ARM target does not yet support tail call optimization. // ARM target does not yet support tail call optimization.
isTailCall = false; isTailCall = false;
@ -1166,7 +1166,7 @@ SDValue
ARMTargetLowering::LowerReturn(SDValue Chain, ARMTargetLowering::LowerReturn(SDValue Chain,
CallingConv::ID CallConv, bool isVarArg, CallingConv::ID CallConv, bool isVarArg,
const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<ISD::OutputArg> &Outs,
DebugLoc dl, SelectionDAG &DAG) { DebugLoc dl, SelectionDAG &DAG) const {
// CCValAssign - represent the assignment of the return value to a location. // CCValAssign - represent the assignment of the return value to a location.
SmallVector<CCValAssign, 16> RVLocs; SmallVector<CCValAssign, 16> RVLocs;
@ -1273,7 +1273,8 @@ static SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) {
return DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Res); return DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Res);
} }
SDValue ARMTargetLowering::LowerBlockAddress(SDValue Op, SelectionDAG &DAG) { SDValue ARMTargetLowering::LowerBlockAddress(SDValue Op,
SelectionDAG &DAG) const {
MachineFunction &MF = DAG.getMachineFunction(); MachineFunction &MF = DAG.getMachineFunction();
ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
unsigned ARMPCLabelIndex = 0; unsigned ARMPCLabelIndex = 0;
@ -1305,7 +1306,7 @@ SDValue ARMTargetLowering::LowerBlockAddress(SDValue Op, SelectionDAG &DAG) {
// Lower ISD::GlobalTLSAddress using the "general dynamic" model // Lower ISD::GlobalTLSAddress using the "general dynamic" model
SDValue SDValue
ARMTargetLowering::LowerToTLSGeneralDynamicModel(GlobalAddressSDNode *GA, ARMTargetLowering::LowerToTLSGeneralDynamicModel(GlobalAddressSDNode *GA,
SelectionDAG &DAG) { SelectionDAG &DAG) const {
DebugLoc dl = GA->getDebugLoc(); DebugLoc dl = GA->getDebugLoc();
EVT PtrVT = getPointerTy(); EVT PtrVT = getPointerTy();
unsigned char PCAdj = Subtarget->isThumb() ? 4 : 8; unsigned char PCAdj = Subtarget->isThumb() ? 4 : 8;
@ -1344,7 +1345,7 @@ ARMTargetLowering::LowerToTLSGeneralDynamicModel(GlobalAddressSDNode *GA,
// "local exec" model. // "local exec" model.
SDValue SDValue
ARMTargetLowering::LowerToTLSExecModels(GlobalAddressSDNode *GA, ARMTargetLowering::LowerToTLSExecModels(GlobalAddressSDNode *GA,
SelectionDAG &DAG) { SelectionDAG &DAG) const {
const GlobalValue *GV = GA->getGlobal(); const GlobalValue *GV = GA->getGlobal();
DebugLoc dl = GA->getDebugLoc(); DebugLoc dl = GA->getDebugLoc();
SDValue Offset; SDValue Offset;
@ -1391,7 +1392,7 @@ ARMTargetLowering::LowerToTLSExecModels(GlobalAddressSDNode *GA,
} }
SDValue SDValue
ARMTargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) { ARMTargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const {
// TODO: implement the "local dynamic" model // TODO: implement the "local dynamic" model
assert(Subtarget->isTargetELF() && assert(Subtarget->isTargetELF() &&
"TLS not implemented for non-ELF targets"); "TLS not implemented for non-ELF targets");
@ -1405,7 +1406,7 @@ ARMTargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) {
} }
SDValue ARMTargetLowering::LowerGlobalAddressELF(SDValue Op, SDValue ARMTargetLowering::LowerGlobalAddressELF(SDValue Op,
SelectionDAG &DAG) { SelectionDAG &DAG) const {
EVT PtrVT = getPointerTy(); EVT PtrVT = getPointerTy();
DebugLoc dl = Op.getDebugLoc(); DebugLoc dl = Op.getDebugLoc();
const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal(); const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
@ -1445,7 +1446,7 @@ SDValue ARMTargetLowering::LowerGlobalAddressELF(SDValue Op,
} }
SDValue ARMTargetLowering::LowerGlobalAddressDarwin(SDValue Op, SDValue ARMTargetLowering::LowerGlobalAddressDarwin(SDValue Op,
SelectionDAG &DAG) { SelectionDAG &DAG) const {
MachineFunction &MF = DAG.getMachineFunction(); MachineFunction &MF = DAG.getMachineFunction();
ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
unsigned ARMPCLabelIndex = 0; unsigned ARMPCLabelIndex = 0;
@ -1484,7 +1485,7 @@ SDValue ARMTargetLowering::LowerGlobalAddressDarwin(SDValue Op,
} }
SDValue ARMTargetLowering::LowerGLOBAL_OFFSET_TABLE(SDValue Op, SDValue ARMTargetLowering::LowerGLOBAL_OFFSET_TABLE(SDValue Op,
SelectionDAG &DAG){ SelectionDAG &DAG) const {
assert(Subtarget->isTargetELF() && assert(Subtarget->isTargetELF() &&
"GLOBAL OFFSET TABLE not implemented for non-ELF targets"); "GLOBAL OFFSET TABLE not implemented for non-ELF targets");
MachineFunction &MF = DAG.getMachineFunction(); MachineFunction &MF = DAG.getMachineFunction();
@ -1507,7 +1508,8 @@ SDValue ARMTargetLowering::LowerGLOBAL_OFFSET_TABLE(SDValue Op,
SDValue SDValue
ARMTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG, ARMTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG,
const ARMSubtarget *Subtarget) { const ARMSubtarget *Subtarget)
const {
unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue(); unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
DebugLoc dl = Op.getDebugLoc(); DebugLoc dl = Op.getDebugLoc();
switch (IntNo) { switch (IntNo) {
@ -1589,7 +1591,8 @@ static SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) {
} }
SDValue SDValue
ARMTargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) { ARMTargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
SelectionDAG &DAG) const {
SDNode *Node = Op.getNode(); SDNode *Node = Op.getNode();
DebugLoc dl = Node->getDebugLoc(); DebugLoc dl = Node->getDebugLoc();
EVT VT = Node->getValueType(0); EVT VT = Node->getValueType(0);
@ -1638,7 +1641,7 @@ ARMTargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) {
SDValue SDValue
ARMTargetLowering::GetF64FormalArgument(CCValAssign &VA, CCValAssign &NextVA, ARMTargetLowering::GetF64FormalArgument(CCValAssign &VA, CCValAssign &NextVA,
SDValue &Root, SelectionDAG &DAG, SDValue &Root, SelectionDAG &DAG,
DebugLoc dl) { DebugLoc dl) const {
MachineFunction &MF = DAG.getMachineFunction(); MachineFunction &MF = DAG.getMachineFunction();
ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
@ -1676,7 +1679,8 @@ ARMTargetLowering::LowerFormalArguments(SDValue Chain,
const SmallVectorImpl<ISD::InputArg> const SmallVectorImpl<ISD::InputArg>
&Ins, &Ins,
DebugLoc dl, SelectionDAG &DAG, DebugLoc dl, SelectionDAG &DAG,
SmallVectorImpl<SDValue> &InVals) { SmallVectorImpl<SDValue> &InVals)
const {
MachineFunction &MF = DAG.getMachineFunction(); MachineFunction &MF = DAG.getMachineFunction();
MachineFrameInfo *MFI = MF.getFrameInfo(); MachineFrameInfo *MFI = MF.getFrameInfo();
@ -1864,7 +1868,8 @@ static bool isFloatingPointZero(SDValue Op) {
/// the given operands. /// the given operands.
SDValue SDValue
ARMTargetLowering::getARMCmp(SDValue LHS, SDValue RHS, ISD::CondCode CC, ARMTargetLowering::getARMCmp(SDValue LHS, SDValue RHS, ISD::CondCode CC,
SDValue &ARMCC, SelectionDAG &DAG, DebugLoc dl) { SDValue &ARMCC, SelectionDAG &DAG,
DebugLoc dl) const {
if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS.getNode())) { if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS.getNode())) {
unsigned C = RHSC->getZExtValue(); unsigned C = RHSC->getZExtValue();
if (!isLegalICmpImmediate(C)) { if (!isLegalICmpImmediate(C)) {
@ -1930,7 +1935,7 @@ static SDValue getVFPCmp(SDValue LHS, SDValue RHS, SelectionDAG &DAG,
return DAG.getNode(ARMISD::FMSTAT, dl, MVT::Flag, Cmp); return DAG.getNode(ARMISD::FMSTAT, dl, MVT::Flag, Cmp);
} }
SDValue ARMTargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) { SDValue ARMTargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const {
EVT VT = Op.getValueType(); EVT VT = Op.getValueType();
SDValue LHS = Op.getOperand(0); SDValue LHS = Op.getOperand(0);
SDValue RHS = Op.getOperand(1); SDValue RHS = Op.getOperand(1);
@ -1964,7 +1969,7 @@ SDValue ARMTargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) {
return Result; return Result;
} }
SDValue ARMTargetLowering::LowerBR_CC(SDValue Op, SelectionDAG &DAG) { SDValue ARMTargetLowering::LowerBR_CC(SDValue Op, SelectionDAG &DAG) const {
SDValue Chain = Op.getOperand(0); SDValue Chain = Op.getOperand(0);
ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get(); ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
SDValue LHS = Op.getOperand(2); SDValue LHS = Op.getOperand(2);
@ -1998,7 +2003,7 @@ SDValue ARMTargetLowering::LowerBR_CC(SDValue Op, SelectionDAG &DAG) {
return Res; return Res;
} }
SDValue ARMTargetLowering::LowerBR_JT(SDValue Op, SelectionDAG &DAG) { SDValue ARMTargetLowering::LowerBR_JT(SDValue Op, SelectionDAG &DAG) const {
SDValue Chain = Op.getOperand(0); SDValue Chain = Op.getOperand(0);
SDValue Table = Op.getOperand(1); SDValue Table = Op.getOperand(1);
SDValue Index = Op.getOperand(2); SDValue Index = Op.getOperand(2);
@ -2087,7 +2092,7 @@ static SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) {
return DAG.getNode(ARMISD::CNEG, dl, VT, AbsVal, AbsVal, ARMCC, CCR, Cmp); return DAG.getNode(ARMISD::CNEG, dl, VT, AbsVal, AbsVal, ARMCC, CCR, Cmp);
} }
SDValue ARMTargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) { SDValue ARMTargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const {
MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
MFI->setFrameAddressIsTaken(true); MFI->setFrameAddressIsTaken(true);
EVT VT = Op.getValueType(); EVT VT = Op.getValueType();
@ -2108,8 +2113,10 @@ ARMTargetLowering::EmitTargetCodeForMemcpy(SelectionDAG &DAG, DebugLoc dl,
SDValue Dst, SDValue Src, SDValue Dst, SDValue Src,
SDValue Size, unsigned Align, SDValue Size, unsigned Align,
bool isVolatile, bool AlwaysInline, bool isVolatile, bool AlwaysInline,
const Value *DstSV, uint64_t DstSVOff, const Value *DstSV,
const Value *SrcSV, uint64_t SrcSVOff){ uint64_t DstSVOff,
const Value *SrcSV,
uint64_t SrcSVOff) const {
// Do repeated 4-byte loads and stores. To be improved. // Do repeated 4-byte loads and stores. To be improved.
// This requires 4-byte alignment. // This requires 4-byte alignment.
if ((Align & 3) != 0) if ((Align & 3) != 0)
@ -2297,7 +2304,8 @@ static SDValue getOnesVector(EVT VT, SelectionDAG &DAG, DebugLoc dl) {
/// LowerShiftRightParts - Lower SRA_PARTS, which returns two /// LowerShiftRightParts - Lower SRA_PARTS, which returns two
/// i32 values and take a 2 x i32 value to shift plus a shift amount. /// i32 values and take a 2 x i32 value to shift plus a shift amount.
SDValue ARMTargetLowering::LowerShiftRightParts(SDValue Op, SelectionDAG &DAG) { SDValue ARMTargetLowering::LowerShiftRightParts(SDValue Op,
SelectionDAG &DAG) const {
assert(Op.getNumOperands() == 3 && "Not a double-shift!"); assert(Op.getNumOperands() == 3 && "Not a double-shift!");
EVT VT = Op.getValueType(); EVT VT = Op.getValueType();
unsigned VTBits = VT.getSizeInBits(); unsigned VTBits = VT.getSizeInBits();
@ -2332,7 +2340,8 @@ SDValue ARMTargetLowering::LowerShiftRightParts(SDValue Op, SelectionDAG &DAG) {
/// LowerShiftLeftParts - Lower SHL_PARTS, which returns two /// LowerShiftLeftParts - Lower SHL_PARTS, which returns two
/// i32 values and take a 2 x i32 value to shift plus a shift amount. /// i32 values and take a 2 x i32 value to shift plus a shift amount.
SDValue ARMTargetLowering::LowerShiftLeftParts(SDValue Op, SelectionDAG &DAG) { SDValue ARMTargetLowering::LowerShiftLeftParts(SDValue Op,
SelectionDAG &DAG) const {
assert(Op.getNumOperands() == 3 && "Not a double-shift!"); assert(Op.getNumOperands() == 3 && "Not a double-shift!");
EVT VT = Op.getValueType(); EVT VT = Op.getValueType();
unsigned VTBits = VT.getSizeInBits(); unsigned VTBits = VT.getSizeInBits();
@ -3129,7 +3138,7 @@ static SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
return DAG.getNode(ISD::BIT_CONVERT, dl, Op.getValueType(), Val); return DAG.getNode(ISD::BIT_CONVERT, dl, Op.getValueType(), Val);
} }
SDValue ARMTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) { SDValue ARMTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
switch (Op.getOpcode()) { switch (Op.getOpcode()) {
default: llvm_unreachable("Don't know how to custom lower this!"); default: llvm_unreachable("Don't know how to custom lower this!");
case ISD::ConstantPool: return LowerConstantPool(Op, DAG); case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
@ -3175,7 +3184,7 @@ SDValue ARMTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) {
/// type with new values built out of custom code. /// type with new values built out of custom code.
void ARMTargetLowering::ReplaceNodeResults(SDNode *N, void ARMTargetLowering::ReplaceNodeResults(SDNode *N,
SmallVectorImpl<SDValue>&Results, SmallVectorImpl<SDValue>&Results,
SelectionDAG &DAG) { SelectionDAG &DAG) const {
SDValue Res; SDValue Res;
switch (N->getOpcode()) { switch (N->getOpcode()) {
default: default:

61
llvm/lib/Target/ARM/ARMISelLowering.h
View File

@ -162,13 +162,13 @@ namespace llvm {
public: public:
explicit ARMTargetLowering(TargetMachine &TM); explicit ARMTargetLowering(TargetMachine &TM);
virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG); virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
/// ReplaceNodeResults - Replace the results of node with an illegal result /// ReplaceNodeResults - Replace the results of node with an illegal result
/// type with new values built out of custom code. /// type with new values built out of custom code.
/// ///
virtual void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results, virtual void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results,
SelectionDAG &DAG); SelectionDAG &DAG) const;
virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const; virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
@ -236,7 +236,7 @@ namespace llvm {
std::vector<SDValue> &Ops, std::vector<SDValue> &Ops,
SelectionDAG &DAG) const; SelectionDAG &DAG) const;
virtual const ARMSubtarget* getSubtarget() { virtual const ARMSubtarget* getSubtarget() const {
return Subtarget; return Subtarget;
} }
@ -271,54 +271,57 @@ namespace llvm {
CCValAssign &VA, CCValAssign &NextVA, CCValAssign &VA, CCValAssign &NextVA,
SDValue &StackPtr, SDValue &StackPtr,
SmallVector<SDValue, 8> &MemOpChains, SmallVector<SDValue, 8> &MemOpChains,
ISD::ArgFlagsTy Flags); ISD::ArgFlagsTy Flags) const;
SDValue GetF64FormalArgument(CCValAssign &VA, CCValAssign &NextVA, SDValue GetF64FormalArgument(CCValAssign &VA, CCValAssign &NextVA,
SDValue &Root, SelectionDAG &DAG, DebugLoc dl); SDValue &Root, SelectionDAG &DAG,
DebugLoc dl) const;
CCAssignFn *CCAssignFnForNode(CallingConv::ID CC, bool Return, bool isVarArg) const; CCAssignFn *CCAssignFnForNode(CallingConv::ID CC, bool Return, bool isVarArg) const;
SDValue LowerMemOpCallTo(SDValue Chain, SDValue StackPtr, SDValue Arg, SDValue LowerMemOpCallTo(SDValue Chain, SDValue StackPtr, SDValue Arg,
DebugLoc dl, SelectionDAG &DAG, DebugLoc dl, SelectionDAG &DAG,
const CCValAssign &VA, const CCValAssign &VA,
ISD::ArgFlagsTy Flags); ISD::ArgFlagsTy Flags) const;
SDValue LowerINTRINSIC_W_CHAIN(SDValue Op, SelectionDAG &DAG); SDValue LowerINTRINSIC_W_CHAIN(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG, SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG,
const ARMSubtarget *Subtarget); const ARMSubtarget *Subtarget) const;
SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG); SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerGlobalAddressDarwin(SDValue Op, SelectionDAG &DAG); SDValue LowerGlobalAddressDarwin(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerGlobalAddressELF(SDValue Op, SelectionDAG &DAG); SDValue LowerGlobalAddressELF(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG); SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerToTLSGeneralDynamicModel(GlobalAddressSDNode *GA, SDValue LowerToTLSGeneralDynamicModel(GlobalAddressSDNode *GA,
SelectionDAG &DAG); SelectionDAG &DAG) const;
SDValue LowerToTLSExecModels(GlobalAddressSDNode *GA, SDValue LowerToTLSExecModels(GlobalAddressSDNode *GA,
SelectionDAG &DAG); SelectionDAG &DAG) const;
SDValue LowerGLOBAL_OFFSET_TABLE(SDValue Op, SelectionDAG &DAG); SDValue LowerGLOBAL_OFFSET_TABLE(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerBR_JT(SDValue Op, SelectionDAG &DAG); SDValue LowerBR_JT(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG); SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG); SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG); SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG); SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerShiftRightParts(SDValue Op, SelectionDAG &DAG); SDValue LowerShiftRightParts(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerShiftLeftParts(SDValue Op, SelectionDAG &DAG); SDValue LowerShiftLeftParts(SDValue Op, SelectionDAG &DAG) const;
SDValue EmitTargetCodeForMemcpy(SelectionDAG &DAG, DebugLoc dl, SDValue EmitTargetCodeForMemcpy(SelectionDAG &DAG, DebugLoc dl,
SDValue Chain, SDValue Chain,
SDValue Dst, SDValue Src, SDValue Dst, SDValue Src,
SDValue Size, unsigned Align, SDValue Size, unsigned Align,
bool isVolatile, bool AlwaysInline, bool isVolatile, bool AlwaysInline,
const Value *DstSV, uint64_t DstSVOff, const Value *DstSV,
const Value *SrcSV, uint64_t SrcSVOff); uint64_t DstSVOff,
const Value *SrcSV,
uint64_t SrcSVOff) const;
SDValue LowerCallResult(SDValue Chain, SDValue InFlag, SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
CallingConv::ID CallConv, bool isVarArg, CallingConv::ID CallConv, bool isVarArg,
const SmallVectorImpl<ISD::InputArg> &Ins, const SmallVectorImpl<ISD::InputArg> &Ins,
DebugLoc dl, SelectionDAG &DAG, DebugLoc dl, SelectionDAG &DAG,
SmallVectorImpl<SDValue> &InVals); SmallVectorImpl<SDValue> &InVals) const;
virtual SDValue virtual SDValue
LowerFormalArguments(SDValue Chain, LowerFormalArguments(SDValue Chain,
CallingConv::ID CallConv, bool isVarArg, CallingConv::ID CallConv, bool isVarArg,
const SmallVectorImpl<ISD::InputArg> &Ins, const SmallVectorImpl<ISD::InputArg> &Ins,
DebugLoc dl, SelectionDAG &DAG, DebugLoc dl, SelectionDAG &DAG,
SmallVectorImpl<SDValue> &InVals); SmallVectorImpl<SDValue> &InVals) const;
virtual SDValue virtual SDValue
LowerCall(SDValue Chain, SDValue Callee, LowerCall(SDValue Chain, SDValue Callee,
@ -327,16 +330,16 @@ namespace llvm {
const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<ISD::OutputArg> &Outs,
const SmallVectorImpl<ISD::InputArg> &Ins, const SmallVectorImpl<ISD::InputArg> &Ins,
DebugLoc dl, SelectionDAG &DAG, DebugLoc dl, SelectionDAG &DAG,
SmallVectorImpl<SDValue> &InVals); SmallVectorImpl<SDValue> &InVals) const;
virtual SDValue virtual SDValue
LowerReturn(SDValue Chain, LowerReturn(SDValue Chain,
CallingConv::ID CallConv, bool isVarArg, CallingConv::ID CallConv, bool isVarArg,
const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<ISD::OutputArg> &Outs,
DebugLoc dl, SelectionDAG &DAG); DebugLoc dl, SelectionDAG &DAG) const;
SDValue getARMCmp(SDValue LHS, SDValue RHS, ISD::CondCode CC, SDValue getARMCmp(SDValue LHS, SDValue RHS, ISD::CondCode CC,
SDValue &ARMCC, SelectionDAG &DAG, DebugLoc dl); SDValue &ARMCC, SelectionDAG &DAG, DebugLoc dl) const;
MachineBasicBlock *EmitAtomicCmpSwap(MachineInstr *MI, MachineBasicBlock *EmitAtomicCmpSwap(MachineInstr *MI,
MachineBasicBlock *BB, MachineBasicBlock *BB,

8
llvm/lib/Target/ARM/ARMTargetMachine.h
View File

@ -71,8 +71,8 @@ public:
return &InstrInfo.getRegisterInfo(); return &InstrInfo.getRegisterInfo();
} }
virtual ARMTargetLowering *getTargetLowering() const { virtual const ARMTargetLowering *getTargetLowering() const {
return const_cast<ARMTargetLowering*>(&TLInfo); return &TLInfo;
} }
virtual const ARMInstrInfo *getInstrInfo() const { return &InstrInfo; } virtual const ARMInstrInfo *getInstrInfo() const { return &InstrInfo; }
@ -97,8 +97,8 @@ public:
return &InstrInfo->getRegisterInfo(); return &InstrInfo->getRegisterInfo();
} }
virtual ARMTargetLowering *getTargetLowering() const { virtual const ARMTargetLowering *getTargetLowering() const {
return const_cast<ARMTargetLowering*>(&TLInfo); return &TLInfo;
} }
/// returns either Thumb1InstrInfo or Thumb2InstrInfo /// returns either Thumb1InstrInfo or Thumb2InstrInfo

1
llvm/lib/Target/Alpha/AlphaISelDAGToDAG.cpp
View File

@ -14,7 +14,6 @@
#include "Alpha.h" #include "Alpha.h"
#include "AlphaTargetMachine.h" #include "AlphaTargetMachine.h"
#include "AlphaISelLowering.h"
#include "llvm/CodeGen/MachineInstrBuilder.h" #include "llvm/CodeGen/MachineInstrBuilder.h"
#include "llvm/CodeGen/MachineFrameInfo.h" #include "llvm/CodeGen/MachineFrameInfo.h"
#include "llvm/CodeGen/MachineFunction.h" #include "llvm/CodeGen/MachineFunction.h"

17
llvm/lib/Target/Alpha/AlphaISelLowering.cpp
View File

@ -226,7 +226,7 @@ AlphaTargetLowering::LowerCall(SDValue Chain, SDValue Callee,
const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<ISD::OutputArg> &Outs,
const SmallVectorImpl<ISD::InputArg> &Ins, const SmallVectorImpl<ISD::InputArg> &Ins,
DebugLoc dl, SelectionDAG &DAG, DebugLoc dl, SelectionDAG &DAG,
SmallVectorImpl<SDValue> &InVals) { SmallVectorImpl<SDValue> &InVals) const {
// Alpha target does not yet support tail call optimization. // Alpha target does not yet support tail call optimization.
isTailCall = false; isTailCall = false;
@ -343,7 +343,7 @@ AlphaTargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
CallingConv::ID CallConv, bool isVarArg, CallingConv::ID CallConv, bool isVarArg,
const SmallVectorImpl<ISD::InputArg> &Ins, const SmallVectorImpl<ISD::InputArg> &Ins,
DebugLoc dl, SelectionDAG &DAG, DebugLoc dl, SelectionDAG &DAG,
SmallVectorImpl<SDValue> &InVals) { SmallVectorImpl<SDValue> &InVals) const {
// Assign locations to each value returned by this call. // Assign locations to each value returned by this call.
SmallVector<CCValAssign, 16> RVLocs; SmallVector<CCValAssign, 16> RVLocs;
@ -386,7 +386,8 @@ AlphaTargetLowering::LowerFormalArguments(SDValue Chain,
const SmallVectorImpl<ISD::InputArg> const SmallVectorImpl<ISD::InputArg>
&Ins, &Ins,
DebugLoc dl, SelectionDAG &DAG, DebugLoc dl, SelectionDAG &DAG,
SmallVectorImpl<SDValue> &InVals) { SmallVectorImpl<SDValue> &InVals)
const {
MachineFunction &MF = DAG.getMachineFunction(); MachineFunction &MF = DAG.getMachineFunction();
MachineFrameInfo *MFI = MF.getFrameInfo(); MachineFrameInfo *MFI = MF.getFrameInfo();
@ -469,7 +470,7 @@ SDValue
AlphaTargetLowering::LowerReturn(SDValue Chain, AlphaTargetLowering::LowerReturn(SDValue Chain,
CallingConv::ID CallConv, bool isVarArg, CallingConv::ID CallConv, bool isVarArg,
const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<ISD::OutputArg> &Outs,
DebugLoc dl, SelectionDAG &DAG) { DebugLoc dl, SelectionDAG &DAG) const {
SDValue Copy = DAG.getCopyToReg(Chain, dl, Alpha::R26, SDValue Copy = DAG.getCopyToReg(Chain, dl, Alpha::R26,
DAG.getNode(AlphaISD::GlobalRetAddr, DAG.getNode(AlphaISD::GlobalRetAddr,
@ -527,7 +528,8 @@ AlphaTargetLowering::LowerReturn(SDValue Chain,
} }
void AlphaTargetLowering::LowerVAARG(SDNode *N, SDValue &Chain, void AlphaTargetLowering::LowerVAARG(SDNode *N, SDValue &Chain,
SDValue &DataPtr, SelectionDAG &DAG) { SDValue &DataPtr,
SelectionDAG &DAG) const {
Chain = N->getOperand(0); Chain = N->getOperand(0);
SDValue VAListP = N->getOperand(1); SDValue VAListP = N->getOperand(1);
const Value *VAListS = cast<SrcValueSDNode>(N->getOperand(2))->getValue(); const Value *VAListS = cast<SrcValueSDNode>(N->getOperand(2))->getValue();
@ -558,7 +560,8 @@ void AlphaTargetLowering::LowerVAARG(SDNode *N, SDValue &Chain,
/// LowerOperation - Provide custom lowering hooks for some operations. /// LowerOperation - Provide custom lowering hooks for some operations.
/// ///
SDValue AlphaTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) { SDValue AlphaTargetLowering::LowerOperation(SDValue Op,
SelectionDAG &DAG) const {
DebugLoc dl = Op.getDebugLoc(); DebugLoc dl = Op.getDebugLoc();
switch (Op.getOpcode()) { switch (Op.getOpcode()) {
default: llvm_unreachable("Wasn't expecting to be able to lower this!"); default: llvm_unreachable("Wasn't expecting to be able to lower this!");
@ -756,7 +759,7 @@ SDValue AlphaTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) {
void AlphaTargetLowering::ReplaceNodeResults(SDNode *N, void AlphaTargetLowering::ReplaceNodeResults(SDNode *N,
SmallVectorImpl<SDValue>&Results, SmallVectorImpl<SDValue>&Results,
SelectionDAG &DAG) { SelectionDAG &DAG) const {
DebugLoc dl = N->getDebugLoc(); DebugLoc dl = N->getDebugLoc();
assert(N->getValueType(0) == MVT::i32 && assert(N->getValueType(0) == MVT::i32 &&
N->getOpcode() == ISD::VAARG && N->getOpcode() == ISD::VAARG &&

14
llvm/lib/Target/Alpha/AlphaISelLowering.h
View File

@ -68,13 +68,13 @@ namespace llvm {
/// LowerOperation - Provide custom lowering hooks for some operations. /// LowerOperation - Provide custom lowering hooks for some operations.
/// ///
virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG); virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
/// ReplaceNodeResults - Replace the results of node with an illegal result /// ReplaceNodeResults - Replace the results of node with an illegal result
/// type with new values built out of custom code. /// type with new values built out of custom code.
/// ///
virtual void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results, virtual void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results,
SelectionDAG &DAG); SelectionDAG &DAG) const;
// Friendly names for dumps // Friendly names for dumps
const char *getTargetNodeName(unsigned Opcode) const; const char *getTargetNodeName(unsigned Opcode) const;
@ -83,7 +83,7 @@ namespace llvm {
CallingConv::ID CallConv, bool isVarArg, CallingConv::ID CallConv, bool isVarArg,
const SmallVectorImpl<ISD::InputArg> &Ins, const SmallVectorImpl<ISD::InputArg> &Ins,
DebugLoc dl, SelectionDAG &DAG, DebugLoc dl, SelectionDAG &DAG,
SmallVectorImpl<SDValue> &InVals); SmallVectorImpl<SDValue> &InVals) const;
ConstraintType getConstraintType(const std::string &Constraint) const; ConstraintType getConstraintType(const std::string &Constraint) const;
@ -108,14 +108,14 @@ namespace llvm {
private: private:
// Helpers for custom lowering. // Helpers for custom lowering.
void LowerVAARG(SDNode *N, SDValue &Chain, SDValue &DataPtr, void LowerVAARG(SDNode *N, SDValue &Chain, SDValue &DataPtr,
SelectionDAG &DAG); SelectionDAG &DAG) const;
virtual SDValue virtual SDValue
LowerFormalArguments(SDValue Chain, LowerFormalArguments(SDValue Chain,
CallingConv::ID CallConv, bool isVarArg, CallingConv::ID CallConv, bool isVarArg,
const SmallVectorImpl<ISD::InputArg> &Ins, const SmallVectorImpl<ISD::InputArg> &Ins,
DebugLoc dl, SelectionDAG &DAG, DebugLoc dl, SelectionDAG &DAG,
SmallVectorImpl<SDValue> &InVals); SmallVectorImpl<SDValue> &InVals) const;
virtual SDValue virtual SDValue
LowerCall(SDValue Chain, SDValue Callee, LowerCall(SDValue Chain, SDValue Callee,
@ -123,13 +123,13 @@ namespace llvm {
const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<ISD::OutputArg> &Outs,
const SmallVectorImpl<ISD::InputArg> &Ins, const SmallVectorImpl<ISD::InputArg> &Ins,
DebugLoc dl, SelectionDAG &DAG, DebugLoc dl, SelectionDAG &DAG,
SmallVectorImpl<SDValue> &InVals); SmallVectorImpl<SDValue> &InVals) const;
virtual SDValue virtual SDValue
LowerReturn(SDValue Chain, LowerReturn(SDValue Chain,
CallingConv::ID CallConv, bool isVarArg, CallingConv::ID CallConv, bool isVarArg,
const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<ISD::OutputArg> &Outs,
DebugLoc dl, SelectionDAG &DAG); DebugLoc dl, SelectionDAG &DAG) const;
}; };
} }

4
llvm/lib/Target/Alpha/AlphaTargetMachine.h
View File

@ -44,8 +44,8 @@ public:
virtual const AlphaRegisterInfo *getRegisterInfo() const { virtual const AlphaRegisterInfo *getRegisterInfo() const {
return &InstrInfo.getRegisterInfo(); return &InstrInfo.getRegisterInfo();
} }
virtual AlphaTargetLowering* getTargetLowering() const { virtual const AlphaTargetLowering* getTargetLowering() const {
return const_cast<AlphaTargetLowering*>(&TLInfo); return &TLInfo;
} }
virtual const TargetData *getTargetData() const { return &DataLayout; } virtual const TargetData *getTargetData() const { return &DataLayout; }
virtual AlphaJITInfo* getJITInfo() { virtual AlphaJITInfo* getJITInfo() {

1
llvm/lib/Target/Blackfin/BlackfinISelDAGToDAG.cpp
View File

@ -12,7 +12,6 @@
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
#include "Blackfin.h" #include "Blackfin.h"
#include "BlackfinISelLowering.h"
#include "BlackfinTargetMachine.h" #include "BlackfinTargetMachine.h"
#include "BlackfinRegisterInfo.h" #include "BlackfinRegisterInfo.h"
#include "llvm/Intrinsics.h" #include "llvm/Intrinsics.h"

19
llvm/lib/Target/Blackfin/BlackfinISelLowering.cpp
View File

@ -139,7 +139,7 @@ MVT::SimpleValueType BlackfinTargetLowering::getSetCCResultType(EVT VT) const {
} }
SDValue BlackfinTargetLowering::LowerGlobalAddress(SDValue Op, SDValue BlackfinTargetLowering::LowerGlobalAddress(SDValue Op,
SelectionDAG &DAG) { SelectionDAG &DAG) const {
DebugLoc DL = Op.getDebugLoc(); DebugLoc DL = Op.getDebugLoc();
const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal(); const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
@ -147,7 +147,8 @@ SDValue BlackfinTargetLowering::LowerGlobalAddress(SDValue Op,
return DAG.getNode(BFISD::Wrapper, DL, MVT::i32, Op); return DAG.getNode(BFISD::Wrapper, DL, MVT::i32, Op);
} }
SDValue BlackfinTargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) { SDValue BlackfinTargetLowering::LowerJumpTable(SDValue Op,
SelectionDAG &DAG) const {
DebugLoc DL = Op.getDebugLoc(); DebugLoc DL = Op.getDebugLoc();
int JTI = cast<JumpTableSDNode>(Op)->getIndex(); int JTI = cast<JumpTableSDNode>(Op)->getIndex();
@ -161,7 +162,8 @@ BlackfinTargetLowering::LowerFormalArguments(SDValue Chain,
const SmallVectorImpl<ISD::InputArg> const SmallVectorImpl<ISD::InputArg>
&Ins, &Ins,
DebugLoc dl, SelectionDAG &DAG, DebugLoc dl, SelectionDAG &DAG,
SmallVectorImpl<SDValue> &InVals) { SmallVectorImpl<SDValue> &InVals)
const {
MachineFunction &MF = DAG.getMachineFunction(); MachineFunction &MF = DAG.getMachineFunction();
MachineFrameInfo *MFI = MF.getFrameInfo(); MachineFrameInfo *MFI = MF.getFrameInfo();
@ -218,7 +220,7 @@ SDValue
BlackfinTargetLowering::LowerReturn(SDValue Chain, BlackfinTargetLowering::LowerReturn(SDValue Chain,
CallingConv::ID CallConv, bool isVarArg, CallingConv::ID CallConv, bool isVarArg,
const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<ISD::OutputArg> &Outs,
DebugLoc dl, SelectionDAG &DAG) { DebugLoc dl, SelectionDAG &DAG) const {
// CCValAssign - represent the assignment of the return value to locations. // CCValAssign - represent the assignment of the return value to locations.
SmallVector<CCValAssign, 16> RVLocs; SmallVector<CCValAssign, 16> RVLocs;
@ -278,7 +280,7 @@ BlackfinTargetLowering::LowerCall(SDValue Chain, SDValue Callee,
const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<ISD::OutputArg> &Outs,
const SmallVectorImpl<ISD::InputArg> &Ins, const SmallVectorImpl<ISD::InputArg> &Ins,
DebugLoc dl, SelectionDAG &DAG, DebugLoc dl, SelectionDAG &DAG,
SmallVectorImpl<SDValue> &InVals) { SmallVectorImpl<SDValue> &InVals) const {
// Blackfin target does not yet support tail call optimization. // Blackfin target does not yet support tail call optimization.
isTailCall = false; isTailCall = false;
@ -414,7 +416,7 @@ BlackfinTargetLowering::LowerCall(SDValue Chain, SDValue Callee,
// Expansion of ADDE / SUBE. This is a bit involved since blackfin doesn't have // Expansion of ADDE / SUBE. This is a bit involved since blackfin doesn't have
// add-with-carry instructions. // add-with-carry instructions.
SDValue BlackfinTargetLowering::LowerADDE(SDValue Op, SelectionDAG &DAG) { SDValue BlackfinTargetLowering::LowerADDE(SDValue Op, SelectionDAG &DAG) const {
// Operands: lhs, rhs, carry-in (AC0 flag) // Operands: lhs, rhs, carry-in (AC0 flag)
// Results: sum, carry-out (AC0 flag) // Results: sum, carry-out (AC0 flag)
DebugLoc dl = Op.getDebugLoc(); DebugLoc dl = Op.getDebugLoc();
@ -448,7 +450,8 @@ SDValue BlackfinTargetLowering::LowerADDE(SDValue Op, SelectionDAG &DAG) {
return DAG.getMergeValues(ops, 2, dl); return DAG.getMergeValues(ops, 2, dl);
} }
SDValue BlackfinTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) { SDValue BlackfinTargetLowering::LowerOperation(SDValue Op,
SelectionDAG &DAG) const {
switch (Op.getOpcode()) { switch (Op.getOpcode()) {
default: default:
Op.getNode()->dump(); Op.getNode()->dump();
@ -468,7 +471,7 @@ SDValue BlackfinTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) {
void void
BlackfinTargetLowering::ReplaceNodeResults(SDNode *N, BlackfinTargetLowering::ReplaceNodeResults(SDNode *N,
SmallVectorImpl<SDValue> &Results, SmallVectorImpl<SDValue> &Results,
SelectionDAG &DAG) { SelectionDAG &DAG) const {
DebugLoc dl = N->getDebugLoc(); DebugLoc dl = N->getDebugLoc();
switch (N->getOpcode()) { switch (N->getOpcode()) {
default: default:

16
llvm/lib/Target/Blackfin/BlackfinISelLowering.h
View File

@ -33,10 +33,10 @@ namespace llvm {
public: public:
BlackfinTargetLowering(TargetMachine &TM); BlackfinTargetLowering(TargetMachine &TM);
virtual MVT::SimpleValueType getSetCCResultType(EVT VT) const; virtual MVT::SimpleValueType getSetCCResultType(EVT VT) const;
virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG); virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
virtual void ReplaceNodeResults(SDNode *N, virtual void ReplaceNodeResults(SDNode *N,
SmallVectorImpl<SDValue> &Results, SmallVectorImpl<SDValue> &Results,
SelectionDAG &DAG); SelectionDAG &DAG) const;
ConstraintType getConstraintType(const std::string &Constraint) const; ConstraintType getConstraintType(const std::string &Constraint) const;
std::pair<unsigned, const TargetRegisterClass*> std::pair<unsigned, const TargetRegisterClass*>
@ -49,29 +49,29 @@ namespace llvm {
unsigned getFunctionAlignment(const Function *F) const; unsigned getFunctionAlignment(const Function *F) const;
private: private:
SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG); SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG); SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerADDE(SDValue Op, SelectionDAG &DAG); SDValue LowerADDE(SDValue Op, SelectionDAG &DAG) const;
virtual SDValue virtual SDValue
LowerFormalArguments(SDValue Chain, LowerFormalArguments(SDValue Chain,
CallingConv::ID CallConv, bool isVarArg, CallingConv::ID CallConv, bool isVarArg,
const SmallVectorImpl<ISD::InputArg> &Ins, const SmallVectorImpl<ISD::InputArg> &Ins,
DebugLoc dl, SelectionDAG &DAG, DebugLoc dl, SelectionDAG &DAG,
SmallVectorImpl<SDValue> &InVals); SmallVectorImpl<SDValue> &InVals) const;
virtual SDValue virtual SDValue
LowerCall(SDValue Chain, SDValue Callee, LowerCall(SDValue Chain, SDValue Callee,
CallingConv::ID CallConv, bool isVarArg, bool &isTailCall, CallingConv::ID CallConv, bool isVarArg, bool &isTailCall,
const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<ISD::OutputArg> &Outs,
const SmallVectorImpl<ISD::InputArg> &Ins, const SmallVectorImpl<ISD::InputArg> &Ins,
DebugLoc dl, SelectionDAG &DAG, DebugLoc dl, SelectionDAG &DAG,
SmallVectorImpl<SDValue> &InVals); SmallVectorImpl<SDValue> &InVals) const;
virtual SDValue virtual SDValue
LowerReturn(SDValue Chain, LowerReturn(SDValue Chain,
CallingConv::ID CallConv, bool isVarArg, CallingConv::ID CallConv, bool isVarArg,
const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<ISD::OutputArg> &Outs,
DebugLoc dl, SelectionDAG &DAG); DebugLoc dl, SelectionDAG &DAG) const;
}; };
} // end namespace llvm } // end namespace llvm

4
llvm/lib/Target/Blackfin/BlackfinTargetMachine.h
View File

@ -43,8 +43,8 @@ namespace llvm {
virtual const BlackfinRegisterInfo *getRegisterInfo() const { virtual const BlackfinRegisterInfo *getRegisterInfo() const {
return &InstrInfo.getRegisterInfo(); return &InstrInfo.getRegisterInfo();
} }
virtual BlackfinTargetLowering* getTargetLowering() const { virtual const BlackfinTargetLowering* getTargetLowering() const {
return const_cast<BlackfinTargetLowering*>(&TLInfo); return &TLInfo;
} }
virtual const TargetData *getTargetData() const { return &DataLayout; } virtual const TargetData *getTargetData() const { return &DataLayout; }
virtual bool addInstSelector(PassManagerBase &PM, virtual bool addInstSelector(PassManagerBase &PM,

8
llvm/lib/Target/CellSPU/SPUISelDAGToDAG.cpp
View File

@ -14,7 +14,6 @@
#include "SPU.h" #include "SPU.h"
#include "SPUTargetMachine.h" #include "SPUTargetMachine.h"
#include "SPUISelLowering.h"
#include "SPUHazardRecognizers.h" #include "SPUHazardRecognizers.h"
#include "SPUFrameInfo.h" #include "SPUFrameInfo.h"
#include "SPURegisterNames.h" #include "SPURegisterNames.h"
@ -239,8 +238,8 @@ namespace {
class SPUDAGToDAGISel : class SPUDAGToDAGISel :
public SelectionDAGISel public SelectionDAGISel
{ {
SPUTargetMachine &TM; const SPUTargetMachine &TM;
SPUTargetLowering &SPUtli; const SPUTargetLowering &SPUtli;
unsigned GlobalBaseReg; unsigned GlobalBaseReg;
public: public:
@ -310,8 +309,7 @@ namespace {
SDValue CPIdx = CurDAG->getConstantPool(CP, SPUtli.getPointerTy()); SDValue CPIdx = CurDAG->getConstantPool(CP, SPUtli.getPointerTy());
unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment(); unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
SDValue CGPoolOffset = SDValue CGPoolOffset =
SPU::LowerConstantPool(CPIdx, *CurDAG, SPU::LowerConstantPool(CPIdx, *CurDAG, TM);
SPUtli.getSPUTargetMachine());
HandleSDNode Dummy(CurDAG->getLoad(vecVT, dl, HandleSDNode Dummy(CurDAG->getLoad(vecVT, dl,
CurDAG->getEntryNode(), CGPoolOffset, CurDAG->getEntryNode(), CGPoolOffset,

17
llvm/lib/Target/CellSPU/SPUISelLowering.cpp
View File

@ -89,7 +89,7 @@ namespace {
SDValue SDValue
ExpandLibCall(RTLIB::Libcall LC, SDValue Op, SelectionDAG &DAG, ExpandLibCall(RTLIB::Libcall LC, SDValue Op, SelectionDAG &DAG,
bool isSigned, SDValue &Hi, SPUTargetLowering &TLI) { bool isSigned, SDValue &Hi, const SPUTargetLowering &TLI) {
// The input chain to this libcall is the entry node of the function. // The input chain to this libcall is the entry node of the function.
// Legalizing the call will automatically add the previous call to the // Legalizing the call will automatically add the previous call to the
// dependence. // dependence.
@ -1005,7 +1005,8 @@ SPUTargetLowering::LowerFormalArguments(SDValue Chain,
const SmallVectorImpl<ISD::InputArg> const SmallVectorImpl<ISD::InputArg>
&Ins, &Ins,
DebugLoc dl, SelectionDAG &DAG, DebugLoc dl, SelectionDAG &DAG,
SmallVectorImpl<SDValue> &InVals) { SmallVectorImpl<SDValue> &InVals)
const {
MachineFunction &MF = DAG.getMachineFunction(); MachineFunction &MF = DAG.getMachineFunction();
MachineFrameInfo *MFI = MF.getFrameInfo(); MachineFrameInfo *MFI = MF.getFrameInfo();
@ -1136,7 +1137,7 @@ SPUTargetLowering::LowerCall(SDValue Chain, SDValue Callee,
const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<ISD::OutputArg> &Outs,
const SmallVectorImpl<ISD::InputArg> &Ins, const SmallVectorImpl<ISD::InputArg> &Ins,
DebugLoc dl, SelectionDAG &DAG, DebugLoc dl, SelectionDAG &DAG,
SmallVectorImpl<SDValue> &InVals) { SmallVectorImpl<SDValue> &InVals) const {
// CellSPU target does not yet support tail call optimization. // CellSPU target does not yet support tail call optimization.
isTailCall = false; isTailCall = false;
@ -1364,7 +1365,7 @@ SDValue
SPUTargetLowering::LowerReturn(SDValue Chain, SPUTargetLowering::LowerReturn(SDValue Chain,
CallingConv::ID CallConv, bool isVarArg, CallingConv::ID CallConv, bool isVarArg,
const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<ISD::OutputArg> &Outs,
DebugLoc dl, SelectionDAG &DAG) { DebugLoc dl, SelectionDAG &DAG) const {
SmallVector<CCValAssign, 16> RVLocs; SmallVector<CCValAssign, 16> RVLocs;
CCState CCInfo(CallConv, isVarArg, getTargetMachine(), CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
@ -2354,7 +2355,7 @@ static SDValue LowerCTPOP(SDValue Op, SelectionDAG &DAG) {
All conversions to i64 are expanded to a libcall. All conversions to i64 are expanded to a libcall.
*/ */
static SDValue LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG, static SDValue LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG,
SPUTargetLowering &TLI) { const SPUTargetLowering &TLI) {
EVT OpVT = Op.getValueType(); EVT OpVT = Op.getValueType();
SDValue Op0 = Op.getOperand(0); SDValue Op0 = Op.getOperand(0);
EVT Op0VT = Op0.getValueType(); EVT Op0VT = Op0.getValueType();
@ -2380,7 +2381,7 @@ static SDValue LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG,
All conversions from i64 are expanded to a libcall. All conversions from i64 are expanded to a libcall.
*/ */
static SDValue LowerINT_TO_FP(SDValue Op, SelectionDAG &DAG, static SDValue LowerINT_TO_FP(SDValue Op, SelectionDAG &DAG,
SPUTargetLowering &TLI) { const SPUTargetLowering &TLI) {
EVT OpVT = Op.getValueType(); EVT OpVT = Op.getValueType();
SDValue Op0 = Op.getOperand(0); SDValue Op0 = Op.getOperand(0);
EVT Op0VT = Op0.getValueType(); EVT Op0VT = Op0.getValueType();
@ -2656,7 +2657,7 @@ static SDValue LowerSIGN_EXTEND(SDValue Op, SelectionDAG &DAG)
lowering of nodes. lowering of nodes.
*/ */
SDValue SDValue
SPUTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) SPUTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const
{ {
unsigned Opc = (unsigned) Op.getOpcode(); unsigned Opc = (unsigned) Op.getOpcode();
EVT VT = Op.getValueType(); EVT VT = Op.getValueType();
@ -2752,7 +2753,7 @@ SPUTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG)
void SPUTargetLowering::ReplaceNodeResults(SDNode *N, void SPUTargetLowering::ReplaceNodeResults(SDNode *N,
SmallVectorImpl<SDValue>&Results, SmallVectorImpl<SDValue>&Results,
SelectionDAG &DAG) SelectionDAG &DAG) const
{ {
#if 0 #if 0
unsigned Opc = (unsigned) N->getOpcode(); unsigned Opc = (unsigned) N->getOpcode();

10
llvm/lib/Target/CellSPU/SPUISelLowering.h
View File

@ -109,11 +109,11 @@ namespace llvm {
virtual MVT::SimpleValueType getSetCCResultType(EVT VT) const; virtual MVT::SimpleValueType getSetCCResultType(EVT VT) const;
//! Custom lowering hooks //! Custom lowering hooks
virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG); virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
//! Custom lowering hook for nodes with illegal result types. //! Custom lowering hook for nodes with illegal result types.
virtual void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results, virtual void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results,
SelectionDAG &DAG); SelectionDAG &DAG) const;
virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const; virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
@ -153,7 +153,7 @@ namespace llvm {
CallingConv::ID CallConv, bool isVarArg, CallingConv::ID CallConv, bool isVarArg,
const SmallVectorImpl<ISD::InputArg> &Ins, const SmallVectorImpl<ISD::InputArg> &Ins,
DebugLoc dl, SelectionDAG &DAG, DebugLoc dl, SelectionDAG &DAG,
SmallVectorImpl<SDValue> &InVals); SmallVectorImpl<SDValue> &InVals) const;
virtual SDValue virtual SDValue
LowerCall(SDValue Chain, SDValue Callee, LowerCall(SDValue Chain, SDValue Callee,
@ -162,13 +162,13 @@ namespace llvm {
const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<ISD::OutputArg> &Outs,
const SmallVectorImpl<ISD::InputArg> &Ins, const SmallVectorImpl<ISD::InputArg> &Ins,
DebugLoc dl, SelectionDAG &DAG, DebugLoc dl, SelectionDAG &DAG,
SmallVectorImpl<SDValue> &InVals); SmallVectorImpl<SDValue> &InVals) const;
virtual SDValue virtual SDValue
LowerReturn(SDValue Chain, LowerReturn(SDValue Chain,
CallingConv::ID CallConv, bool isVarArg, CallingConv::ID CallConv, bool isVarArg,
const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<ISD::OutputArg> &Outs,
DebugLoc dl, SelectionDAG &DAG); DebugLoc dl, SelectionDAG &DAG) const;
}; };
} }

4
llvm/lib/Target/CellSPU/SPUTargetMachine.h
View File

@ -57,8 +57,8 @@ public:
return NULL; return NULL;
} }
virtual SPUTargetLowering *getTargetLowering() const { virtual const SPUTargetLowering *getTargetLowering() const {
return const_cast<SPUTargetLowering*>(&TLInfo); return &TLInfo;
} }
virtual const SPURegisterInfo *getRegisterInfo() const { virtual const SPURegisterInfo *getRegisterInfo() const {

1
llvm/lib/Target/MBlaze/MBlazeISelDAGToDAG.cpp
View File

@ -13,7 +13,6 @@
#define DEBUG_TYPE "mblaze-isel" #define DEBUG_TYPE "mblaze-isel"
#include "MBlaze.h" #include "MBlaze.h"
#include "MBlazeISelLowering.h"
#include "MBlazeMachineFunction.h" #include "MBlazeMachineFunction.h"
#include "MBlazeRegisterInfo.h" #include "MBlazeRegisterInfo.h"
#include "MBlazeSubtarget.h" #include "MBlazeSubtarget.h"

25
llvm/lib/Target/MBlaze/MBlazeISelLowering.cpp
View File

@ -185,7 +185,8 @@ unsigned MBlazeTargetLowering::getFunctionAlignment(const Function *) const {
return 2; return 2;
} }
SDValue MBlazeTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) { SDValue MBlazeTargetLowering::LowerOperation(SDValue Op,
SelectionDAG &DAG) const {
switch (Op.getOpcode()) switch (Op.getOpcode())
{ {
case ISD::ConstantPool: return LowerConstantPool(Op, DAG); case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
@ -387,7 +388,8 @@ EmitInstrWithCustomInserter(MachineInstr *MI, MachineBasicBlock *BB,
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// //
SDValue MBlazeTargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) { SDValue MBlazeTargetLowering::LowerSELECT_CC(SDValue Op,
SelectionDAG &DAG) const {
SDValue LHS = Op.getOperand(0); SDValue LHS = Op.getOperand(0);
SDValue RHS = Op.getOperand(1); SDValue RHS = Op.getOperand(1);
SDValue TrueVal = Op.getOperand(2); SDValue TrueVal = Op.getOperand(2);
@ -409,7 +411,7 @@ SDValue MBlazeTargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) {
} }
SDValue MBlazeTargetLowering:: SDValue MBlazeTargetLowering::
LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) { LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const {
// FIXME there isn't actually debug info here // FIXME there isn't actually debug info here
DebugLoc dl = Op.getDebugLoc(); DebugLoc dl = Op.getDebugLoc();
const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal(); const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
@ -419,13 +421,13 @@ LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) {
} }
SDValue MBlazeTargetLowering:: SDValue MBlazeTargetLowering::
LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) { LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const {
llvm_unreachable("TLS not implemented for MicroBlaze."); llvm_unreachable("TLS not implemented for MicroBlaze.");
return SDValue(); // Not reached return SDValue(); // Not reached
} }
SDValue MBlazeTargetLowering:: SDValue MBlazeTargetLowering::
LowerJumpTable(SDValue Op, SelectionDAG &DAG) { LowerJumpTable(SDValue Op, SelectionDAG &DAG) const {
SDValue ResNode; SDValue ResNode;
SDValue HiPart; SDValue HiPart;
// FIXME there isn't actually debug info here // FIXME there isn't actually debug info here
@ -442,7 +444,7 @@ LowerJumpTable(SDValue Op, SelectionDAG &DAG) {
} }
SDValue MBlazeTargetLowering:: SDValue MBlazeTargetLowering::
LowerConstantPool(SDValue Op, SelectionDAG &DAG) { LowerConstantPool(SDValue Op, SelectionDAG &DAG) const {
SDValue ResNode; SDValue ResNode;
EVT PtrVT = Op.getValueType(); EVT PtrVT = Op.getValueType();
ConstantPoolSDNode *N = cast<ConstantPoolSDNode>(Op); ConstantPoolSDNode *N = cast<ConstantPoolSDNode>(Op);
@ -455,7 +457,8 @@ LowerConstantPool(SDValue Op, SelectionDAG &DAG) {
return DAG.getNode(MBlazeISD::Wrap, dl, MVT::i32, CP); return DAG.getNode(MBlazeISD::Wrap, dl, MVT::i32, CP);
} }
SDValue MBlazeTargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) { SDValue MBlazeTargetLowering::LowerVASTART(SDValue Op,
SelectionDAG &DAG) const {
MachineFunction &MF = DAG.getMachineFunction(); MachineFunction &MF = DAG.getMachineFunction();
MBlazeFunctionInfo *FuncInfo = MF.getInfo<MBlazeFunctionInfo>(); MBlazeFunctionInfo *FuncInfo = MF.getInfo<MBlazeFunctionInfo>();
@ -537,7 +540,7 @@ LowerCall(SDValue Chain, SDValue Callee, CallingConv::ID CallConv,
const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<ISD::OutputArg> &Outs,
const SmallVectorImpl<ISD::InputArg> &Ins, const SmallVectorImpl<ISD::InputArg> &Ins,
DebugLoc dl, SelectionDAG &DAG, DebugLoc dl, SelectionDAG &DAG,
SmallVectorImpl<SDValue> &InVals) { SmallVectorImpl<SDValue> &InVals) const {
// MBlaze does not yet support tail call optimization // MBlaze does not yet support tail call optimization
isTailCall = false; isTailCall = false;
@ -673,7 +676,7 @@ SDValue MBlazeTargetLowering::
LowerCallResult(SDValue Chain, SDValue InFlag, CallingConv::ID CallConv, LowerCallResult(SDValue Chain, SDValue InFlag, CallingConv::ID CallConv,
bool isVarArg, const SmallVectorImpl<ISD::InputArg> &Ins, bool isVarArg, const SmallVectorImpl<ISD::InputArg> &Ins,
DebugLoc dl, SelectionDAG &DAG, DebugLoc dl, SelectionDAG &DAG,
SmallVectorImpl<SDValue> &InVals) { SmallVectorImpl<SDValue> &InVals) const {
// Assign locations to each value returned by this call. // Assign locations to each value returned by this call.
SmallVector<CCValAssign, 16> RVLocs; SmallVector<CCValAssign, 16> RVLocs;
CCState CCInfo(CallConv, isVarArg, getTargetMachine(), CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
@ -703,7 +706,7 @@ SDValue MBlazeTargetLowering::
LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
const SmallVectorImpl<ISD::InputArg> &Ins, const SmallVectorImpl<ISD::InputArg> &Ins,
DebugLoc dl, SelectionDAG &DAG, DebugLoc dl, SelectionDAG &DAG,
SmallVectorImpl<SDValue> &InVals) { SmallVectorImpl<SDValue> &InVals) const {
MachineFunction &MF = DAG.getMachineFunction(); MachineFunction &MF = DAG.getMachineFunction();
MachineFrameInfo *MFI = MF.getFrameInfo(); MachineFrameInfo *MFI = MF.getFrameInfo();
MBlazeFunctionInfo *MBlazeFI = MF.getInfo<MBlazeFunctionInfo>(); MBlazeFunctionInfo *MBlazeFI = MF.getInfo<MBlazeFunctionInfo>();
@ -845,7 +848,7 @@ LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
SDValue MBlazeTargetLowering:: SDValue MBlazeTargetLowering::
LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<ISD::OutputArg> &Outs,
DebugLoc dl, SelectionDAG &DAG) { DebugLoc dl, SelectionDAG &DAG) const {
// CCValAssign - represent the assignment of // CCValAssign - represent the assignment of
// the return value to a location // the return value to a location
SmallVector<CCValAssign, 16> RVLocs; SmallVector<CCValAssign, 16> RVLocs;

22
llvm/lib/Target/MBlaze/MBlazeISelLowering.h
View File

@ -67,7 +67,7 @@ namespace llvm {
explicit MBlazeTargetLowering(MBlazeTargetMachine &TM); explicit MBlazeTargetLowering(MBlazeTargetMachine &TM);
/// LowerOperation - Provide custom lowering hooks for some operations. /// LowerOperation - Provide custom lowering hooks for some operations.
virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG); virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
/// getTargetNodeName - This method returns the name of a target specific /// getTargetNodeName - This method returns the name of a target specific
// DAG node. // DAG node.
@ -87,22 +87,22 @@ namespace llvm {
CallingConv::ID CallConv, bool isVarArg, CallingConv::ID CallConv, bool isVarArg,
const SmallVectorImpl<ISD::InputArg> &Ins, const SmallVectorImpl<ISD::InputArg> &Ins,
DebugLoc dl, SelectionDAG &DAG, DebugLoc dl, SelectionDAG &DAG,
SmallVectorImpl<SDValue> &InVals); SmallVectorImpl<SDValue> &InVals) const;
// Lower Operand specifics // Lower Operand specifics
SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG); SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG); SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG); SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG); SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG); SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG); SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) const;
virtual SDValue virtual SDValue
LowerFormalArguments(SDValue Chain, LowerFormalArguments(SDValue Chain,
CallingConv::ID CallConv, bool isVarArg, CallingConv::ID CallConv, bool isVarArg,
const SmallVectorImpl<ISD::InputArg> &Ins, const SmallVectorImpl<ISD::InputArg> &Ins,
DebugLoc dl, SelectionDAG &DAG, DebugLoc dl, SelectionDAG &DAG,
SmallVectorImpl<SDValue> &InVals); SmallVectorImpl<SDValue> &InVals) const;
virtual SDValue virtual SDValue
LowerCall(SDValue Chain, SDValue Callee, LowerCall(SDValue Chain, SDValue Callee,
@ -111,13 +111,13 @@ namespace llvm {
const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<ISD::OutputArg> &Outs,
const SmallVectorImpl<ISD::InputArg> &Ins, const SmallVectorImpl<ISD::InputArg> &Ins,
DebugLoc dl, SelectionDAG &DAG, DebugLoc dl, SelectionDAG &DAG,
SmallVectorImpl<SDValue> &InVals); SmallVectorImpl<SDValue> &InVals) const;
virtual SDValue virtual SDValue
LowerReturn(SDValue Chain, LowerReturn(SDValue Chain,
CallingConv::ID CallConv, bool isVarArg, CallingConv::ID CallConv, bool isVarArg,
const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<ISD::OutputArg> &Outs,
DebugLoc dl, SelectionDAG &DAG); DebugLoc dl, SelectionDAG &DAG) const;
virtual MachineBasicBlock *EmitInstrWithCustomInserter(MachineInstr *MI, virtual MachineBasicBlock *EmitInstrWithCustomInserter(MachineInstr *MI,
MachineBasicBlock *MBB, MachineBasicBlock *MBB,

4
llvm/lib/Target/MBlaze/MBlazeTargetMachine.h
View File

@ -51,8 +51,8 @@ namespace llvm {
virtual const MBlazeRegisterInfo *getRegisterInfo() const virtual const MBlazeRegisterInfo *getRegisterInfo() const
{ return &InstrInfo.getRegisterInfo(); } { return &InstrInfo.getRegisterInfo(); }
virtual MBlazeTargetLowering *getTargetLowering() const virtual const MBlazeTargetLowering *getTargetLowering() const
{ return const_cast<MBlazeTargetLowering*>(&TLInfo); } { return &TLInfo; }
const TargetIntrinsicInfo *getIntrinsicInfo() const const TargetIntrinsicInfo *getIntrinsicInfo() const
{ return &IntrinsicInfo; } { return &IntrinsicInfo; }

5
llvm/lib/Target/MSP430/MSP430ISelDAGToDAG.cpp
View File

@ -12,7 +12,6 @@
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
#include "MSP430.h" #include "MSP430.h"
#include "MSP430ISelLowering.h"
#include "MSP430TargetMachine.h" #include "MSP430TargetMachine.h"
#include "llvm/DerivedTypes.h" #include "llvm/DerivedTypes.h"
#include "llvm/Function.h" #include "llvm/Function.h"
@ -100,7 +99,7 @@ namespace {
/// ///
namespace { namespace {
class MSP430DAGToDAGISel : public SelectionDAGISel { class MSP430DAGToDAGISel : public SelectionDAGISel {
MSP430TargetLowering &Lowering; const MSP430TargetLowering &Lowering;
const MSP430Subtarget &Subtarget; const MSP430Subtarget &Subtarget;
public: public:
@ -364,7 +363,7 @@ SDNode *MSP430DAGToDAGISel::SelectIndexedBinOp(SDNode *Op,
unsigned Opc8, unsigned Opc16) { unsigned Opc8, unsigned Opc16) {
if (N1.getOpcode() == ISD::LOAD && if (N1.getOpcode() == ISD::LOAD &&
N1.hasOneUse() && N1.hasOneUse() &&
IsLegalToFold(N1, Op, Op)) { IsLegalToFold(N1, Op, Op, OptLevel)) {
LoadSDNode *LD = cast<LoadSDNode>(N1); LoadSDNode *LD = cast<LoadSDNode>(N1);
if (!isValidIndexedLoad(LD)) if (!isValidIndexedLoad(LD))
return NULL; return NULL;

42
llvm/lib/Target/MSP430/MSP430ISelLowering.cpp
View File

@ -176,7 +176,8 @@ MSP430TargetLowering::MSP430TargetLowering(MSP430TargetMachine &tm) :
} }
} }
SDValue MSP430TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) { SDValue MSP430TargetLowering::LowerOperation(SDValue Op,
SelectionDAG &DAG) const {
switch (Op.getOpcode()) { switch (Op.getOpcode()) {
case ISD::SHL: // FALLTHROUGH case ISD::SHL: // FALLTHROUGH
case ISD::SRL: case ISD::SRL:
@ -252,7 +253,8 @@ MSP430TargetLowering::LowerFormalArguments(SDValue Chain,
&Ins, &Ins,
DebugLoc dl, DebugLoc dl,
SelectionDAG &DAG, SelectionDAG &DAG,
SmallVectorImpl<SDValue> &InVals) { SmallVectorImpl<SDValue> &InVals)
const {
switch (CallConv) { switch (CallConv) {
default: default:
@ -277,7 +279,7 @@ MSP430TargetLowering::LowerCall(SDValue Chain, SDValue Callee,
const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<ISD::OutputArg> &Outs,
const SmallVectorImpl<ISD::InputArg> &Ins, const SmallVectorImpl<ISD::InputArg> &Ins,
DebugLoc dl, SelectionDAG &DAG, DebugLoc dl, SelectionDAG &DAG,
SmallVectorImpl<SDValue> &InVals) { SmallVectorImpl<SDValue> &InVals) const {
// MSP430 target does not yet support tail call optimization. // MSP430 target does not yet support tail call optimization.
isTailCall = false; isTailCall = false;
@ -306,7 +308,8 @@ MSP430TargetLowering::LowerCCCArguments(SDValue Chain,
&Ins, &Ins,
DebugLoc dl, DebugLoc dl,
SelectionDAG &DAG, SelectionDAG &DAG,
SmallVectorImpl<SDValue> &InVals) { SmallVectorImpl<SDValue> &InVals)
const {
MachineFunction &MF = DAG.getMachineFunction(); MachineFunction &MF = DAG.getMachineFunction();
MachineFrameInfo *MFI = MF.getFrameInfo(); MachineFrameInfo *MFI = MF.getFrameInfo();
MachineRegisterInfo &RegInfo = MF.getRegInfo(); MachineRegisterInfo &RegInfo = MF.getRegInfo();
@ -383,7 +386,7 @@ SDValue
MSP430TargetLowering::LowerReturn(SDValue Chain, MSP430TargetLowering::LowerReturn(SDValue Chain,
CallingConv::ID CallConv, bool isVarArg, CallingConv::ID CallConv, bool isVarArg,
const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<ISD::OutputArg> &Outs,
DebugLoc dl, SelectionDAG &DAG) { DebugLoc dl, SelectionDAG &DAG) const {
// CCValAssign - represent the assignment of the return value to a location // CCValAssign - represent the assignment of the return value to a location
SmallVector<CCValAssign, 16> RVLocs; SmallVector<CCValAssign, 16> RVLocs;
@ -445,7 +448,7 @@ MSP430TargetLowering::LowerCCCCallTo(SDValue Chain, SDValue Callee,
&Outs, &Outs,
const SmallVectorImpl<ISD::InputArg> &Ins, const SmallVectorImpl<ISD::InputArg> &Ins,
DebugLoc dl, SelectionDAG &DAG, DebugLoc dl, SelectionDAG &DAG,
SmallVectorImpl<SDValue> &InVals) { SmallVectorImpl<SDValue> &InVals) const {
// Analyze operands of the call, assigning locations to each operand. // Analyze operands of the call, assigning locations to each operand.
SmallVector<CCValAssign, 16> ArgLocs; SmallVector<CCValAssign, 16> ArgLocs;
CCState CCInfo(CallConv, isVarArg, getTargetMachine(), CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
@ -568,7 +571,7 @@ MSP430TargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
CallingConv::ID CallConv, bool isVarArg, CallingConv::ID CallConv, bool isVarArg,
const SmallVectorImpl<ISD::InputArg> &Ins, const SmallVectorImpl<ISD::InputArg> &Ins,
DebugLoc dl, SelectionDAG &DAG, DebugLoc dl, SelectionDAG &DAG,
SmallVectorImpl<SDValue> &InVals) { SmallVectorImpl<SDValue> &InVals) const {
// Assign locations to each value returned by this call. // Assign locations to each value returned by this call.
SmallVector<CCValAssign, 16> RVLocs; SmallVector<CCValAssign, 16> RVLocs;
@ -589,7 +592,7 @@ MSP430TargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
} }
SDValue MSP430TargetLowering::LowerShifts(SDValue Op, SDValue MSP430TargetLowering::LowerShifts(SDValue Op,
SelectionDAG &DAG) { SelectionDAG &DAG) const {
unsigned Opc = Op.getOpcode(); unsigned Opc = Op.getOpcode();
SDNode* N = Op.getNode(); SDNode* N = Op.getNode();
EVT VT = Op.getValueType(); EVT VT = Op.getValueType();
@ -632,7 +635,8 @@ SDValue MSP430TargetLowering::LowerShifts(SDValue Op,
return Victim; return Victim;
} }
SDValue MSP430TargetLowering::LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) { SDValue MSP430TargetLowering::LowerGlobalAddress(SDValue Op,
SelectionDAG &DAG) const {
const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal(); const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset(); int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset();
@ -643,7 +647,7 @@ SDValue MSP430TargetLowering::LowerGlobalAddress(SDValue Op, SelectionDAG &DAG)
} }
SDValue MSP430TargetLowering::LowerExternalSymbol(SDValue Op, SDValue MSP430TargetLowering::LowerExternalSymbol(SDValue Op,
SelectionDAG &DAG) { SelectionDAG &DAG) const {
DebugLoc dl = Op.getDebugLoc(); DebugLoc dl = Op.getDebugLoc();
const char *Sym = cast<ExternalSymbolSDNode>(Op)->getSymbol(); const char *Sym = cast<ExternalSymbolSDNode>(Op)->getSymbol();
SDValue Result = DAG.getTargetExternalSymbol(Sym, getPointerTy()); SDValue Result = DAG.getTargetExternalSymbol(Sym, getPointerTy());
@ -734,7 +738,7 @@ static SDValue EmitCMP(SDValue &LHS, SDValue &RHS, SDValue &TargetCC,
} }
SDValue MSP430TargetLowering::LowerBR_CC(SDValue Op, SelectionDAG &DAG) { SDValue MSP430TargetLowering::LowerBR_CC(SDValue Op, SelectionDAG &DAG) const {
SDValue Chain = Op.getOperand(0); SDValue Chain = Op.getOperand(0);
ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get(); ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
SDValue LHS = Op.getOperand(2); SDValue LHS = Op.getOperand(2);
@ -750,7 +754,7 @@ SDValue MSP430TargetLowering::LowerBR_CC(SDValue Op, SelectionDAG &DAG) {
} }
SDValue MSP430TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) { SDValue MSP430TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
SDValue LHS = Op.getOperand(0); SDValue LHS = Op.getOperand(0);
SDValue RHS = Op.getOperand(1); SDValue RHS = Op.getOperand(1);
DebugLoc dl = Op.getDebugLoc(); DebugLoc dl = Op.getDebugLoc();
@ -830,7 +834,8 @@ SDValue MSP430TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) {
} }
} }
SDValue MSP430TargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) { SDValue MSP430TargetLowering::LowerSELECT_CC(SDValue Op,
SelectionDAG &DAG) const {
SDValue LHS = Op.getOperand(0); SDValue LHS = Op.getOperand(0);
SDValue RHS = Op.getOperand(1); SDValue RHS = Op.getOperand(1);
SDValue TrueV = Op.getOperand(2); SDValue TrueV = Op.getOperand(2);
@ -852,7 +857,7 @@ SDValue MSP430TargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) {
} }
SDValue MSP430TargetLowering::LowerSIGN_EXTEND(SDValue Op, SDValue MSP430TargetLowering::LowerSIGN_EXTEND(SDValue Op,
SelectionDAG &DAG) { SelectionDAG &DAG) const {
SDValue Val = Op.getOperand(0); SDValue Val = Op.getOperand(0);
EVT VT = Op.getValueType(); EVT VT = Op.getValueType();
DebugLoc dl = Op.getDebugLoc(); DebugLoc dl = Op.getDebugLoc();
@ -864,7 +869,8 @@ SDValue MSP430TargetLowering::LowerSIGN_EXTEND(SDValue Op,
DAG.getValueType(Val.getValueType())); DAG.getValueType(Val.getValueType()));
} }
SDValue MSP430TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) { SDValue
MSP430TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) const {
MachineFunction &MF = DAG.getMachineFunction(); MachineFunction &MF = DAG.getMachineFunction();
MSP430MachineFunctionInfo *FuncInfo = MF.getInfo<MSP430MachineFunctionInfo>(); MSP430MachineFunctionInfo *FuncInfo = MF.getInfo<MSP430MachineFunctionInfo>();
int ReturnAddrIndex = FuncInfo->getRAIndex(); int ReturnAddrIndex = FuncInfo->getRAIndex();
@ -880,7 +886,8 @@ SDValue MSP430TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) {
return DAG.getFrameIndex(ReturnAddrIndex, getPointerTy()); return DAG.getFrameIndex(ReturnAddrIndex, getPointerTy());
} }
SDValue MSP430TargetLowering::LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) { SDValue MSP430TargetLowering::LowerRETURNADDR(SDValue Op,
SelectionDAG &DAG) const {
unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue(); unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
DebugLoc dl = Op.getDebugLoc(); DebugLoc dl = Op.getDebugLoc();
@ -900,7 +907,8 @@ SDValue MSP430TargetLowering::LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) {
RetAddrFI, NULL, 0, false, false, 0); RetAddrFI, NULL, 0, false, false, 0);
} }
SDValue MSP430TargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) { SDValue MSP430TargetLowering::LowerFRAMEADDR(SDValue Op,
SelectionDAG &DAG) const {
MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
MFI->setFrameAddressIsTaken(true); MFI->setFrameAddressIsTaken(true);
EVT VT = Op.getValueType(); EVT VT = Op.getValueType();

34
llvm/lib/Target/MSP430/MSP430ISelLowering.h
View File

@ -74,7 +74,7 @@ namespace llvm {
explicit MSP430TargetLowering(MSP430TargetMachine &TM); explicit MSP430TargetLowering(MSP430TargetMachine &TM);
/// LowerOperation - Provide custom lowering hooks for some operations. /// LowerOperation - Provide custom lowering hooks for some operations.
virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG); virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
/// getTargetNodeName - This method returns the name of a target specific /// getTargetNodeName - This method returns the name of a target specific
/// DAG node. /// DAG node.
@ -83,16 +83,16 @@ namespace llvm {
/// getFunctionAlignment - Return the Log2 alignment of this function. /// getFunctionAlignment - Return the Log2 alignment of this function.
virtual unsigned getFunctionAlignment(const Function *F) const; virtual unsigned getFunctionAlignment(const Function *F) const;
SDValue LowerShifts(SDValue Op, SelectionDAG &DAG); SDValue LowerShifts(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG); SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerExternalSymbol(SDValue Op, SelectionDAG &DAG); SDValue LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG); SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG); SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG); SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerSIGN_EXTEND(SDValue Op, SelectionDAG &DAG); SDValue LowerSIGN_EXTEND(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG); SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG); SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
SDValue getReturnAddressFrameIndex(SelectionDAG &DAG); SDValue getReturnAddressFrameIndex(SelectionDAG &DAG) const;
TargetLowering::ConstraintType TargetLowering::ConstraintType
getConstraintType(const std::string &Constraint) const; getConstraintType(const std::string &Constraint) const;
@ -130,7 +130,7 @@ namespace llvm {
const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<ISD::OutputArg> &Outs,
const SmallVectorImpl<ISD::InputArg> &Ins, const SmallVectorImpl<ISD::InputArg> &Ins,
DebugLoc dl, SelectionDAG &DAG, DebugLoc dl, SelectionDAG &DAG,
SmallVectorImpl<SDValue> &InVals); SmallVectorImpl<SDValue> &InVals) const;
SDValue LowerCCCArguments(SDValue Chain, SDValue LowerCCCArguments(SDValue Chain,
CallingConv::ID CallConv, CallingConv::ID CallConv,
@ -138,33 +138,33 @@ namespace llvm {
const SmallVectorImpl<ISD::InputArg> &Ins, const SmallVectorImpl<ISD::InputArg> &Ins,
DebugLoc dl, DebugLoc dl,
SelectionDAG &DAG, SelectionDAG &DAG,
SmallVectorImpl<SDValue> &InVals); SmallVectorImpl<SDValue> &InVals) const;
SDValue LowerCallResult(SDValue Chain, SDValue InFlag, SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
CallingConv::ID CallConv, bool isVarArg, CallingConv::ID CallConv, bool isVarArg,
const SmallVectorImpl<ISD::InputArg> &Ins, const SmallVectorImpl<ISD::InputArg> &Ins,
DebugLoc dl, SelectionDAG &DAG, DebugLoc dl, SelectionDAG &DAG,
SmallVectorImpl<SDValue> &InVals); SmallVectorImpl<SDValue> &InVals) const;
virtual SDValue virtual SDValue
LowerFormalArguments(SDValue Chain, LowerFormalArguments(SDValue Chain,
CallingConv::ID CallConv, bool isVarArg, CallingConv::ID CallConv, bool isVarArg,
const SmallVectorImpl<ISD::InputArg> &Ins, const SmallVectorImpl<ISD::InputArg> &Ins,
DebugLoc dl, SelectionDAG &DAG, DebugLoc dl, SelectionDAG &DAG,
SmallVectorImpl<SDValue> &InVals); SmallVectorImpl<SDValue> &InVals) const;
virtual SDValue virtual SDValue
LowerCall(SDValue Chain, SDValue Callee, LowerCall(SDValue Chain, SDValue Callee,
CallingConv::ID CallConv, bool isVarArg, bool &isTailCall, CallingConv::ID CallConv, bool isVarArg, bool &isTailCall,
const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<ISD::OutputArg> &Outs,
const SmallVectorImpl<ISD::InputArg> &Ins, const SmallVectorImpl<ISD::InputArg> &Ins,
DebugLoc dl, SelectionDAG &DAG, DebugLoc dl, SelectionDAG &DAG,
SmallVectorImpl<SDValue> &InVals); SmallVectorImpl<SDValue> &InVals) const;
virtual SDValue virtual SDValue
LowerReturn(SDValue Chain, LowerReturn(SDValue Chain,
CallingConv::ID CallConv, bool isVarArg, CallingConv::ID CallConv, bool isVarArg,
const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<ISD::OutputArg> &Outs,
DebugLoc dl, SelectionDAG &DAG); DebugLoc dl, SelectionDAG &DAG) const;
virtual bool getPostIndexedAddressParts(SDNode *N, SDNode *Op, virtual bool getPostIndexedAddressParts(SDNode *N, SDNode *Op,
SDValue &Base, SDValue &Base,

4
llvm/lib/Target/MSP430/MSP430TargetMachine.h
View File

@ -50,8 +50,8 @@ public:
return &InstrInfo.getRegisterInfo(); return &InstrInfo.getRegisterInfo();
} }
virtual MSP430TargetLowering *getTargetLowering() const { virtual const MSP430TargetLowering *getTargetLowering() const {
return const_cast<MSP430TargetLowering*>(&TLInfo); return &TLInfo;
} }
virtual bool addInstSelector(PassManagerBase &PM, CodeGenOpt::Level OptLevel); virtual bool addInstSelector(PassManagerBase &PM, CodeGenOpt::Level OptLevel);

1
llvm/lib/Target/Mips/MipsISelDAGToDAG.cpp
View File

@ -13,7 +13,6 @@
#define DEBUG_TYPE "mips-isel" #define DEBUG_TYPE "mips-isel"
#include "Mips.h" #include "Mips.h"
#include "MipsISelLowering.h"
#include "MipsMachineFunction.h" #include "MipsMachineFunction.h"
#include "MipsRegisterInfo.h" #include "MipsRegisterInfo.h"
#include "MipsSubtarget.h" #include "MipsSubtarget.h"

34
llvm/lib/Target/Mips/MipsISelLowering.cpp
View File

@ -166,7 +166,7 @@ unsigned MipsTargetLowering::getFunctionAlignment(const Function *) const {
} }
SDValue MipsTargetLowering:: SDValue MipsTargetLowering::
LowerOperation(SDValue Op, SelectionDAG &DAG) LowerOperation(SDValue Op, SelectionDAG &DAG) const
{ {
switch (Op.getOpcode()) switch (Op.getOpcode())
{ {
@ -341,7 +341,7 @@ MipsTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
SDValue MipsTargetLowering:: SDValue MipsTargetLowering::
LowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG) LowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG) const
{ {
if (!Subtarget->isMips1()) if (!Subtarget->isMips1())
return Op; return Op;
@ -374,7 +374,7 @@ LowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG)
} }
SDValue MipsTargetLowering:: SDValue MipsTargetLowering::
LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const
{ {
SDValue Chain = Op.getOperand(0); SDValue Chain = Op.getOperand(0);
SDValue Size = Op.getOperand(1); SDValue Size = Op.getOperand(1);
@ -398,7 +398,7 @@ LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG)
} }
SDValue MipsTargetLowering:: SDValue MipsTargetLowering::
LowerANDOR(SDValue Op, SelectionDAG &DAG) LowerANDOR(SDValue Op, SelectionDAG &DAG) const
{ {
SDValue LHS = Op.getOperand(0); SDValue LHS = Op.getOperand(0);
SDValue RHS = Op.getOperand(1); SDValue RHS = Op.getOperand(1);
@ -419,7 +419,7 @@ LowerANDOR(SDValue Op, SelectionDAG &DAG)
} }
SDValue MipsTargetLowering:: SDValue MipsTargetLowering::
LowerBRCOND(SDValue Op, SelectionDAG &DAG) LowerBRCOND(SDValue Op, SelectionDAG &DAG) const
{ {
// The first operand is the chain, the second is the condition, the third is // The first operand is the chain, the second is the condition, the third is
// the block to branch to if the condition is true. // the block to branch to if the condition is true.
@ -441,7 +441,7 @@ LowerBRCOND(SDValue Op, SelectionDAG &DAG)
} }
SDValue MipsTargetLowering:: SDValue MipsTargetLowering::
LowerSETCC(SDValue Op, SelectionDAG &DAG) LowerSETCC(SDValue Op, SelectionDAG &DAG) const
{ {
// The operands to this are the left and right operands to compare (ops #0, // The operands to this are the left and right operands to compare (ops #0,
// and #1) and the condition code to compare them with (op #2) as a // and #1) and the condition code to compare them with (op #2) as a
@ -457,7 +457,7 @@ LowerSETCC(SDValue Op, SelectionDAG &DAG)
} }
SDValue MipsTargetLowering:: SDValue MipsTargetLowering::
LowerSELECT(SDValue Op, SelectionDAG &DAG) LowerSELECT(SDValue Op, SelectionDAG &DAG) const
{ {
SDValue Cond = Op.getOperand(0); SDValue Cond = Op.getOperand(0);
SDValue True = Op.getOperand(1); SDValue True = Op.getOperand(1);
@ -481,7 +481,8 @@ LowerSELECT(SDValue Op, SelectionDAG &DAG)
Cond, True, False, CCNode); Cond, True, False, CCNode);
} }
SDValue MipsTargetLowering::LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) { SDValue MipsTargetLowering::LowerGlobalAddress(SDValue Op,
SelectionDAG &DAG) const {
// FIXME there isn't actually debug info here // FIXME there isn't actually debug info here
DebugLoc dl = Op.getDebugLoc(); DebugLoc dl = Op.getDebugLoc();
const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal(); const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
@ -525,14 +526,14 @@ SDValue MipsTargetLowering::LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) {
} }
SDValue MipsTargetLowering:: SDValue MipsTargetLowering::
LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const
{ {
llvm_unreachable("TLS not implemented for MIPS."); llvm_unreachable("TLS not implemented for MIPS.");
return SDValue(); // Not reached return SDValue(); // Not reached
} }
SDValue MipsTargetLowering:: SDValue MipsTargetLowering::
LowerJumpTable(SDValue Op, SelectionDAG &DAG) LowerJumpTable(SDValue Op, SelectionDAG &DAG) const
{ {
SDValue ResNode; SDValue ResNode;
SDValue HiPart; SDValue HiPart;
@ -560,7 +561,7 @@ LowerJumpTable(SDValue Op, SelectionDAG &DAG)
} }
SDValue MipsTargetLowering:: SDValue MipsTargetLowering::
LowerConstantPool(SDValue Op, SelectionDAG &DAG) LowerConstantPool(SDValue Op, SelectionDAG &DAG) const
{ {
SDValue ResNode; SDValue ResNode;
ConstantPoolSDNode *N = cast<ConstantPoolSDNode>(Op); ConstantPoolSDNode *N = cast<ConstantPoolSDNode>(Op);
@ -596,7 +597,7 @@ LowerConstantPool(SDValue Op, SelectionDAG &DAG)
return ResNode; return ResNode;
} }
SDValue MipsTargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) { SDValue MipsTargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const {
MachineFunction &MF = DAG.getMachineFunction(); MachineFunction &MF = DAG.getMachineFunction();
MipsFunctionInfo *FuncInfo = MF.getInfo<MipsFunctionInfo>(); MipsFunctionInfo *FuncInfo = MF.getInfo<MipsFunctionInfo>();
@ -773,7 +774,7 @@ MipsTargetLowering::LowerCall(SDValue Chain, SDValue Callee,
const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<ISD::OutputArg> &Outs,
const SmallVectorImpl<ISD::InputArg> &Ins, const SmallVectorImpl<ISD::InputArg> &Ins,
DebugLoc dl, SelectionDAG &DAG, DebugLoc dl, SelectionDAG &DAG,
SmallVectorImpl<SDValue> &InVals) { SmallVectorImpl<SDValue> &InVals) const {
// MIPs target does not yet support tail call optimization. // MIPs target does not yet support tail call optimization.
isTailCall = false; isTailCall = false;
@ -967,7 +968,7 @@ MipsTargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
CallingConv::ID CallConv, bool isVarArg, CallingConv::ID CallConv, bool isVarArg,
const SmallVectorImpl<ISD::InputArg> &Ins, const SmallVectorImpl<ISD::InputArg> &Ins,
DebugLoc dl, SelectionDAG &DAG, DebugLoc dl, SelectionDAG &DAG,
SmallVectorImpl<SDValue> &InVals) { SmallVectorImpl<SDValue> &InVals) const {
// Assign locations to each value returned by this call. // Assign locations to each value returned by this call.
SmallVector<CCValAssign, 16> RVLocs; SmallVector<CCValAssign, 16> RVLocs;
@ -999,7 +1000,8 @@ MipsTargetLowering::LowerFormalArguments(SDValue Chain,
const SmallVectorImpl<ISD::InputArg> const SmallVectorImpl<ISD::InputArg>
&Ins, &Ins,
DebugLoc dl, SelectionDAG &DAG, DebugLoc dl, SelectionDAG &DAG,
SmallVectorImpl<SDValue> &InVals) { SmallVectorImpl<SDValue> &InVals)
const {
MachineFunction &MF = DAG.getMachineFunction(); MachineFunction &MF = DAG.getMachineFunction();
MachineFrameInfo *MFI = MF.getFrameInfo(); MachineFrameInfo *MFI = MF.getFrameInfo();
@ -1171,7 +1173,7 @@ SDValue
MipsTargetLowering::LowerReturn(SDValue Chain, MipsTargetLowering::LowerReturn(SDValue Chain,
CallingConv::ID CallConv, bool isVarArg, CallingConv::ID CallConv, bool isVarArg,
const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<ISD::OutputArg> &Outs,
DebugLoc dl, SelectionDAG &DAG) { DebugLoc dl, SelectionDAG &DAG) const {
// CCValAssign - represent the assignment of // CCValAssign - represent the assignment of
// the return value to a location // the return value to a location

32
llvm/lib/Target/Mips/MipsISelLowering.h
View File

@ -72,7 +72,7 @@ namespace llvm {
explicit MipsTargetLowering(MipsTargetMachine &TM); explicit MipsTargetLowering(MipsTargetMachine &TM);
/// LowerOperation - Provide custom lowering hooks for some operations. /// LowerOperation - Provide custom lowering hooks for some operations.
virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG); virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
/// getTargetNodeName - This method returns the name of a target specific /// getTargetNodeName - This method returns the name of a target specific
// DAG node. // DAG node.
@ -93,27 +93,27 @@ namespace llvm {
CallingConv::ID CallConv, bool isVarArg, CallingConv::ID CallConv, bool isVarArg,
const SmallVectorImpl<ISD::InputArg> &Ins, const SmallVectorImpl<ISD::InputArg> &Ins,
DebugLoc dl, SelectionDAG &DAG, DebugLoc dl, SelectionDAG &DAG,
SmallVectorImpl<SDValue> &InVals); SmallVectorImpl<SDValue> &InVals) const;
// Lower Operand specifics // Lower Operand specifics
SDValue LowerANDOR(SDValue Op, SelectionDAG &DAG); SDValue LowerANDOR(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerBRCOND(SDValue Op, SelectionDAG &DAG); SDValue LowerBRCOND(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG); SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG); SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG); SDValue LowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG); SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG); SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG); SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerSELECT(SDValue Op, SelectionDAG &DAG); SDValue LowerSELECT(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG); SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG); SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) const;
virtual SDValue virtual SDValue
LowerFormalArguments(SDValue Chain, LowerFormalArguments(SDValue Chain,
CallingConv::ID CallConv, bool isVarArg, CallingConv::ID CallConv, bool isVarArg,
const SmallVectorImpl<ISD::InputArg> &Ins, const SmallVectorImpl<ISD::InputArg> &Ins,
DebugLoc dl, SelectionDAG &DAG, DebugLoc dl, SelectionDAG &DAG,
SmallVectorImpl<SDValue> &InVals); SmallVectorImpl<SDValue> &InVals) const;
virtual SDValue virtual SDValue
LowerCall(SDValue Chain, SDValue Callee, LowerCall(SDValue Chain, SDValue Callee,
@ -122,13 +122,13 @@ namespace llvm {
const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<ISD::OutputArg> &Outs,
const SmallVectorImpl<ISD::InputArg> &Ins, const SmallVectorImpl<ISD::InputArg> &Ins,
DebugLoc dl, SelectionDAG &DAG, DebugLoc dl, SelectionDAG &DAG,
SmallVectorImpl<SDValue> &InVals); SmallVectorImpl<SDValue> &InVals) const;
virtual SDValue virtual SDValue
LowerReturn(SDValue Chain, LowerReturn(SDValue Chain,
CallingConv::ID CallConv, bool isVarArg, CallingConv::ID CallConv, bool isVarArg,
const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<ISD::OutputArg> &Outs,
DebugLoc dl, SelectionDAG &DAG); DebugLoc dl, SelectionDAG &DAG) const;
virtual MachineBasicBlock *EmitInstrWithCustomInserter(MachineInstr *MI, virtual MachineBasicBlock *EmitInstrWithCustomInserter(MachineInstr *MI,
MachineBasicBlock *MBB, MachineBasicBlock *MBB,

4
llvm/lib/Target/Mips/MipsTargetMachine.h
View File

@ -47,8 +47,8 @@ namespace llvm {
return &InstrInfo.getRegisterInfo(); return &InstrInfo.getRegisterInfo();
} }
virtual MipsTargetLowering *getTargetLowering() const { virtual const MipsTargetLowering *getTargetLowering() const {
return const_cast<MipsTargetLowering*>(&TLInfo); return &TLInfo;
} }
// Pass Pipeline Configuration // Pass Pipeline Configuration

3
llvm/lib/Target/PIC16/AsmPrinter/PIC16AsmPrinter.cpp
View File

@ -37,9 +37,8 @@ using namespace llvm;
PIC16AsmPrinter::PIC16AsmPrinter(TargetMachine &TM, MCStreamer &Streamer) PIC16AsmPrinter::PIC16AsmPrinter(TargetMachine &TM, MCStreamer &Streamer)
: AsmPrinter(TM, Streamer), DbgInfo(Streamer, TM.getMCAsmInfo()) { : AsmPrinter(TM, Streamer), DbgInfo(Streamer, TM.getMCAsmInfo()) {
PTLI = static_cast<PIC16TargetLowering*>(TM.getTargetLowering());
PMAI = static_cast<const PIC16MCAsmInfo*>(TM.getMCAsmInfo()); PMAI = static_cast<const PIC16MCAsmInfo*>(TM.getMCAsmInfo());
PTOF = (PIC16TargetObjectFile *)&PTLI->getObjFileLowering(); PTOF = &getObjFileLowering();
} }
void PIC16AsmPrinter::EmitInstruction(const MachineInstr *MI) { void PIC16AsmPrinter::EmitInstruction(const MachineInstr *MI) {

1
llvm/lib/Target/PIC16/AsmPrinter/PIC16AsmPrinter.h
View File

@ -77,7 +77,6 @@ namespace llvm {
private: private:
PIC16TargetObjectFile *PTOF; PIC16TargetObjectFile *PTOF;
PIC16TargetLowering *PTLI;
PIC16DbgInfo DbgInfo; PIC16DbgInfo DbgInfo;
const PIC16MCAsmInfo *PMAI; const PIC16MCAsmInfo *PMAI;
std::set<std::string> LibcallDecls; // Sorted & uniqued set of extern decls. std::set<std::string> LibcallDecls; // Sorted & uniqued set of extern decls.

11
llvm/lib/Target/PIC16/PIC16ISelDAGToDAG.h
View File

@ -14,9 +14,9 @@
#define DEBUG_TYPE "pic16-isel" #define DEBUG_TYPE "pic16-isel"
#include "PIC16.h" #include "PIC16.h"
#include "PIC16ISelLowering.h"
#include "PIC16RegisterInfo.h" #include "PIC16RegisterInfo.h"
#include "PIC16TargetMachine.h" #include "PIC16TargetMachine.h"
#include "PIC16MachineFunctionInfo.h"
#include "llvm/CodeGen/SelectionDAGISel.h" #include "llvm/CodeGen/SelectionDAGISel.h"
#include "llvm/Support/Compiler.h" #include "llvm/Support/Compiler.h"
#include "llvm/Support/raw_ostream.h" #include "llvm/Support/raw_ostream.h"
@ -29,19 +29,16 @@ namespace {
class VISIBILITY_HIDDEN PIC16DAGToDAGISel : public SelectionDAGISel { class VISIBILITY_HIDDEN PIC16DAGToDAGISel : public SelectionDAGISel {
/// TM - Keep a reference to PIC16TargetMachine. /// TM - Keep a reference to PIC16TargetMachine.
PIC16TargetMachine &TM; const PIC16TargetMachine &TM;
/// PIC16Lowering - This object fully describes how to lower LLVM code to an /// PIC16Lowering - This object fully describes how to lower LLVM code to an
/// PIC16-specific SelectionDAG. /// PIC16-specific SelectionDAG.
PIC16TargetLowering &PIC16Lowering; const PIC16TargetLowering &PIC16Lowering;
public: public:
explicit PIC16DAGToDAGISel(PIC16TargetMachine &tm) : explicit PIC16DAGToDAGISel(PIC16TargetMachine &tm) :
SelectionDAGISel(tm), SelectionDAGISel(tm),
TM(tm), PIC16Lowering(*TM.getTargetLowering()) { TM(tm), PIC16Lowering(*TM.getTargetLowering()) {}
// Keep PIC16 specific DAGISel to use during the lowering
PIC16Lowering.ISel = this;
}
// Pass Name // Pass Name
virtual const char *getPassName() const { virtual const char *getPassName() const {

91
llvm/lib/Target/PIC16/PIC16ISelLowering.cpp
View File

@ -25,6 +25,7 @@
#include "llvm/CodeGen/MachineFunction.h" #include "llvm/CodeGen/MachineFunction.h"
#include "llvm/CodeGen/MachineInstrBuilder.h" #include "llvm/CodeGen/MachineInstrBuilder.h"
#include "llvm/CodeGen/MachineRegisterInfo.h" #include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/SelectionDAGISel.h"
#include "llvm/Support/ErrorHandling.h" #include "llvm/Support/ErrorHandling.h"
@ -323,7 +324,7 @@ static SDValue getOutFlag(SDValue &Op) {
} }
// Get the TmpOffset for FrameIndex // Get the TmpOffset for FrameIndex
unsigned PIC16TargetLowering::GetTmpOffsetForFI(unsigned FI, unsigned size, unsigned PIC16TargetLowering::GetTmpOffsetForFI(unsigned FI, unsigned size,
MachineFunction &MF) { MachineFunction &MF) const {
PIC16MachineFunctionInfo *FuncInfo = MF.getInfo<PIC16MachineFunctionInfo>(); PIC16MachineFunctionInfo *FuncInfo = MF.getInfo<PIC16MachineFunctionInfo>();
std::map<unsigned, unsigned> &FiTmpOffsetMap = FuncInfo->getFiTmpOffsetMap(); std::map<unsigned, unsigned> &FiTmpOffsetMap = FuncInfo->getFiTmpOffsetMap();
@ -338,7 +339,7 @@ unsigned PIC16TargetLowering::GetTmpOffsetForFI(unsigned FI, unsigned size,
return FiTmpOffsetMap[FI]; return FiTmpOffsetMap[FI];
} }
void PIC16TargetLowering::ResetTmpOffsetMap(SelectionDAG &DAG) { void PIC16TargetLowering::ResetTmpOffsetMap(SelectionDAG &DAG) const {
MachineFunction &MF = DAG.getMachineFunction(); MachineFunction &MF = DAG.getMachineFunction();
PIC16MachineFunctionInfo *FuncInfo = MF.getInfo<PIC16MachineFunctionInfo>(); PIC16MachineFunctionInfo *FuncInfo = MF.getInfo<PIC16MachineFunctionInfo>();
FuncInfo->getFiTmpOffsetMap().clear(); FuncInfo->getFiTmpOffsetMap().clear();
@ -402,7 +403,7 @@ PIC16TargetLowering::setPIC16LibcallName(PIC16ISD::PIC16Libcall Call,
} }
const char * const char *
PIC16TargetLowering::getPIC16LibcallName(PIC16ISD::PIC16Libcall Call) { PIC16TargetLowering::getPIC16LibcallName(PIC16ISD::PIC16Libcall Call) const {
return PIC16LibcallNames[Call]; return PIC16LibcallNames[Call];
} }
@ -410,7 +411,7 @@ SDValue
PIC16TargetLowering::MakePIC16Libcall(PIC16ISD::PIC16Libcall Call, PIC16TargetLowering::MakePIC16Libcall(PIC16ISD::PIC16Libcall Call,
EVT RetVT, const SDValue *Ops, EVT RetVT, const SDValue *Ops,
unsigned NumOps, bool isSigned, unsigned NumOps, bool isSigned,
SelectionDAG &DAG, DebugLoc dl) { SelectionDAG &DAG, DebugLoc dl) const {
TargetLowering::ArgListTy Args; TargetLowering::ArgListTy Args;
Args.reserve(NumOps); Args.reserve(NumOps);
@ -468,7 +469,7 @@ const char *PIC16TargetLowering::getTargetNodeName(unsigned Opcode) const {
void PIC16TargetLowering::ReplaceNodeResults(SDNode *N, void PIC16TargetLowering::ReplaceNodeResults(SDNode *N,
SmallVectorImpl<SDValue>&Results, SmallVectorImpl<SDValue>&Results,
SelectionDAG &DAG) { SelectionDAG &DAG) const {
switch (N->getOpcode()) { switch (N->getOpcode()) {
case ISD::GlobalAddress: case ISD::GlobalAddress:
@ -495,7 +496,8 @@ void PIC16TargetLowering::ReplaceNodeResults(SDNode *N,
} }
} }
SDValue PIC16TargetLowering::ExpandFrameIndex(SDNode *N, SelectionDAG &DAG) { SDValue PIC16TargetLowering::ExpandFrameIndex(SDNode *N,
SelectionDAG &DAG) const {
// Currently handling FrameIndex of size MVT::i16 only // Currently handling FrameIndex of size MVT::i16 only
// One example of this scenario is when return value is written on // One example of this scenario is when return value is written on
@ -530,7 +532,7 @@ SDValue PIC16TargetLowering::ExpandFrameIndex(SDNode *N, SelectionDAG &DAG) {
} }
SDValue PIC16TargetLowering::ExpandStore(SDNode *N, SelectionDAG &DAG) { SDValue PIC16TargetLowering::ExpandStore(SDNode *N, SelectionDAG &DAG) const {
StoreSDNode *St = cast<StoreSDNode>(N); StoreSDNode *St = cast<StoreSDNode>(N);
SDValue Chain = St->getChain(); SDValue Chain = St->getChain();
SDValue Src = St->getValue(); SDValue Src = St->getValue();
@ -648,8 +650,9 @@ SDValue PIC16TargetLowering::ExpandStore(SDNode *N, SelectionDAG &DAG) {
} }
} }
SDValue PIC16TargetLowering::ExpandExternalSymbol(SDNode *N, SelectionDAG &DAG) SDValue PIC16TargetLowering::ExpandExternalSymbol(SDNode *N,
{ SelectionDAG &DAG)
const {
ExternalSymbolSDNode *ES = dyn_cast<ExternalSymbolSDNode>(SDValue(N, 0)); ExternalSymbolSDNode *ES = dyn_cast<ExternalSymbolSDNode>(SDValue(N, 0));
// FIXME there isn't really debug info here // FIXME there isn't really debug info here
DebugLoc dl = ES->getDebugLoc(); DebugLoc dl = ES->getDebugLoc();
@ -663,7 +666,8 @@ SDValue PIC16TargetLowering::ExpandExternalSymbol(SDNode *N, SelectionDAG &DAG)
} }
// ExpandGlobalAddress - // ExpandGlobalAddress -
SDValue PIC16TargetLowering::ExpandGlobalAddress(SDNode *N, SelectionDAG &DAG) { SDValue PIC16TargetLowering::ExpandGlobalAddress(SDNode *N,
SelectionDAG &DAG) const {
GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(SDValue(N, 0)); GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(SDValue(N, 0));
// FIXME there isn't really debug info here // FIXME there isn't really debug info here
DebugLoc dl = G->getDebugLoc(); DebugLoc dl = G->getDebugLoc();
@ -678,7 +682,7 @@ SDValue PIC16TargetLowering::ExpandGlobalAddress(SDNode *N, SelectionDAG &DAG) {
return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i16, Lo, Hi); return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i16, Lo, Hi);
} }
bool PIC16TargetLowering::isDirectAddress(const SDValue &Op) { bool PIC16TargetLowering::isDirectAddress(const SDValue &Op) const {
assert (Op.getNode() != NULL && "Can't operate on NULL SDNode!!"); assert (Op.getNode() != NULL && "Can't operate on NULL SDNode!!");
if (Op.getOpcode() == ISD::BUILD_PAIR) { if (Op.getOpcode() == ISD::BUILD_PAIR) {
@ -689,7 +693,7 @@ bool PIC16TargetLowering::isDirectAddress(const SDValue &Op) {
} }
// Return true if DirectAddress is in ROM_SPACE // Return true if DirectAddress is in ROM_SPACE
bool PIC16TargetLowering::isRomAddress(const SDValue &Op) { bool PIC16TargetLowering::isRomAddress(const SDValue &Op) const {
// RomAddress is a GlobalAddress in ROM_SPACE_ // RomAddress is a GlobalAddress in ROM_SPACE_
// If the Op is not a GlobalAddress return NULL without checking // If the Op is not a GlobalAddress return NULL without checking
@ -715,7 +719,7 @@ bool PIC16TargetLowering::isRomAddress(const SDValue &Op) {
// parts of Op in Lo and Hi. // parts of Op in Lo and Hi.
void PIC16TargetLowering::GetExpandedParts(SDValue Op, SelectionDAG &DAG, void PIC16TargetLowering::GetExpandedParts(SDValue Op, SelectionDAG &DAG,
SDValue &Lo, SDValue &Hi) { SDValue &Lo, SDValue &Hi) const {
SDNode *N = Op.getNode(); SDNode *N = Op.getNode();
DebugLoc dl = N->getDebugLoc(); DebugLoc dl = N->getDebugLoc();
EVT NewVT = getTypeToTransformTo(*DAG.getContext(), N->getValueType(0)); EVT NewVT = getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
@ -732,7 +736,7 @@ void PIC16TargetLowering::GetExpandedParts(SDValue Op, SelectionDAG &DAG,
// Legalize FrameIndex into ExternalSymbol and offset. // Legalize FrameIndex into ExternalSymbol and offset.
void void
PIC16TargetLowering::LegalizeFrameIndex(SDValue Op, SelectionDAG &DAG, PIC16TargetLowering::LegalizeFrameIndex(SDValue Op, SelectionDAG &DAG,
SDValue &ES, int &Offset) { SDValue &ES, int &Offset) const {
MachineFunction &MF = DAG.getMachineFunction(); MachineFunction &MF = DAG.getMachineFunction();
const Function *Func = MF.getFunction(); const Function *Func = MF.getFunction();
@ -780,7 +784,7 @@ PIC16TargetLowering::LegalizeFrameIndex(SDValue Op, SelectionDAG &DAG,
void PIC16TargetLowering::LegalizeAddress(SDValue Ptr, SelectionDAG &DAG, void PIC16TargetLowering::LegalizeAddress(SDValue Ptr, SelectionDAG &DAG,
SDValue &Lo, SDValue &Hi, SDValue &Lo, SDValue &Hi,
unsigned &Offset, DebugLoc dl) { unsigned &Offset, DebugLoc dl) const {
// Offset, by default, should be 0 // Offset, by default, should be 0
Offset = 0; Offset = 0;
@ -859,7 +863,7 @@ void PIC16TargetLowering::LegalizeAddress(SDValue Ptr, SelectionDAG &DAG,
return; return;
} }
SDValue PIC16TargetLowering::ExpandLoad(SDNode *N, SelectionDAG &DAG) { SDValue PIC16TargetLowering::ExpandLoad(SDNode *N, SelectionDAG &DAG) const {
LoadSDNode *LD = dyn_cast<LoadSDNode>(SDValue(N, 0)); LoadSDNode *LD = dyn_cast<LoadSDNode>(SDValue(N, 0));
SDValue Chain = LD->getChain(); SDValue Chain = LD->getChain();
SDValue Ptr = LD->getBasePtr(); SDValue Ptr = LD->getBasePtr();
@ -974,7 +978,7 @@ SDValue PIC16TargetLowering::ExpandLoad(SDNode *N, SelectionDAG &DAG) {
return DAG.getNode(ISD::MERGE_VALUES, dl, Tys, BP, Chain); return DAG.getNode(ISD::MERGE_VALUES, dl, Tys, BP, Chain);
} }
SDValue PIC16TargetLowering::LowerShift(SDValue Op, SelectionDAG &DAG) { SDValue PIC16TargetLowering::LowerShift(SDValue Op, SelectionDAG &DAG) const {
// We should have handled larger operands in type legalizer itself. // We should have handled larger operands in type legalizer itself.
assert (Op.getValueType() == MVT::i8 && "illegal shift to lower"); assert (Op.getValueType() == MVT::i8 && "illegal shift to lower");
@ -1004,7 +1008,7 @@ SDValue PIC16TargetLowering::LowerShift(SDValue Op, SelectionDAG &DAG) {
return Call; return Call;
} }
SDValue PIC16TargetLowering::LowerMUL(SDValue Op, SelectionDAG &DAG) { SDValue PIC16TargetLowering::LowerMUL(SDValue Op, SelectionDAG &DAG) const {
// We should have handled larger operands in type legalizer itself. // We should have handled larger operands in type legalizer itself.
assert (Op.getValueType() == MVT::i8 && "illegal multiply to lower"); assert (Op.getValueType() == MVT::i8 && "illegal multiply to lower");
@ -1020,7 +1024,7 @@ SDValue PIC16TargetLowering::LowerMUL(SDValue Op, SelectionDAG &DAG) {
void void
PIC16TargetLowering::LowerOperationWrapper(SDNode *N, PIC16TargetLowering::LowerOperationWrapper(SDNode *N,
SmallVectorImpl<SDValue>&Results, SmallVectorImpl<SDValue>&Results,
SelectionDAG &DAG) { SelectionDAG &DAG) const {
SDValue Op = SDValue(N, 0); SDValue Op = SDValue(N, 0);
SDValue Res; SDValue Res;
unsigned i; unsigned i;
@ -1044,7 +1048,8 @@ PIC16TargetLowering::LowerOperationWrapper(SDNode *N,
} }
} }
SDValue PIC16TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) { SDValue PIC16TargetLowering::LowerOperation(SDValue Op,
SelectionDAG &DAG) const {
switch (Op.getOpcode()) { switch (Op.getOpcode()) {
case ISD::ADD: case ISD::ADD:
case ISD::ADDC: case ISD::ADDC:
@ -1078,7 +1083,7 @@ SDValue PIC16TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) {
SDValue PIC16TargetLowering::ConvertToMemOperand(SDValue Op, SDValue PIC16TargetLowering::ConvertToMemOperand(SDValue Op,
SelectionDAG &DAG, SelectionDAG &DAG,
DebugLoc dl) { DebugLoc dl) const {
assert (Op.getValueType() == MVT::i8 assert (Op.getValueType() == MVT::i8
&& "illegal value type to store on stack."); && "illegal value type to store on stack.");
@ -1116,7 +1121,7 @@ LowerIndirectCallArguments(SDValue Chain, SDValue InFlag,
SDValue DataAddr_Lo, SDValue DataAddr_Hi, SDValue DataAddr_Lo, SDValue DataAddr_Hi,
const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<ISD::OutputArg> &Outs,
const SmallVectorImpl<ISD::InputArg> &Ins, const SmallVectorImpl<ISD::InputArg> &Ins,
DebugLoc dl, SelectionDAG &DAG) { DebugLoc dl, SelectionDAG &DAG) const {
unsigned NumOps = Outs.size(); unsigned NumOps = Outs.size();
// If call has no arguments then do nothing and return. // If call has no arguments then do nothing and return.
@ -1153,7 +1158,7 @@ LowerIndirectCallArguments(SDValue Chain, SDValue InFlag,
SDValue PIC16TargetLowering:: SDValue PIC16TargetLowering::
LowerDirectCallArguments(SDValue ArgLabel, SDValue Chain, SDValue InFlag, LowerDirectCallArguments(SDValue ArgLabel, SDValue Chain, SDValue InFlag,
const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<ISD::OutputArg> &Outs,
DebugLoc dl, SelectionDAG &DAG) { DebugLoc dl, SelectionDAG &DAG) const {
unsigned NumOps = Outs.size(); unsigned NumOps = Outs.size();
std::string Name; std::string Name;
SDValue Arg, StoreAt; SDValue Arg, StoreAt;
@ -1210,7 +1215,7 @@ LowerIndirectCallReturn(SDValue Chain, SDValue InFlag,
SDValue DataAddr_Lo, SDValue DataAddr_Hi, SDValue DataAddr_Lo, SDValue DataAddr_Hi,
const SmallVectorImpl<ISD::InputArg> &Ins, const SmallVectorImpl<ISD::InputArg> &Ins,
DebugLoc dl, SelectionDAG &DAG, DebugLoc dl, SelectionDAG &DAG,
SmallVectorImpl<SDValue> &InVals) { SmallVectorImpl<SDValue> &InVals) const {
unsigned RetVals = Ins.size(); unsigned RetVals = Ins.size();
// If call does not have anything to return // If call does not have anything to return
@ -1237,7 +1242,7 @@ SDValue PIC16TargetLowering::
LowerDirectCallReturn(SDValue RetLabel, SDValue Chain, SDValue InFlag, LowerDirectCallReturn(SDValue RetLabel, SDValue Chain, SDValue InFlag,
const SmallVectorImpl<ISD::InputArg> &Ins, const SmallVectorImpl<ISD::InputArg> &Ins,
DebugLoc dl, SelectionDAG &DAG, DebugLoc dl, SelectionDAG &DAG,
SmallVectorImpl<SDValue> &InVals) { SmallVectorImpl<SDValue> &InVals) const {
// Currently handling primitive types only. They will come in // Currently handling primitive types only. They will come in
// i8 parts // i8 parts
@ -1277,7 +1282,7 @@ SDValue
PIC16TargetLowering::LowerReturn(SDValue Chain, PIC16TargetLowering::LowerReturn(SDValue Chain,
CallingConv::ID CallConv, bool isVarArg, CallingConv::ID CallConv, bool isVarArg,
const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<ISD::OutputArg> &Outs,
DebugLoc dl, SelectionDAG &DAG) { DebugLoc dl, SelectionDAG &DAG) const {
// Number of values to return // Number of values to return
unsigned NumRet = Outs.size(); unsigned NumRet = Outs.size();
@ -1305,7 +1310,7 @@ PIC16TargetLowering::LowerReturn(SDValue Chain,
void PIC16TargetLowering:: void PIC16TargetLowering::
GetDataAddress(DebugLoc dl, SDValue Callee, SDValue &Chain, GetDataAddress(DebugLoc dl, SDValue Callee, SDValue &Chain,
SDValue &DataAddr_Lo, SDValue &DataAddr_Hi, SDValue &DataAddr_Lo, SDValue &DataAddr_Hi,
SelectionDAG &DAG) { SelectionDAG &DAG) const {
assert (Callee.getOpcode() == PIC16ISD::PIC16Connect assert (Callee.getOpcode() == PIC16ISD::PIC16Connect
&& "Don't know what to do of such callee!!"); && "Don't know what to do of such callee!!");
SDValue ZeroOperand = DAG.getConstant(0, MVT::i8); SDValue ZeroOperand = DAG.getConstant(0, MVT::i8);
@ -1371,7 +1376,7 @@ PIC16TargetLowering::LowerCall(SDValue Chain, SDValue Callee,
const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<ISD::OutputArg> &Outs,
const SmallVectorImpl<ISD::InputArg> &Ins, const SmallVectorImpl<ISD::InputArg> &Ins,
DebugLoc dl, SelectionDAG &DAG, DebugLoc dl, SelectionDAG &DAG,
SmallVectorImpl<SDValue> &InVals) { SmallVectorImpl<SDValue> &InVals) const {
// PIC16 target does not yet support tail call optimization. // PIC16 target does not yet support tail call optimization.
isTailCall = false; isTailCall = false;
@ -1489,7 +1494,7 @@ PIC16TargetLowering::LowerCall(SDValue Chain, SDValue Callee,
DataAddr_Hi, Ins, dl, DAG, InVals); DataAddr_Hi, Ins, dl, DAG, InVals);
} }
bool PIC16TargetLowering::isDirectLoad(const SDValue Op) { bool PIC16TargetLowering::isDirectLoad(const SDValue Op) const {
if (Op.getOpcode() == PIC16ISD::PIC16Load) if (Op.getOpcode() == PIC16ISD::PIC16Load)
if (Op.getOperand(1).getOpcode() == ISD::TargetGlobalAddress if (Op.getOperand(1).getOpcode() == ISD::TargetGlobalAddress
|| Op.getOperand(1).getOpcode() == ISD::TargetExternalSymbol) || Op.getOperand(1).getOpcode() == ISD::TargetExternalSymbol)
@ -1503,7 +1508,7 @@ bool PIC16TargetLowering::isDirectLoad(const SDValue Op) {
// no instruction that can operation on two registers. Most insns take // no instruction that can operation on two registers. Most insns take
// one register and one memory operand (addwf) / Constant (addlw). // one register and one memory operand (addwf) / Constant (addlw).
bool PIC16TargetLowering::NeedToConvertToMemOp(SDValue Op, unsigned &MemOp, bool PIC16TargetLowering::NeedToConvertToMemOp(SDValue Op, unsigned &MemOp,
SelectionDAG &DAG) { SelectionDAG &DAG) const {
// If one of the operand is a constant, return false. // If one of the operand is a constant, return false.
if (Op.getOperand(0).getOpcode() == ISD::Constant || if (Op.getOperand(0).getOpcode() == ISD::Constant ||
Op.getOperand(1).getOpcode() == ISD::Constant) Op.getOperand(1).getOpcode() == ISD::Constant)
@ -1525,7 +1530,9 @@ bool PIC16TargetLowering::NeedToConvertToMemOp(SDValue Op, unsigned &MemOp,
// Direct load operands are folded in binary operations. But before folding // Direct load operands are folded in binary operations. But before folding
// verify if this folding is legal. Fold only if it is legal otherwise // verify if this folding is legal. Fold only if it is legal otherwise
// convert this direct load to a separate memory operation. // convert this direct load to a separate memory operation.
if(ISel->IsLegalToFold(Op.getOperand(0), Op.getNode(), Op.getNode())) if (SelectionDAGISel::IsLegalToFold(Op.getOperand(0),
Op.getNode(), Op.getNode(),
CodeGenOpt::Default))
return false; return false;
else else
MemOp = 0; MemOp = 0;
@ -1552,7 +1559,9 @@ bool PIC16TargetLowering::NeedToConvertToMemOp(SDValue Op, unsigned &MemOp,
// Direct load operands are folded in binary operations. But before folding // Direct load operands are folded in binary operations. But before folding
// verify if this folding is legal. Fold only if it is legal otherwise // verify if this folding is legal. Fold only if it is legal otherwise
// convert this direct load to a separate memory operation. // convert this direct load to a separate memory operation.
if(ISel->IsLegalToFold(Op.getOperand(1), Op.getNode(), Op.getNode())) if (SelectionDAGISel::IsLegalToFold(Op.getOperand(1),
Op.getNode(), Op.getNode(),
CodeGenOpt::Default))
return false; return false;
else else
MemOp = 1; MemOp = 1;
@ -1563,7 +1572,7 @@ bool PIC16TargetLowering::NeedToConvertToMemOp(SDValue Op, unsigned &MemOp,
// LowerBinOp - Lower a commutative binary operation that does not // LowerBinOp - Lower a commutative binary operation that does not
// affect status flag carry. // affect status flag carry.
SDValue PIC16TargetLowering::LowerBinOp(SDValue Op, SelectionDAG &DAG) { SDValue PIC16TargetLowering::LowerBinOp(SDValue Op, SelectionDAG &DAG) const {
DebugLoc dl = Op.getDebugLoc(); DebugLoc dl = Op.getDebugLoc();
// We should have handled larger operands in type legalizer itself. // We should have handled larger operands in type legalizer itself.
@ -1584,7 +1593,7 @@ SDValue PIC16TargetLowering::LowerBinOp(SDValue Op, SelectionDAG &DAG) {
// LowerADD - Lower all types of ADD operations including the ones // LowerADD - Lower all types of ADD operations including the ones
// that affects carry. // that affects carry.
SDValue PIC16TargetLowering::LowerADD(SDValue Op, SelectionDAG &DAG) { SDValue PIC16TargetLowering::LowerADD(SDValue Op, SelectionDAG &DAG) const {
// We should have handled larger operands in type legalizer itself. // We should have handled larger operands in type legalizer itself.
assert (Op.getValueType() == MVT::i8 && "illegal add to lower"); assert (Op.getValueType() == MVT::i8 && "illegal add to lower");
DebugLoc dl = Op.getDebugLoc(); DebugLoc dl = Op.getDebugLoc();
@ -1613,7 +1622,7 @@ SDValue PIC16TargetLowering::LowerADD(SDValue Op, SelectionDAG &DAG) {
return Op; return Op;
} }
SDValue PIC16TargetLowering::LowerSUB(SDValue Op, SelectionDAG &DAG) { SDValue PIC16TargetLowering::LowerSUB(SDValue Op, SelectionDAG &DAG) const {
DebugLoc dl = Op.getDebugLoc(); DebugLoc dl = Op.getDebugLoc();
// We should have handled larger operands in type legalizer itself. // We should have handled larger operands in type legalizer itself.
assert (Op.getValueType() == MVT::i8 && "illegal sub to lower"); assert (Op.getValueType() == MVT::i8 && "illegal sub to lower");
@ -1661,7 +1670,7 @@ SDValue PIC16TargetLowering::LowerSUB(SDValue Op, SelectionDAG &DAG) {
} }
void PIC16TargetLowering::InitReservedFrameCount(const Function *F, void PIC16TargetLowering::InitReservedFrameCount(const Function *F,
SelectionDAG &DAG) { SelectionDAG &DAG) const {
MachineFunction &MF = DAG.getMachineFunction(); MachineFunction &MF = DAG.getMachineFunction();
PIC16MachineFunctionInfo *FuncInfo = MF.getInfo<PIC16MachineFunctionInfo>(); PIC16MachineFunctionInfo *FuncInfo = MF.getInfo<PIC16MachineFunctionInfo>();
@ -1686,7 +1695,8 @@ PIC16TargetLowering::LowerFormalArguments(SDValue Chain,
const SmallVectorImpl<ISD::InputArg> &Ins, const SmallVectorImpl<ISD::InputArg> &Ins,
DebugLoc dl, DebugLoc dl,
SelectionDAG &DAG, SelectionDAG &DAG,
SmallVectorImpl<SDValue> &InVals) { SmallVectorImpl<SDValue> &InVals)
const {
unsigned NumArgVals = Ins.size(); unsigned NumArgVals = Ins.size();
// Get the callee's name to create the <fname>.args label to pass args. // Get the callee's name to create the <fname>.args label to pass args.
@ -1799,7 +1809,7 @@ static void LookThroughSetCC(SDValue &LHS, SDValue &RHS,
// Returns appropriate CMP insn and corresponding condition code in PIC16CC // Returns appropriate CMP insn and corresponding condition code in PIC16CC
SDValue PIC16TargetLowering::getPIC16Cmp(SDValue LHS, SDValue RHS, SDValue PIC16TargetLowering::getPIC16Cmp(SDValue LHS, SDValue RHS,
unsigned CC, SDValue &PIC16CC, unsigned CC, SDValue &PIC16CC,
SelectionDAG &DAG, DebugLoc dl) { SelectionDAG &DAG, DebugLoc dl) const {
PIC16CC::CondCodes CondCode = (PIC16CC::CondCodes) CC; PIC16CC::CondCodes CondCode = (PIC16CC::CondCodes) CC;
// PIC16 sub is literal - W. So Swap the operands and condition if needed. // PIC16 sub is literal - W. So Swap the operands and condition if needed.
@ -1863,7 +1873,8 @@ SDValue PIC16TargetLowering::getPIC16Cmp(SDValue LHS, SDValue RHS,
} }
SDValue PIC16TargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) { SDValue PIC16TargetLowering::LowerSELECT_CC(SDValue Op,
SelectionDAG &DAG) const {
SDValue LHS = Op.getOperand(0); SDValue LHS = Op.getOperand(0);
SDValue RHS = Op.getOperand(1); SDValue RHS = Op.getOperand(1);
ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get(); ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
@ -1955,7 +1966,7 @@ PIC16TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
} }
SDValue PIC16TargetLowering::LowerBR_CC(SDValue Op, SelectionDAG &DAG) { SDValue PIC16TargetLowering::LowerBR_CC(SDValue Op, SelectionDAG &DAG) const {
SDValue Chain = Op.getOperand(0); SDValue Chain = Op.getOperand(0);
ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get(); ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
SDValue LHS = Op.getOperand(2); // LHS of the condition. SDValue LHS = Op.getOperand(2); // LHS of the condition.

82
llvm/lib/Target/PIC16/PIC16ISelLowering.h
View File

@ -18,7 +18,6 @@
#include "PIC16.h" #include "PIC16.h"
#include "PIC16Subtarget.h" #include "PIC16Subtarget.h"
#include "llvm/CodeGen/SelectionDAG.h" #include "llvm/CodeGen/SelectionDAG.h"
#include "llvm/CodeGen/SelectionDAGISel.h"
#include "llvm/Target/TargetLowering.h" #include "llvm/Target/TargetLowering.h"
#include <map> #include <map>
@ -85,53 +84,53 @@ namespace llvm {
/// getSetCCResultType - Return the ISD::SETCC ValueType /// getSetCCResultType - Return the ISD::SETCC ValueType
virtual MVT::SimpleValueType getSetCCResultType(EVT ValType) const; virtual MVT::SimpleValueType getSetCCResultType(EVT ValType) const;
virtual MVT::SimpleValueType getCmpLibcallReturnType() const; virtual MVT::SimpleValueType getCmpLibcallReturnType() const;
SDValue LowerShift(SDValue Op, SelectionDAG &DAG); SDValue LowerShift(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerMUL(SDValue Op, SelectionDAG &DAG); SDValue LowerMUL(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerADD(SDValue Op, SelectionDAG &DAG); SDValue LowerADD(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerSUB(SDValue Op, SelectionDAG &DAG); SDValue LowerSUB(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerBinOp(SDValue Op, SelectionDAG &DAG); SDValue LowerBinOp(SDValue Op, SelectionDAG &DAG) const;
// Call returns // Call returns
SDValue SDValue
LowerDirectCallReturn(SDValue RetLabel, SDValue Chain, SDValue InFlag, LowerDirectCallReturn(SDValue RetLabel, SDValue Chain, SDValue InFlag,
const SmallVectorImpl<ISD::InputArg> &Ins, const SmallVectorImpl<ISD::InputArg> &Ins,
DebugLoc dl, SelectionDAG &DAG, DebugLoc dl, SelectionDAG &DAG,
SmallVectorImpl<SDValue> &InVals); SmallVectorImpl<SDValue> &InVals) const;
SDValue SDValue
LowerIndirectCallReturn(SDValue Chain, SDValue InFlag, LowerIndirectCallReturn(SDValue Chain, SDValue InFlag,
SDValue DataAddr_Lo, SDValue DataAddr_Hi, SDValue DataAddr_Lo, SDValue DataAddr_Hi,
const SmallVectorImpl<ISD::InputArg> &Ins, const SmallVectorImpl<ISD::InputArg> &Ins,
DebugLoc dl, SelectionDAG &DAG, DebugLoc dl, SelectionDAG &DAG,
SmallVectorImpl<SDValue> &InVals); SmallVectorImpl<SDValue> &InVals) const;
// Call arguments // Call arguments
SDValue SDValue
LowerDirectCallArguments(SDValue ArgLabel, SDValue Chain, SDValue InFlag, LowerDirectCallArguments(SDValue ArgLabel, SDValue Chain, SDValue InFlag,
const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<ISD::OutputArg> &Outs,
DebugLoc dl, SelectionDAG &DAG); DebugLoc dl, SelectionDAG &DAG) const;
SDValue SDValue
LowerIndirectCallArguments(SDValue Chain, SDValue InFlag, LowerIndirectCallArguments(SDValue Chain, SDValue InFlag,
SDValue DataAddr_Lo, SDValue DataAddr_Hi, SDValue DataAddr_Lo, SDValue DataAddr_Hi,
const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<ISD::OutputArg> &Outs,
const SmallVectorImpl<ISD::InputArg> &Ins, const SmallVectorImpl<ISD::InputArg> &Ins,
DebugLoc dl, SelectionDAG &DAG); DebugLoc dl, SelectionDAG &DAG) const;
SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG); SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG); SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const;
SDValue getPIC16Cmp(SDValue LHS, SDValue RHS, unsigned OrigCC, SDValue &CC, SDValue getPIC16Cmp(SDValue LHS, SDValue RHS, unsigned OrigCC, SDValue &CC,
SelectionDAG &DAG, DebugLoc dl); SelectionDAG &DAG, DebugLoc dl) const;
virtual MachineBasicBlock *EmitInstrWithCustomInserter(MachineInstr *MI, virtual MachineBasicBlock *EmitInstrWithCustomInserter(MachineInstr *MI,
MachineBasicBlock *MBB, MachineBasicBlock *MBB,
DenseMap<MachineBasicBlock*, MachineBasicBlock*> *EM) const; DenseMap<MachineBasicBlock*, MachineBasicBlock*> *EM) const;
virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG); virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
virtual void ReplaceNodeResults(SDNode *N, virtual void ReplaceNodeResults(SDNode *N,
SmallVectorImpl<SDValue> &Results, SmallVectorImpl<SDValue> &Results,
SelectionDAG &DAG); SelectionDAG &DAG) const;
virtual void LowerOperationWrapper(SDNode *N, virtual void LowerOperationWrapper(SDNode *N,
SmallVectorImpl<SDValue> &Results, SmallVectorImpl<SDValue> &Results,
SelectionDAG &DAG); SelectionDAG &DAG) const;
virtual SDValue virtual SDValue
LowerFormalArguments(SDValue Chain, LowerFormalArguments(SDValue Chain,
@ -139,7 +138,7 @@ namespace llvm {
bool isVarArg, bool isVarArg,
const SmallVectorImpl<ISD::InputArg> &Ins, const SmallVectorImpl<ISD::InputArg> &Ins,
DebugLoc dl, SelectionDAG &DAG, DebugLoc dl, SelectionDAG &DAG,
SmallVectorImpl<SDValue> &InVals); SmallVectorImpl<SDValue> &InVals) const;
virtual SDValue virtual SDValue
LowerCall(SDValue Chain, SDValue Callee, LowerCall(SDValue Chain, SDValue Callee,
@ -147,19 +146,19 @@ namespace llvm {
const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<ISD::OutputArg> &Outs,
const SmallVectorImpl<ISD::InputArg> &Ins, const SmallVectorImpl<ISD::InputArg> &Ins,
DebugLoc dl, SelectionDAG &DAG, DebugLoc dl, SelectionDAG &DAG,
SmallVectorImpl<SDValue> &InVals); SmallVectorImpl<SDValue> &InVals) const;
virtual SDValue virtual SDValue
LowerReturn(SDValue Chain, LowerReturn(SDValue Chain,
CallingConv::ID CallConv, bool isVarArg, CallingConv::ID CallConv, bool isVarArg,
const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<ISD::OutputArg> &Outs,
DebugLoc dl, SelectionDAG &DAG); DebugLoc dl, SelectionDAG &DAG) const;
SDValue ExpandStore(SDNode *N, SelectionDAG &DAG); SDValue ExpandStore(SDNode *N, SelectionDAG &DAG) const;
SDValue ExpandLoad(SDNode *N, SelectionDAG &DAG); SDValue ExpandLoad(SDNode *N, SelectionDAG &DAG) const;
SDValue ExpandGlobalAddress(SDNode *N, SelectionDAG &DAG); SDValue ExpandGlobalAddress(SDNode *N, SelectionDAG &DAG) const;
SDValue ExpandExternalSymbol(SDNode *N, SelectionDAG &DAG); SDValue ExpandExternalSymbol(SDNode *N, SelectionDAG &DAG) const;
SDValue ExpandFrameIndex(SDNode *N, SelectionDAG &DAG); SDValue ExpandFrameIndex(SDNode *N, SelectionDAG &DAG) const;
SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const; SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
SDValue PerformPIC16LoadCombine(SDNode *N, DAGCombinerInfo &DCI) const; SDValue PerformPIC16LoadCombine(SDNode *N, DAGCombinerInfo &DCI) const;
@ -169,10 +168,10 @@ namespace llvm {
// already exists for the FI then it returns the same else it creates the // already exists for the FI then it returns the same else it creates the
// new offset and returns. // new offset and returns.
unsigned GetTmpOffsetForFI(unsigned FI, unsigned slot_size, unsigned GetTmpOffsetForFI(unsigned FI, unsigned slot_size,
MachineFunction &MF); MachineFunction &MF) const;
void ResetTmpOffsetMap(SelectionDAG &DAG); void ResetTmpOffsetMap(SelectionDAG &DAG) const;
void InitReservedFrameCount(const Function *F, void InitReservedFrameCount(const Function *F,
SelectionDAG &DAG); SelectionDAG &DAG) const;
/// getFunctionAlignment - Return the Log2 alignment of this function. /// getFunctionAlignment - Return the Log2 alignment of this function.
virtual unsigned getFunctionAlignment(const Function *) const { virtual unsigned getFunctionAlignment(const Function *) const {
@ -182,43 +181,45 @@ namespace llvm {
private: private:
// If the Node is a BUILD_PAIR representing a direct Address, // If the Node is a BUILD_PAIR representing a direct Address,
// then this function will return true. // then this function will return true.
bool isDirectAddress(const SDValue &Op); bool isDirectAddress(const SDValue &Op) const;
// If the Node is a DirectAddress in ROM_SPACE then this // If the Node is a DirectAddress in ROM_SPACE then this
// function will return true // function will return true
bool isRomAddress(const SDValue &Op); bool isRomAddress(const SDValue &Op) const;
// Extract the Lo and Hi component of Op. // Extract the Lo and Hi component of Op.
void GetExpandedParts(SDValue Op, SelectionDAG &DAG, SDValue &Lo, void GetExpandedParts(SDValue Op, SelectionDAG &DAG, SDValue &Lo,
SDValue &Hi); SDValue &Hi) const;
// Load pointer can be a direct or indirect address. In PIC16 direct // Load pointer can be a direct or indirect address. In PIC16 direct
// addresses need Banksel and Indirect addresses need to be loaded to // addresses need Banksel and Indirect addresses need to be loaded to
// FSR first. Handle address specific cases here. // FSR first. Handle address specific cases here.
void LegalizeAddress(SDValue Ptr, SelectionDAG &DAG, SDValue &Chain, void LegalizeAddress(SDValue Ptr, SelectionDAG &DAG, SDValue &Chain,
SDValue &NewPtr, unsigned &Offset, DebugLoc dl); SDValue &NewPtr, unsigned &Offset, DebugLoc dl) const;
// FrameIndex should be broken down into ExternalSymbol and FrameOffset. // FrameIndex should be broken down into ExternalSymbol and FrameOffset.
void LegalizeFrameIndex(SDValue Op, SelectionDAG &DAG, SDValue &ES, void LegalizeFrameIndex(SDValue Op, SelectionDAG &DAG, SDValue &ES,
int &Offset); int &Offset) const;
// For indirect calls data address of the callee frame need to be // For indirect calls data address of the callee frame need to be
// extracted. This function fills the arguments DataAddr_Lo and // extracted. This function fills the arguments DataAddr_Lo and
// DataAddr_Hi with the address of the callee frame. // DataAddr_Hi with the address of the callee frame.
void GetDataAddress(DebugLoc dl, SDValue Callee, SDValue &Chain, void GetDataAddress(DebugLoc dl, SDValue Callee, SDValue &Chain,
SDValue &DataAddr_Lo, SDValue &DataAddr_Hi, SDValue &DataAddr_Lo, SDValue &DataAddr_Hi,
SelectionDAG &DAG); SelectionDAG &DAG) const;
// We can not have both operands of a binary operation in W. // We can not have both operands of a binary operation in W.
// This function is used to put one operand on stack and generate a load. // This function is used to put one operand on stack and generate a load.
SDValue ConvertToMemOperand(SDValue Op, SelectionDAG &DAG, DebugLoc dl); SDValue ConvertToMemOperand(SDValue Op, SelectionDAG &DAG,
DebugLoc dl) const;
// This function checks if we need to put an operand of an operation on // This function checks if we need to put an operand of an operation on
// stack and generate a load or not. // stack and generate a load or not.
// DAG parameter is required to access DAG information during // DAG parameter is required to access DAG information during
// analysis. // analysis.
bool NeedToConvertToMemOp(SDValue Op, unsigned &MemOp, SelectionDAG &DAG); bool NeedToConvertToMemOp(SDValue Op, unsigned &MemOp,
SelectionDAG &DAG) const;
/// Subtarget - Keep a pointer to the PIC16Subtarget around so that we can /// Subtarget - Keep a pointer to the PIC16Subtarget around so that we can
/// make the right decision when generating code for different targets. /// make the right decision when generating code for different targets.
@ -231,20 +232,15 @@ namespace llvm {
// To set and retrieve the lib call names. // To set and retrieve the lib call names.
void setPIC16LibcallName(PIC16ISD::PIC16Libcall Call, const char *Name); void setPIC16LibcallName(PIC16ISD::PIC16Libcall Call, const char *Name);
const char *getPIC16LibcallName(PIC16ISD::PIC16Libcall Call); const char *getPIC16LibcallName(PIC16ISD::PIC16Libcall Call) const;
// Make PIC16 Libcall. // Make PIC16 Libcall.
SDValue MakePIC16Libcall(PIC16ISD::PIC16Libcall Call, EVT RetVT, SDValue MakePIC16Libcall(PIC16ISD::PIC16Libcall Call, EVT RetVT,
const SDValue *Ops, unsigned NumOps, bool isSigned, const SDValue *Ops, unsigned NumOps, bool isSigned,
SelectionDAG &DAG, DebugLoc dl); SelectionDAG &DAG, DebugLoc dl) const;
// Check if operation has a direct load operand. // Check if operation has a direct load operand.
inline bool isDirectLoad(const SDValue Op); inline bool isDirectLoad(const SDValue Op) const;
public:
// Keep a pointer to SelectionDAGISel to access its public
// interface (It is required during legalization)
SelectionDAGISel *ISel;
}; };
} // namespace llvm } // namespace llvm

4
llvm/lib/Target/PIC16/PIC16InstrInfo.cpp
View File

@ -71,7 +71,7 @@ void PIC16InstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
MachineBasicBlock::iterator I, MachineBasicBlock::iterator I,
unsigned SrcReg, bool isKill, int FI, unsigned SrcReg, bool isKill, int FI,
const TargetRegisterClass *RC) const { const TargetRegisterClass *RC) const {
PIC16TargetLowering *PTLI = TM.getTargetLowering(); const PIC16TargetLowering *PTLI = TM.getTargetLowering();
DebugLoc DL; DebugLoc DL;
if (I != MBB.end()) DL = I->getDebugLoc(); if (I != MBB.end()) DL = I->getDebugLoc();
@ -113,7 +113,7 @@ void PIC16InstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
MachineBasicBlock::iterator I, MachineBasicBlock::iterator I,
unsigned DestReg, int FI, unsigned DestReg, int FI,
const TargetRegisterClass *RC) const { const TargetRegisterClass *RC) const {
PIC16TargetLowering *PTLI = TM.getTargetLowering(); const PIC16TargetLowering *PTLI = TM.getTargetLowering();
DebugLoc DL; DebugLoc DL;
if (I != MBB.end()) DL = I->getDebugLoc(); if (I != MBB.end()) DL = I->getDebugLoc();

4
llvm/lib/Target/PIC16/PIC16TargetMachine.h
View File

@ -50,8 +50,8 @@ public:
return &(InstrInfo.getRegisterInfo()); return &(InstrInfo.getRegisterInfo());
} }
virtual PIC16TargetLowering *getTargetLowering() const { virtual const PIC16TargetLowering *getTargetLowering() const {
return const_cast<PIC16TargetLowering*>(&TLInfo); return &TLInfo;
} }
virtual bool addInstSelector(PassManagerBase &PM, virtual bool addInstSelector(PassManagerBase &PM,

1
llvm/lib/Target/PIC16/PIC16TargetObjectFile.cpp
View File

@ -8,7 +8,6 @@
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
#include "PIC16TargetObjectFile.h" #include "PIC16TargetObjectFile.h"
#include "PIC16ISelLowering.h"
#include "PIC16TargetMachine.h" #include "PIC16TargetMachine.h"
#include "PIC16Section.h" #include "PIC16Section.h"
#include "llvm/DerivedTypes.h" #include "llvm/DerivedTypes.h"

5
llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
View File

@ -16,7 +16,6 @@
#include "PPC.h" #include "PPC.h"
#include "PPCPredicates.h" #include "PPCPredicates.h"
#include "PPCTargetMachine.h" #include "PPCTargetMachine.h"
#include "PPCISelLowering.h"
#include "PPCHazardRecognizers.h" #include "PPCHazardRecognizers.h"
#include "llvm/CodeGen/MachineInstrBuilder.h" #include "llvm/CodeGen/MachineInstrBuilder.h"
#include "llvm/CodeGen/MachineFunction.h" #include "llvm/CodeGen/MachineFunction.h"
@ -41,8 +40,8 @@ namespace {
/// instructions for SelectionDAG operations. /// instructions for SelectionDAG operations.
/// ///
class PPCDAGToDAGISel : public SelectionDAGISel { class PPCDAGToDAGISel : public SelectionDAGISel {
PPCTargetMachine &TM; const PPCTargetMachine &TM;
PPCTargetLowering &PPCLowering; const PPCTargetLowering &PPCLowering;
const PPCSubtarget &PPCSubTarget; const PPCSubtarget &PPCSubTarget;
unsigned GlobalBaseReg; unsigned GlobalBaseReg;
public: public:

82
llvm/lib/Target/PowerPC/PPCISelLowering.cpp
View File

@ -1095,7 +1095,7 @@ bool PPCTargetLowering::getPreIndexedAddressParts(SDNode *N, SDValue &Base,
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
SDValue PPCTargetLowering::LowerConstantPool(SDValue Op, SDValue PPCTargetLowering::LowerConstantPool(SDValue Op,
SelectionDAG &DAG) { SelectionDAG &DAG) const {
EVT PtrVT = Op.getValueType(); EVT PtrVT = Op.getValueType();
ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op); ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
const Constant *C = CP->getConstVal(); const Constant *C = CP->getConstVal();
@ -1129,7 +1129,7 @@ SDValue PPCTargetLowering::LowerConstantPool(SDValue Op,
return Lo; return Lo;
} }
SDValue PPCTargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) { SDValue PPCTargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) const {
EVT PtrVT = Op.getValueType(); EVT PtrVT = Op.getValueType();
JumpTableSDNode *JT = cast<JumpTableSDNode>(Op); JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
SDValue JTI = DAG.getTargetJumpTable(JT->getIndex(), PtrVT); SDValue JTI = DAG.getTargetJumpTable(JT->getIndex(), PtrVT);
@ -1163,12 +1163,13 @@ SDValue PPCTargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) {
} }
SDValue PPCTargetLowering::LowerGlobalTLSAddress(SDValue Op, SDValue PPCTargetLowering::LowerGlobalTLSAddress(SDValue Op,
SelectionDAG &DAG) { SelectionDAG &DAG) const {
llvm_unreachable("TLS not implemented for PPC."); llvm_unreachable("TLS not implemented for PPC.");
return SDValue(); // Not reached return SDValue(); // Not reached
} }
SDValue PPCTargetLowering::LowerBlockAddress(SDValue Op, SelectionDAG &DAG) { SDValue PPCTargetLowering::LowerBlockAddress(SDValue Op,
SelectionDAG &DAG) const {
EVT PtrVT = Op.getValueType(); EVT PtrVT = Op.getValueType();
DebugLoc DL = Op.getDebugLoc(); DebugLoc DL = Op.getDebugLoc();
@ -1199,7 +1200,7 @@ SDValue PPCTargetLowering::LowerBlockAddress(SDValue Op, SelectionDAG &DAG) {
} }
SDValue PPCTargetLowering::LowerGlobalAddress(SDValue Op, SDValue PPCTargetLowering::LowerGlobalAddress(SDValue Op,
SelectionDAG &DAG) { SelectionDAG &DAG) const {
EVT PtrVT = Op.getValueType(); EVT PtrVT = Op.getValueType();
GlobalAddressSDNode *GSDN = cast<GlobalAddressSDNode>(Op); GlobalAddressSDNode *GSDN = cast<GlobalAddressSDNode>(Op);
const GlobalValue *GV = GSDN->getGlobal(); const GlobalValue *GV = GSDN->getGlobal();
@ -1247,7 +1248,7 @@ SDValue PPCTargetLowering::LowerGlobalAddress(SDValue Op,
false, false, 0); false, false, 0);
} }
SDValue PPCTargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) { SDValue PPCTargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get(); ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
DebugLoc dl = Op.getDebugLoc(); DebugLoc dl = Op.getDebugLoc();
@ -1291,13 +1292,14 @@ SDValue PPCTargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) {
} }
SDValue PPCTargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG, SDValue PPCTargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG,
const PPCSubtarget &Subtarget) { const PPCSubtarget &Subtarget) const {
llvm_unreachable("VAARG not yet implemented for the SVR4 ABI!"); llvm_unreachable("VAARG not yet implemented for the SVR4 ABI!");
return SDValue(); // Not reached return SDValue(); // Not reached
} }
SDValue PPCTargetLowering::LowerTRAMPOLINE(SDValue Op, SelectionDAG &DAG) { SDValue PPCTargetLowering::LowerTRAMPOLINE(SDValue Op,
SelectionDAG &DAG) const {
SDValue Chain = Op.getOperand(0); SDValue Chain = Op.getOperand(0);
SDValue Trmp = Op.getOperand(1); // trampoline SDValue Trmp = Op.getOperand(1); // trampoline
SDValue FPtr = Op.getOperand(2); // nested function SDValue FPtr = Op.getOperand(2); // nested function
@ -1339,7 +1341,7 @@ SDValue PPCTargetLowering::LowerTRAMPOLINE(SDValue Op, SelectionDAG &DAG) {
} }
SDValue PPCTargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG, SDValue PPCTargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG,
const PPCSubtarget &Subtarget) { const PPCSubtarget &Subtarget) const {
MachineFunction &MF = DAG.getMachineFunction(); MachineFunction &MF = DAG.getMachineFunction();
PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>(); PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
@ -1522,7 +1524,8 @@ PPCTargetLowering::LowerFormalArguments(SDValue Chain,
const SmallVectorImpl<ISD::InputArg> const SmallVectorImpl<ISD::InputArg>
&Ins, &Ins,
DebugLoc dl, SelectionDAG &DAG, DebugLoc dl, SelectionDAG &DAG,
SmallVectorImpl<SDValue> &InVals) { SmallVectorImpl<SDValue> &InVals)
const {
if (PPCSubTarget.isSVR4ABI() && !PPCSubTarget.isPPC64()) { if (PPCSubTarget.isSVR4ABI() && !PPCSubTarget.isPPC64()) {
return LowerFormalArguments_SVR4(Chain, CallConv, isVarArg, Ins, return LowerFormalArguments_SVR4(Chain, CallConv, isVarArg, Ins,
dl, DAG, InVals); dl, DAG, InVals);
@ -1539,7 +1542,7 @@ PPCTargetLowering::LowerFormalArguments_SVR4(
const SmallVectorImpl<ISD::InputArg> const SmallVectorImpl<ISD::InputArg>
&Ins, &Ins,
DebugLoc dl, SelectionDAG &DAG, DebugLoc dl, SelectionDAG &DAG,
SmallVectorImpl<SDValue> &InVals) { SmallVectorImpl<SDValue> &InVals) const {
// 32-bit SVR4 ABI Stack Frame Layout: // 32-bit SVR4 ABI Stack Frame Layout:
// +-----------------------------------+ // +-----------------------------------+
@ -1776,7 +1779,7 @@ PPCTargetLowering::LowerFormalArguments_Darwin(
const SmallVectorImpl<ISD::InputArg> const SmallVectorImpl<ISD::InputArg>
&Ins, &Ins,
DebugLoc dl, SelectionDAG &DAG, DebugLoc dl, SelectionDAG &DAG,
SmallVectorImpl<SDValue> &InVals) { SmallVectorImpl<SDValue> &InVals) const {
// TODO: add description of PPC stack frame format, or at least some docs. // TODO: add description of PPC stack frame format, or at least some docs.
// //
MachineFunction &MF = DAG.getMachineFunction(); MachineFunction &MF = DAG.getMachineFunction();
@ -2362,7 +2365,7 @@ SDValue PPCTargetLowering::EmitTailCallLoadFPAndRetAddr(SelectionDAG & DAG,
SDValue &LROpOut, SDValue &LROpOut,
SDValue &FPOpOut, SDValue &FPOpOut,
bool isDarwinABI, bool isDarwinABI,
DebugLoc dl) { DebugLoc dl) const {
if (SPDiff) { if (SPDiff) {
// Load the LR and FP stack slot for later adjusting. // Load the LR and FP stack slot for later adjusting.
EVT VT = PPCSubTarget.isPPC64() ? MVT::i64 : MVT::i32; EVT VT = PPCSubTarget.isPPC64() ? MVT::i64 : MVT::i32;
@ -2585,7 +2588,7 @@ PPCTargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
CallingConv::ID CallConv, bool isVarArg, CallingConv::ID CallConv, bool isVarArg,
const SmallVectorImpl<ISD::InputArg> &Ins, const SmallVectorImpl<ISD::InputArg> &Ins,
DebugLoc dl, SelectionDAG &DAG, DebugLoc dl, SelectionDAG &DAG,
SmallVectorImpl<SDValue> &InVals) { SmallVectorImpl<SDValue> &InVals) const {
SmallVector<CCValAssign, 16> RVLocs; SmallVector<CCValAssign, 16> RVLocs;
CCState CCRetInfo(CallConv, isVarArg, getTargetMachine(), CCState CCRetInfo(CallConv, isVarArg, getTargetMachine(),
@ -2616,7 +2619,7 @@ PPCTargetLowering::FinishCall(CallingConv::ID CallConv, DebugLoc dl,
SDValue &Callee, SDValue &Callee,
int SPDiff, unsigned NumBytes, int SPDiff, unsigned NumBytes,
const SmallVectorImpl<ISD::InputArg> &Ins, const SmallVectorImpl<ISD::InputArg> &Ins,
SmallVectorImpl<SDValue> &InVals) { SmallVectorImpl<SDValue> &InVals) const {
std::vector<EVT> NodeTys; std::vector<EVT> NodeTys;
SmallVector<SDValue, 8> Ops; SmallVector<SDValue, 8> Ops;
unsigned CallOpc = PrepareCall(DAG, Callee, InFlag, Chain, dl, SPDiff, unsigned CallOpc = PrepareCall(DAG, Callee, InFlag, Chain, dl, SPDiff,
@ -2704,7 +2707,7 @@ PPCTargetLowering::LowerCall(SDValue Chain, SDValue Callee,
const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<ISD::OutputArg> &Outs,
const SmallVectorImpl<ISD::InputArg> &Ins, const SmallVectorImpl<ISD::InputArg> &Ins,
DebugLoc dl, SelectionDAG &DAG, DebugLoc dl, SelectionDAG &DAG,
SmallVectorImpl<SDValue> &InVals) { SmallVectorImpl<SDValue> &InVals) const {
if (isTailCall) if (isTailCall)
isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv, isVarArg, isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv, isVarArg,
Ins, DAG); Ins, DAG);
@ -2727,7 +2730,7 @@ PPCTargetLowering::LowerCall_SVR4(SDValue Chain, SDValue Callee,
const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<ISD::OutputArg> &Outs,
const SmallVectorImpl<ISD::InputArg> &Ins, const SmallVectorImpl<ISD::InputArg> &Ins,
DebugLoc dl, SelectionDAG &DAG, DebugLoc dl, SelectionDAG &DAG,
SmallVectorImpl<SDValue> &InVals) { SmallVectorImpl<SDValue> &InVals) const {
// See PPCTargetLowering::LowerFormalArguments_SVR4() for a description // See PPCTargetLowering::LowerFormalArguments_SVR4() for a description
// of the 32-bit SVR4 ABI stack frame layout. // of the 32-bit SVR4 ABI stack frame layout.
@ -2933,7 +2936,7 @@ PPCTargetLowering::LowerCall_Darwin(SDValue Chain, SDValue Callee,
const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<ISD::OutputArg> &Outs,
const SmallVectorImpl<ISD::InputArg> &Ins, const SmallVectorImpl<ISD::InputArg> &Ins,
DebugLoc dl, SelectionDAG &DAG, DebugLoc dl, SelectionDAG &DAG,
SmallVectorImpl<SDValue> &InVals) { SmallVectorImpl<SDValue> &InVals) const {
unsigned NumOps = Outs.size(); unsigned NumOps = Outs.size();
@ -3294,7 +3297,7 @@ SDValue
PPCTargetLowering::LowerReturn(SDValue Chain, PPCTargetLowering::LowerReturn(SDValue Chain,
CallingConv::ID CallConv, bool isVarArg, CallingConv::ID CallConv, bool isVarArg,
const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<ISD::OutputArg> &Outs,
DebugLoc dl, SelectionDAG &DAG) { DebugLoc dl, SelectionDAG &DAG) const {
SmallVector<CCValAssign, 16> RVLocs; SmallVector<CCValAssign, 16> RVLocs;
CCState CCInfo(CallConv, isVarArg, getTargetMachine(), CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
@ -3326,7 +3329,7 @@ PPCTargetLowering::LowerReturn(SDValue Chain,
} }
SDValue PPCTargetLowering::LowerSTACKRESTORE(SDValue Op, SelectionDAG &DAG, SDValue PPCTargetLowering::LowerSTACKRESTORE(SDValue Op, SelectionDAG &DAG,
const PPCSubtarget &Subtarget) { const PPCSubtarget &Subtarget) const {
// When we pop the dynamic allocation we need to restore the SP link. // When we pop the dynamic allocation we need to restore the SP link.
DebugLoc dl = Op.getDebugLoc(); DebugLoc dl = Op.getDebugLoc();
@ -3410,7 +3413,7 @@ PPCTargetLowering::getFramePointerFrameIndex(SelectionDAG & DAG) const {
SDValue PPCTargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op, SDValue PPCTargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
SelectionDAG &DAG, SelectionDAG &DAG,
const PPCSubtarget &Subtarget) { const PPCSubtarget &Subtarget) const {
// Get the inputs. // Get the inputs.
SDValue Chain = Op.getOperand(0); SDValue Chain = Op.getOperand(0);
SDValue Size = Op.getOperand(1); SDValue Size = Op.getOperand(1);
@ -3431,7 +3434,7 @@ SDValue PPCTargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
/// LowerSELECT_CC - Lower floating point select_cc's into fsel instruction when /// LowerSELECT_CC - Lower floating point select_cc's into fsel instruction when
/// possible. /// possible.
SDValue PPCTargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) { SDValue PPCTargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const {
// Not FP? Not a fsel. // Not FP? Not a fsel.
if (!Op.getOperand(0).getValueType().isFloatingPoint() || if (!Op.getOperand(0).getValueType().isFloatingPoint() ||
!Op.getOperand(2).getValueType().isFloatingPoint()) !Op.getOperand(2).getValueType().isFloatingPoint())
@ -3505,7 +3508,7 @@ SDValue PPCTargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) {
// FIXME: Split this code up when LegalizeDAGTypes lands. // FIXME: Split this code up when LegalizeDAGTypes lands.
SDValue PPCTargetLowering::LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG, SDValue PPCTargetLowering::LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG,
DebugLoc dl) { DebugLoc dl) const {
assert(Op.getOperand(0).getValueType().isFloatingPoint()); assert(Op.getOperand(0).getValueType().isFloatingPoint());
SDValue Src = Op.getOperand(0); SDValue Src = Op.getOperand(0);
if (Src.getValueType() == MVT::f32) if (Src.getValueType() == MVT::f32)
@ -3540,7 +3543,8 @@ SDValue PPCTargetLowering::LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG,
false, false, 0); false, false, 0);
} }
SDValue PPCTargetLowering::LowerSINT_TO_FP(SDValue Op, SelectionDAG &DAG) { SDValue PPCTargetLowering::LowerSINT_TO_FP(SDValue Op,
SelectionDAG &DAG) const {
DebugLoc dl = Op.getDebugLoc(); DebugLoc dl = Op.getDebugLoc();
// Don't handle ppc_fp128 here; let it be lowered to a libcall. // Don't handle ppc_fp128 here; let it be lowered to a libcall.
if (Op.getValueType() != MVT::f32 && Op.getValueType() != MVT::f64) if (Op.getValueType() != MVT::f32 && Op.getValueType() != MVT::f64)
@ -3589,7 +3593,8 @@ SDValue PPCTargetLowering::LowerSINT_TO_FP(SDValue Op, SelectionDAG &DAG) {
return FP; return FP;
} }
SDValue PPCTargetLowering::LowerFLT_ROUNDS_(SDValue Op, SelectionDAG &DAG) { SDValue PPCTargetLowering::LowerFLT_ROUNDS_(SDValue Op,
SelectionDAG &DAG) const {
DebugLoc dl = Op.getDebugLoc(); DebugLoc dl = Op.getDebugLoc();
/* /*
The rounding mode is in bits 30:31 of FPSR, and has the following The rounding mode is in bits 30:31 of FPSR, and has the following
@ -3652,7 +3657,7 @@ SDValue PPCTargetLowering::LowerFLT_ROUNDS_(SDValue Op, SelectionDAG &DAG) {
ISD::TRUNCATE : ISD::ZERO_EXTEND), dl, VT, RetVal); ISD::TRUNCATE : ISD::ZERO_EXTEND), dl, VT, RetVal);
} }
SDValue PPCTargetLowering::LowerSHL_PARTS(SDValue Op, SelectionDAG &DAG) { SDValue PPCTargetLowering::LowerSHL_PARTS(SDValue Op, SelectionDAG &DAG) const {
EVT VT = Op.getValueType(); EVT VT = Op.getValueType();
unsigned BitWidth = VT.getSizeInBits(); unsigned BitWidth = VT.getSizeInBits();
DebugLoc dl = Op.getDebugLoc(); DebugLoc dl = Op.getDebugLoc();
@ -3681,7 +3686,7 @@ SDValue PPCTargetLowering::LowerSHL_PARTS(SDValue Op, SelectionDAG &DAG) {
return DAG.getMergeValues(OutOps, 2, dl); return DAG.getMergeValues(OutOps, 2, dl);
} }
SDValue PPCTargetLowering::LowerSRL_PARTS(SDValue Op, SelectionDAG &DAG) { SDValue PPCTargetLowering::LowerSRL_PARTS(SDValue Op, SelectionDAG &DAG) const {
EVT VT = Op.getValueType(); EVT VT = Op.getValueType();
DebugLoc dl = Op.getDebugLoc(); DebugLoc dl = Op.getDebugLoc();
unsigned BitWidth = VT.getSizeInBits(); unsigned BitWidth = VT.getSizeInBits();
@ -3710,7 +3715,7 @@ SDValue PPCTargetLowering::LowerSRL_PARTS(SDValue Op, SelectionDAG &DAG) {
return DAG.getMergeValues(OutOps, 2, dl); return DAG.getMergeValues(OutOps, 2, dl);
} }
SDValue PPCTargetLowering::LowerSRA_PARTS(SDValue Op, SelectionDAG &DAG) { SDValue PPCTargetLowering::LowerSRA_PARTS(SDValue Op, SelectionDAG &DAG) const {
DebugLoc dl = Op.getDebugLoc(); DebugLoc dl = Op.getDebugLoc();
EVT VT = Op.getValueType(); EVT VT = Op.getValueType();
unsigned BitWidth = VT.getSizeInBits(); unsigned BitWidth = VT.getSizeInBits();
@ -3811,7 +3816,8 @@ static SDValue BuildVSLDOI(SDValue LHS, SDValue RHS, unsigned Amt,
// selects to a single instruction, return Op. Otherwise, if we can codegen // selects to a single instruction, return Op. Otherwise, if we can codegen
// this case more efficiently than a constant pool load, lower it to the // this case more efficiently than a constant pool load, lower it to the
// sequence of ops that should be used. // sequence of ops that should be used.
SDValue PPCTargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) { SDValue PPCTargetLowering::LowerBUILD_VECTOR(SDValue Op,
SelectionDAG &DAG) const {
DebugLoc dl = Op.getDebugLoc(); DebugLoc dl = Op.getDebugLoc();
BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(Op.getNode()); BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(Op.getNode());
assert(BVN != 0 && "Expected a BuildVectorSDNode in LowerBUILD_VECTOR"); assert(BVN != 0 && "Expected a BuildVectorSDNode in LowerBUILD_VECTOR");
@ -4053,7 +4059,7 @@ static SDValue GeneratePerfectShuffle(unsigned PFEntry, SDValue LHS,
/// return the code it can be lowered into. Worst case, it can always be /// return the code it can be lowered into. Worst case, it can always be
/// lowered into a vperm. /// lowered into a vperm.
SDValue PPCTargetLowering::LowerVECTOR_SHUFFLE(SDValue Op, SDValue PPCTargetLowering::LowerVECTOR_SHUFFLE(SDValue Op,
SelectionDAG &DAG) { SelectionDAG &DAG) const {
DebugLoc dl = Op.getDebugLoc(); DebugLoc dl = Op.getDebugLoc();
SDValue V1 = Op.getOperand(0); SDValue V1 = Op.getOperand(0);
SDValue V2 = Op.getOperand(1); SDValue V2 = Op.getOperand(1);
@ -4219,7 +4225,7 @@ static bool getAltivecCompareInfo(SDValue Intrin, int &CompareOpc,
/// LowerINTRINSIC_WO_CHAIN - If this is an intrinsic that we want to custom /// LowerINTRINSIC_WO_CHAIN - If this is an intrinsic that we want to custom
/// lower, do it, otherwise return null. /// lower, do it, otherwise return null.
SDValue PPCTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, SDValue PPCTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
SelectionDAG &DAG) { SelectionDAG &DAG) const {
// If this is a lowered altivec predicate compare, CompareOpc is set to the // If this is a lowered altivec predicate compare, CompareOpc is set to the
// opcode number of the comparison. // opcode number of the comparison.
DebugLoc dl = Op.getDebugLoc(); DebugLoc dl = Op.getDebugLoc();
@ -4287,7 +4293,7 @@ SDValue PPCTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
} }
SDValue PPCTargetLowering::LowerSCALAR_TO_VECTOR(SDValue Op, SDValue PPCTargetLowering::LowerSCALAR_TO_VECTOR(SDValue Op,
SelectionDAG &DAG) { SelectionDAG &DAG) const {
DebugLoc dl = Op.getDebugLoc(); DebugLoc dl = Op.getDebugLoc();
// Create a stack slot that is 16-byte aligned. // Create a stack slot that is 16-byte aligned.
MachineFrameInfo *FrameInfo = DAG.getMachineFunction().getFrameInfo(); MachineFrameInfo *FrameInfo = DAG.getMachineFunction().getFrameInfo();
@ -4304,7 +4310,7 @@ SDValue PPCTargetLowering::LowerSCALAR_TO_VECTOR(SDValue Op,
false, false, 0); false, false, 0);
} }
SDValue PPCTargetLowering::LowerMUL(SDValue Op, SelectionDAG &DAG) { SDValue PPCTargetLowering::LowerMUL(SDValue Op, SelectionDAG &DAG) const {
DebugLoc dl = Op.getDebugLoc(); DebugLoc dl = Op.getDebugLoc();
if (Op.getValueType() == MVT::v4i32) { if (Op.getValueType() == MVT::v4i32) {
SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1); SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1);
@ -4365,7 +4371,7 @@ SDValue PPCTargetLowering::LowerMUL(SDValue Op, SelectionDAG &DAG) {
/// LowerOperation - Provide custom lowering hooks for some operations. /// LowerOperation - Provide custom lowering hooks for some operations.
/// ///
SDValue PPCTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) { SDValue PPCTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
switch (Op.getOpcode()) { switch (Op.getOpcode()) {
default: llvm_unreachable("Wasn't expecting to be able to lower this!"); default: llvm_unreachable("Wasn't expecting to be able to lower this!");
case ISD::ConstantPool: return LowerConstantPool(Op, DAG); case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
@ -4413,7 +4419,7 @@ SDValue PPCTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) {
void PPCTargetLowering::ReplaceNodeResults(SDNode *N, void PPCTargetLowering::ReplaceNodeResults(SDNode *N,
SmallVectorImpl<SDValue>&Results, SmallVectorImpl<SDValue>&Results,
SelectionDAG &DAG) { SelectionDAG &DAG) const {
DebugLoc dl = N->getDebugLoc(); DebugLoc dl = N->getDebugLoc();
switch (N->getOpcode()) { switch (N->getOpcode()) {
default: default:
@ -5492,7 +5498,8 @@ bool PPCTargetLowering::isLegalAddressImmediate(llvm::GlobalValue* GV) const {
return false; return false;
} }
SDValue PPCTargetLowering::LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) { SDValue PPCTargetLowering::LowerRETURNADDR(SDValue Op,
SelectionDAG &DAG) const {
DebugLoc dl = Op.getDebugLoc(); DebugLoc dl = Op.getDebugLoc();
// Depths > 0 not supported yet! // Depths > 0 not supported yet!
if (cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue() > 0) if (cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue() > 0)
@ -5512,7 +5519,8 @@ SDValue PPCTargetLowering::LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) {
false, false, 0); false, false, 0);
} }
SDValue PPCTargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) { SDValue PPCTargetLowering::LowerFRAMEADDR(SDValue Op,
SelectionDAG &DAG) const {
DebugLoc dl = Op.getDebugLoc(); DebugLoc dl = Op.getDebugLoc();
// Depths > 0 not supported yet! // Depths > 0 not supported yet!
if (cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue() > 0) if (cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue() > 0)

74
llvm/lib/Target/PowerPC/PPCISelLowering.h
View File

@ -279,13 +279,13 @@ namespace llvm {
/// LowerOperation - Provide custom lowering hooks for some operations. /// LowerOperation - Provide custom lowering hooks for some operations.
/// ///
virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG); virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
/// ReplaceNodeResults - Replace the results of node with an illegal result /// ReplaceNodeResults - Replace the results of node with an illegal result
/// type with new values built out of custom code. /// type with new values built out of custom code.
/// ///
virtual void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results, virtual void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results,
SelectionDAG &DAG); SelectionDAG &DAG) const;
virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const; virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
@ -378,43 +378,43 @@ namespace llvm {
SDValue &LROpOut, SDValue &LROpOut,
SDValue &FPOpOut, SDValue &FPOpOut,
bool isDarwinABI, bool isDarwinABI,
DebugLoc dl); DebugLoc dl) const;
SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG); SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG); SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG); SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG); SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG); SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG); SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG); SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG); SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerTRAMPOLINE(SDValue Op, SelectionDAG &DAG); SDValue LowerTRAMPOLINE(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG, SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG,
const PPCSubtarget &Subtarget); const PPCSubtarget &Subtarget) const;
SDValue LowerVAARG(SDValue Op, SelectionDAG &DAG, SDValue LowerVAARG(SDValue Op, SelectionDAG &DAG,
const PPCSubtarget &Subtarget); const PPCSubtarget &Subtarget) const;
SDValue LowerSTACKRESTORE(SDValue Op, SelectionDAG &DAG, SDValue LowerSTACKRESTORE(SDValue Op, SelectionDAG &DAG,
const PPCSubtarget &Subtarget); const PPCSubtarget &Subtarget) const;
SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG, SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG,
const PPCSubtarget &Subtarget); const PPCSubtarget &Subtarget) const;
SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG); SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG, DebugLoc dl); SDValue LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG, DebugLoc dl) const;
SDValue LowerSINT_TO_FP(SDValue Op, SelectionDAG &DAG); SDValue LowerSINT_TO_FP(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerFLT_ROUNDS_(SDValue Op, SelectionDAG &DAG); SDValue LowerFLT_ROUNDS_(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerSHL_PARTS(SDValue Op, SelectionDAG &DAG); SDValue LowerSHL_PARTS(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerSRL_PARTS(SDValue Op, SelectionDAG &DAG); SDValue LowerSRL_PARTS(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerSRA_PARTS(SDValue Op, SelectionDAG &DAG); SDValue LowerSRA_PARTS(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG); SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG); SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG); SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG); SDValue LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerMUL(SDValue Op, SelectionDAG &DAG); SDValue LowerMUL(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerCallResult(SDValue Chain, SDValue InFlag, SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
CallingConv::ID CallConv, bool isVarArg, CallingConv::ID CallConv, bool isVarArg,
const SmallVectorImpl<ISD::InputArg> &Ins, const SmallVectorImpl<ISD::InputArg> &Ins,
DebugLoc dl, SelectionDAG &DAG, DebugLoc dl, SelectionDAG &DAG,
SmallVectorImpl<SDValue> &InVals); SmallVectorImpl<SDValue> &InVals) const;
SDValue FinishCall(CallingConv::ID CallConv, DebugLoc dl, bool isTailCall, SDValue FinishCall(CallingConv::ID CallConv, DebugLoc dl, bool isTailCall,
bool isVarArg, bool isVarArg,
SelectionDAG &DAG, SelectionDAG &DAG,
@ -424,14 +424,14 @@ namespace llvm {
SDValue &Callee, SDValue &Callee,
int SPDiff, unsigned NumBytes, int SPDiff, unsigned NumBytes,
const SmallVectorImpl<ISD::InputArg> &Ins, const SmallVectorImpl<ISD::InputArg> &Ins,
SmallVectorImpl<SDValue> &InVals); SmallVectorImpl<SDValue> &InVals) const;
virtual SDValue virtual SDValue
LowerFormalArguments(SDValue Chain, LowerFormalArguments(SDValue Chain,
CallingConv::ID CallConv, bool isVarArg, CallingConv::ID CallConv, bool isVarArg,
const SmallVectorImpl<ISD::InputArg> &Ins, const SmallVectorImpl<ISD::InputArg> &Ins,
DebugLoc dl, SelectionDAG &DAG, DebugLoc dl, SelectionDAG &DAG,
SmallVectorImpl<SDValue> &InVals); SmallVectorImpl<SDValue> &InVals) const;
virtual SDValue virtual SDValue
LowerCall(SDValue Chain, SDValue Callee, LowerCall(SDValue Chain, SDValue Callee,
@ -439,26 +439,26 @@ namespace llvm {
const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<ISD::OutputArg> &Outs,
const SmallVectorImpl<ISD::InputArg> &Ins, const SmallVectorImpl<ISD::InputArg> &Ins,
DebugLoc dl, SelectionDAG &DAG, DebugLoc dl, SelectionDAG &DAG,
SmallVectorImpl<SDValue> &InVals); SmallVectorImpl<SDValue> &InVals) const;
virtual SDValue virtual SDValue
LowerReturn(SDValue Chain, LowerReturn(SDValue Chain,
CallingConv::ID CallConv, bool isVarArg, CallingConv::ID CallConv, bool isVarArg,
const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<ISD::OutputArg> &Outs,
DebugLoc dl, SelectionDAG &DAG); DebugLoc dl, SelectionDAG &DAG) const;
SDValue SDValue
LowerFormalArguments_Darwin(SDValue Chain, LowerFormalArguments_Darwin(SDValue Chain,
CallingConv::ID CallConv, bool isVarArg, CallingConv::ID CallConv, bool isVarArg,
const SmallVectorImpl<ISD::InputArg> &Ins, const SmallVectorImpl<ISD::InputArg> &Ins,
DebugLoc dl, SelectionDAG &DAG, DebugLoc dl, SelectionDAG &DAG,
SmallVectorImpl<SDValue> &InVals); SmallVectorImpl<SDValue> &InVals) const;
SDValue SDValue
LowerFormalArguments_SVR4(SDValue Chain, LowerFormalArguments_SVR4(SDValue Chain,
CallingConv::ID CallConv, bool isVarArg, CallingConv::ID CallConv, bool isVarArg,
const SmallVectorImpl<ISD::InputArg> &Ins, const SmallVectorImpl<ISD::InputArg> &Ins,
DebugLoc dl, SelectionDAG &DAG, DebugLoc dl, SelectionDAG &DAG,
SmallVectorImpl<SDValue> &InVals); SmallVectorImpl<SDValue> &InVals) const;
SDValue SDValue
LowerCall_Darwin(SDValue Chain, SDValue Callee, LowerCall_Darwin(SDValue Chain, SDValue Callee,
@ -466,14 +466,14 @@ namespace llvm {
const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<ISD::OutputArg> &Outs,
const SmallVectorImpl<ISD::InputArg> &Ins, const SmallVectorImpl<ISD::InputArg> &Ins,
DebugLoc dl, SelectionDAG &DAG, DebugLoc dl, SelectionDAG &DAG,
SmallVectorImpl<SDValue> &InVals); SmallVectorImpl<SDValue> &InVals) const;
SDValue SDValue
LowerCall_SVR4(SDValue Chain, SDValue Callee, LowerCall_SVR4(SDValue Chain, SDValue Callee,
CallingConv::ID CallConv, bool isVarArg, bool isTailCall, CallingConv::ID CallConv, bool isVarArg, bool isTailCall,
const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<ISD::OutputArg> &Outs,
const SmallVectorImpl<ISD::InputArg> &Ins, const SmallVectorImpl<ISD::InputArg> &Ins,
DebugLoc dl, SelectionDAG &DAG, DebugLoc dl, SelectionDAG &DAG,
SmallVectorImpl<SDValue> &InVals); SmallVectorImpl<SDValue> &InVals) const;
}; };
} }

4
llvm/lib/Target/PowerPC/PPCTargetMachine.h
View File

@ -44,8 +44,8 @@ public:
virtual const PPCInstrInfo *getInstrInfo() const { return &InstrInfo; } virtual const PPCInstrInfo *getInstrInfo() const { return &InstrInfo; }
virtual const PPCFrameInfo *getFrameInfo() const { return &FrameInfo; } virtual const PPCFrameInfo *getFrameInfo() const { return &FrameInfo; }
virtual PPCJITInfo *getJITInfo() { return &JITInfo; } virtual PPCJITInfo *getJITInfo() { return &JITInfo; }
virtual PPCTargetLowering *getTargetLowering() const { virtual const PPCTargetLowering *getTargetLowering() const {
return const_cast<PPCTargetLowering*>(&TLInfo); return &TLInfo;
} }
virtual const PPCRegisterInfo *getRegisterInfo() const { virtual const PPCRegisterInfo *getRegisterInfo() const {
return &InstrInfo.getRegisterInfo(); return &InstrInfo.getRegisterInfo();

1
llvm/lib/Target/Sparc/SparcISelDAGToDAG.cpp
View File

@ -11,7 +11,6 @@
// //
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
#include "SparcISelLowering.h"
#include "SparcTargetMachine.h" #include "SparcTargetMachine.h"
#include "llvm/Intrinsics.h" #include "llvm/Intrinsics.h"
#include "llvm/CodeGen/SelectionDAGISel.h" #include "llvm/CodeGen/SelectionDAGISel.h"

15
llvm/lib/Target/Sparc/SparcISelLowering.cpp
View File

@ -38,7 +38,7 @@ SDValue
SparcTargetLowering::LowerReturn(SDValue Chain, SparcTargetLowering::LowerReturn(SDValue Chain,
CallingConv::ID CallConv, bool isVarArg, CallingConv::ID CallConv, bool isVarArg,
const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<ISD::OutputArg> &Outs,
DebugLoc dl, SelectionDAG &DAG) { DebugLoc dl, SelectionDAG &DAG) const {
// CCValAssign - represent the assignment of the return value to locations. // CCValAssign - represent the assignment of the return value to locations.
SmallVector<CCValAssign, 16> RVLocs; SmallVector<CCValAssign, 16> RVLocs;
@ -86,7 +86,8 @@ SparcTargetLowering::LowerFormalArguments(SDValue Chain,
const SmallVectorImpl<ISD::InputArg> const SmallVectorImpl<ISD::InputArg>
&Ins, &Ins,
DebugLoc dl, SelectionDAG &DAG, DebugLoc dl, SelectionDAG &DAG,
SmallVectorImpl<SDValue> &InVals) { SmallVectorImpl<SDValue> &InVals)
const {
MachineFunction &MF = DAG.getMachineFunction(); MachineFunction &MF = DAG.getMachineFunction();
MachineRegisterInfo &RegInfo = MF.getRegInfo(); MachineRegisterInfo &RegInfo = MF.getRegInfo();
@ -263,7 +264,7 @@ SparcTargetLowering::LowerCall(SDValue Chain, SDValue Callee,
const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<ISD::OutputArg> &Outs,
const SmallVectorImpl<ISD::InputArg> &Ins, const SmallVectorImpl<ISD::InputArg> &Ins,
DebugLoc dl, SelectionDAG &DAG, DebugLoc dl, SelectionDAG &DAG,
SmallVectorImpl<SDValue> &InVals) { SmallVectorImpl<SDValue> &InVals) const {
// Sparc target does not yet support tail call optimization. // Sparc target does not yet support tail call optimization.
isTailCall = false; isTailCall = false;
@ -754,7 +755,7 @@ static void LookThroughSetCC(SDValue &LHS, SDValue &RHS,
} }
SDValue SparcTargetLowering::LowerGlobalAddress(SDValue Op, SDValue SparcTargetLowering::LowerGlobalAddress(SDValue Op,
SelectionDAG &DAG) { SelectionDAG &DAG) const {
const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal(); const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
// FIXME there isn't really any debug info here // FIXME there isn't really any debug info here
DebugLoc dl = Op.getDebugLoc(); DebugLoc dl = Op.getDebugLoc();
@ -775,7 +776,7 @@ SDValue SparcTargetLowering::LowerGlobalAddress(SDValue Op,
} }
SDValue SparcTargetLowering::LowerConstantPool(SDValue Op, SDValue SparcTargetLowering::LowerConstantPool(SDValue Op,
SelectionDAG &DAG) { SelectionDAG &DAG) const {
ConstantPoolSDNode *N = cast<ConstantPoolSDNode>(Op); ConstantPoolSDNode *N = cast<ConstantPoolSDNode>(Op);
// FIXME there isn't really any debug info here // FIXME there isn't really any debug info here
DebugLoc dl = Op.getDebugLoc(); DebugLoc dl = Op.getDebugLoc();
@ -875,7 +876,7 @@ static SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) {
} }
static SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG, static SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG,
SparcTargetLowering &TLI) { const SparcTargetLowering &TLI) {
MachineFunction &MF = DAG.getMachineFunction(); MachineFunction &MF = DAG.getMachineFunction();
SparcMachineFunctionInfo *FuncInfo = MF.getInfo<SparcMachineFunctionInfo>(); SparcMachineFunctionInfo *FuncInfo = MF.getInfo<SparcMachineFunctionInfo>();
@ -945,7 +946,7 @@ static SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) {
SDValue SparcTargetLowering:: SDValue SparcTargetLowering::
LowerOperation(SDValue Op, SelectionDAG &DAG) { LowerOperation(SDValue Op, SelectionDAG &DAG) const {
switch (Op.getOpcode()) { switch (Op.getOpcode()) {
default: llvm_unreachable("Should not custom lower this!"); default: llvm_unreachable("Should not custom lower this!");
// Frame & Return address. Currently unimplemented // Frame & Return address. Currently unimplemented

12
llvm/lib/Target/Sparc/SparcISelLowering.h
View File

@ -43,7 +43,7 @@ namespace llvm {
class SparcTargetLowering : public TargetLowering { class SparcTargetLowering : public TargetLowering {
public: public:
SparcTargetLowering(TargetMachine &TM); SparcTargetLowering(TargetMachine &TM);
virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG); virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
/// computeMaskedBitsForTargetNode - Determine which of the bits specified /// computeMaskedBitsForTargetNode - Determine which of the bits specified
/// in Mask are known to be either zero or one and return them in the /// in Mask are known to be either zero or one and return them in the
@ -79,7 +79,7 @@ namespace llvm {
bool isVarArg, bool isVarArg,
const SmallVectorImpl<ISD::InputArg> &Ins, const SmallVectorImpl<ISD::InputArg> &Ins,
DebugLoc dl, SelectionDAG &DAG, DebugLoc dl, SelectionDAG &DAG,
SmallVectorImpl<SDValue> &InVals); SmallVectorImpl<SDValue> &InVals) const;
virtual SDValue virtual SDValue
LowerCall(SDValue Chain, SDValue Callee, LowerCall(SDValue Chain, SDValue Callee,
@ -88,16 +88,16 @@ namespace llvm {
const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<ISD::OutputArg> &Outs,
const SmallVectorImpl<ISD::InputArg> &Ins, const SmallVectorImpl<ISD::InputArg> &Ins,
DebugLoc dl, SelectionDAG &DAG, DebugLoc dl, SelectionDAG &DAG,
SmallVectorImpl<SDValue> &InVals); SmallVectorImpl<SDValue> &InVals) const;
virtual SDValue virtual SDValue
LowerReturn(SDValue Chain, LowerReturn(SDValue Chain,
CallingConv::ID CallConv, bool isVarArg, CallingConv::ID CallConv, bool isVarArg,
const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<ISD::OutputArg> &Outs,
DebugLoc dl, SelectionDAG &DAG); DebugLoc dl, SelectionDAG &DAG) const;
SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG); SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG); SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
}; };
} // end namespace llvm } // end namespace llvm

4
llvm/lib/Target/Sparc/SparcTargetMachine.h
View File

@ -39,8 +39,8 @@ public:
virtual const SparcRegisterInfo *getRegisterInfo() const { virtual const SparcRegisterInfo *getRegisterInfo() const {
return &InstrInfo.getRegisterInfo(); return &InstrInfo.getRegisterInfo();
} }
virtual SparcTargetLowering* getTargetLowering() const { virtual const SparcTargetLowering* getTargetLowering() const {
return const_cast<SparcTargetLowering*>(&TLInfo); return &TLInfo;
} }
virtual const TargetData *getTargetData() const { return &DataLayout; } virtual const TargetData *getTargetData() const { return &DataLayout; }

5
llvm/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp
View File

@ -12,7 +12,6 @@
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
#include "SystemZ.h" #include "SystemZ.h"
#include "SystemZISelLowering.h"
#include "SystemZTargetMachine.h" #include "SystemZTargetMachine.h"
#include "llvm/DerivedTypes.h" #include "llvm/DerivedTypes.h"
#include "llvm/Function.h" #include "llvm/Function.h"
@ -85,7 +84,7 @@ namespace {
/// ///
namespace { namespace {
class SystemZDAGToDAGISel : public SelectionDAGISel { class SystemZDAGToDAGISel : public SelectionDAGISel {
SystemZTargetLowering &Lowering; const SystemZTargetLowering &Lowering;
const SystemZSubtarget &Subtarget; const SystemZSubtarget &Subtarget;
void getAddressOperandsRI(const SystemZRRIAddressMode &AM, void getAddressOperandsRI(const SystemZRRIAddressMode &AM,
@ -588,7 +587,7 @@ bool SystemZDAGToDAGISel::SelectLAAddr(SDNode *Op, SDValue Addr,
bool SystemZDAGToDAGISel::TryFoldLoad(SDNode *P, SDValue N, bool SystemZDAGToDAGISel::TryFoldLoad(SDNode *P, SDValue N,
SDValue &Base, SDValue &Disp, SDValue &Index) { SDValue &Base, SDValue &Disp, SDValue &Index) {
if (ISD::isNON_EXTLoad(N.getNode()) && if (ISD::isNON_EXTLoad(N.getNode()) &&
IsLegalToFold(N, P, P)) IsLegalToFold(N, P, P, OptLevel))
return SelectAddrRRI20(P, N.getOperand(1), Base, Disp, Index); return SelectAddrRRI20(P, N.getOperand(1), Base, Disp, Index);
return false; return false;
} }

30
llvm/lib/Target/SystemZ/SystemZISelLowering.cpp
View File

@ -158,7 +158,8 @@ SystemZTargetLowering::SystemZTargetLowering(SystemZTargetMachine &tm) :
setTruncStoreAction(MVT::f64, MVT::f32, Expand); setTruncStoreAction(MVT::f64, MVT::f32, Expand);
} }
SDValue SystemZTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) { SDValue SystemZTargetLowering::LowerOperation(SDValue Op,
SelectionDAG &DAG) const {
switch (Op.getOpcode()) { switch (Op.getOpcode()) {
case ISD::BR_CC: return LowerBR_CC(Op, DAG); case ISD::BR_CC: return LowerBR_CC(Op, DAG);
case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG); case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG);
@ -236,7 +237,8 @@ SystemZTargetLowering::LowerFormalArguments(SDValue Chain,
&Ins, &Ins,
DebugLoc dl, DebugLoc dl,
SelectionDAG &DAG, SelectionDAG &DAG,
SmallVectorImpl<SDValue> &InVals) { SmallVectorImpl<SDValue> &InVals)
const {
switch (CallConv) { switch (CallConv) {
default: default:
@ -254,7 +256,7 @@ SystemZTargetLowering::LowerCall(SDValue Chain, SDValue Callee,
const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<ISD::OutputArg> &Outs,
const SmallVectorImpl<ISD::InputArg> &Ins, const SmallVectorImpl<ISD::InputArg> &Ins,
DebugLoc dl, SelectionDAG &DAG, DebugLoc dl, SelectionDAG &DAG,
SmallVectorImpl<SDValue> &InVals) { SmallVectorImpl<SDValue> &InVals) const {
// SystemZ target does not yet support tail call optimization. // SystemZ target does not yet support tail call optimization.
isTailCall = false; isTailCall = false;
@ -280,7 +282,8 @@ SystemZTargetLowering::LowerCCCArguments(SDValue Chain,
&Ins, &Ins,
DebugLoc dl, DebugLoc dl,
SelectionDAG &DAG, SelectionDAG &DAG,
SmallVectorImpl<SDValue> &InVals) { SmallVectorImpl<SDValue> &InVals)
const {
MachineFunction &MF = DAG.getMachineFunction(); MachineFunction &MF = DAG.getMachineFunction();
MachineFrameInfo *MFI = MF.getFrameInfo(); MachineFrameInfo *MFI = MF.getFrameInfo();
@ -371,7 +374,7 @@ SystemZTargetLowering::LowerCCCCallTo(SDValue Chain, SDValue Callee,
&Outs, &Outs,
const SmallVectorImpl<ISD::InputArg> &Ins, const SmallVectorImpl<ISD::InputArg> &Ins,
DebugLoc dl, SelectionDAG &DAG, DebugLoc dl, SelectionDAG &DAG,
SmallVectorImpl<SDValue> &InVals) { SmallVectorImpl<SDValue> &InVals) const {
MachineFunction &MF = DAG.getMachineFunction(); MachineFunction &MF = DAG.getMachineFunction();
@ -505,7 +508,7 @@ SystemZTargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
const SmallVectorImpl<ISD::InputArg> const SmallVectorImpl<ISD::InputArg>
&Ins, &Ins,
DebugLoc dl, SelectionDAG &DAG, DebugLoc dl, SelectionDAG &DAG,
SmallVectorImpl<SDValue> &InVals) { SmallVectorImpl<SDValue> &InVals) const {
// Assign locations to each value returned by this call. // Assign locations to each value returned by this call.
SmallVector<CCValAssign, 16> RVLocs; SmallVector<CCValAssign, 16> RVLocs;
@ -547,7 +550,7 @@ SDValue
SystemZTargetLowering::LowerReturn(SDValue Chain, SystemZTargetLowering::LowerReturn(SDValue Chain,
CallingConv::ID CallConv, bool isVarArg, CallingConv::ID CallConv, bool isVarArg,
const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<ISD::OutputArg> &Outs,
DebugLoc dl, SelectionDAG &DAG) { DebugLoc dl, SelectionDAG &DAG) const {
// CCValAssign - represent the assignment of the return value to a location // CCValAssign - represent the assignment of the return value to a location
SmallVector<CCValAssign, 16> RVLocs; SmallVector<CCValAssign, 16> RVLocs;
@ -600,7 +603,7 @@ SystemZTargetLowering::LowerReturn(SDValue Chain,
SDValue SystemZTargetLowering::EmitCmp(SDValue LHS, SDValue RHS, SDValue SystemZTargetLowering::EmitCmp(SDValue LHS, SDValue RHS,
ISD::CondCode CC, SDValue &SystemZCC, ISD::CondCode CC, SDValue &SystemZCC,
SelectionDAG &DAG) { SelectionDAG &DAG) const {
// FIXME: Emit a test if RHS is zero // FIXME: Emit a test if RHS is zero
bool isUnsigned = false; bool isUnsigned = false;
@ -678,7 +681,7 @@ SDValue SystemZTargetLowering::EmitCmp(SDValue LHS, SDValue RHS,
} }
SDValue SystemZTargetLowering::LowerBR_CC(SDValue Op, SelectionDAG &DAG) { SDValue SystemZTargetLowering::LowerBR_CC(SDValue Op, SelectionDAG &DAG) const {
SDValue Chain = Op.getOperand(0); SDValue Chain = Op.getOperand(0);
ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get(); ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
SDValue LHS = Op.getOperand(2); SDValue LHS = Op.getOperand(2);
@ -692,7 +695,8 @@ SDValue SystemZTargetLowering::LowerBR_CC(SDValue Op, SelectionDAG &DAG) {
Chain, Dest, SystemZCC, Flag); Chain, Dest, SystemZCC, Flag);
} }
SDValue SystemZTargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) { SDValue SystemZTargetLowering::LowerSELECT_CC(SDValue Op,
SelectionDAG &DAG) const {
SDValue LHS = Op.getOperand(0); SDValue LHS = Op.getOperand(0);
SDValue RHS = Op.getOperand(1); SDValue RHS = Op.getOperand(1);
SDValue TrueV = Op.getOperand(2); SDValue TrueV = Op.getOperand(2);
@ -714,7 +718,7 @@ SDValue SystemZTargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) {
} }
SDValue SystemZTargetLowering::LowerGlobalAddress(SDValue Op, SDValue SystemZTargetLowering::LowerGlobalAddress(SDValue Op,
SelectionDAG &DAG) { SelectionDAG &DAG) const {
DebugLoc dl = Op.getDebugLoc(); DebugLoc dl = Op.getDebugLoc();
const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal(); const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset(); int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset();
@ -753,7 +757,7 @@ SDValue SystemZTargetLowering::LowerGlobalAddress(SDValue Op,
// FIXME: PIC here // FIXME: PIC here
SDValue SystemZTargetLowering::LowerJumpTable(SDValue Op, SDValue SystemZTargetLowering::LowerJumpTable(SDValue Op,
SelectionDAG &DAG) { SelectionDAG &DAG) const {
DebugLoc dl = Op.getDebugLoc(); DebugLoc dl = Op.getDebugLoc();
JumpTableSDNode *JT = cast<JumpTableSDNode>(Op); JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
SDValue Result = DAG.getTargetJumpTable(JT->getIndex(), getPointerTy()); SDValue Result = DAG.getTargetJumpTable(JT->getIndex(), getPointerTy());
@ -765,7 +769,7 @@ SDValue SystemZTargetLowering::LowerJumpTable(SDValue Op,
// FIXME: PIC here // FIXME: PIC here
// FIXME: This is just dirty hack. We need to lower cpool properly // FIXME: This is just dirty hack. We need to lower cpool properly
SDValue SystemZTargetLowering::LowerConstantPool(SDValue Op, SDValue SystemZTargetLowering::LowerConstantPool(SDValue Op,
SelectionDAG &DAG) { SelectionDAG &DAG) const {
DebugLoc dl = Op.getDebugLoc(); DebugLoc dl = Op.getDebugLoc();
ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op); ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);

26
llvm/lib/Target/SystemZ/SystemZISelLowering.h
View File

@ -58,7 +58,7 @@ namespace llvm {
explicit SystemZTargetLowering(SystemZTargetMachine &TM); explicit SystemZTargetLowering(SystemZTargetMachine &TM);
/// LowerOperation - Provide custom lowering hooks for some operations. /// LowerOperation - Provide custom lowering hooks for some operations.
virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG); virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
/// getTargetNodeName - This method returns the name of a target specific /// getTargetNodeName - This method returns the name of a target specific
/// DAG node. /// DAG node.
@ -74,15 +74,15 @@ namespace llvm {
TargetLowering::ConstraintType TargetLowering::ConstraintType
getConstraintType(const std::string &Constraint) const; getConstraintType(const std::string &Constraint) const;
SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG); SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG); SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG); SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG); SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG); SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
SDValue EmitCmp(SDValue LHS, SDValue RHS, SDValue EmitCmp(SDValue LHS, SDValue RHS,
ISD::CondCode CC, SDValue &SystemZCC, ISD::CondCode CC, SDValue &SystemZCC,
SelectionDAG &DAG); SelectionDAG &DAG) const;
MachineBasicBlock* EmitInstrWithCustomInserter(MachineInstr *MI, MachineBasicBlock* EmitInstrWithCustomInserter(MachineInstr *MI,
@ -101,7 +101,7 @@ namespace llvm {
const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<ISD::OutputArg> &Outs,
const SmallVectorImpl<ISD::InputArg> &Ins, const SmallVectorImpl<ISD::InputArg> &Ins,
DebugLoc dl, SelectionDAG &DAG, DebugLoc dl, SelectionDAG &DAG,
SmallVectorImpl<SDValue> &InVals); SmallVectorImpl<SDValue> &InVals) const;
SDValue LowerCCCArguments(SDValue Chain, SDValue LowerCCCArguments(SDValue Chain,
CallingConv::ID CallConv, CallingConv::ID CallConv,
@ -109,33 +109,33 @@ namespace llvm {
const SmallVectorImpl<ISD::InputArg> &Ins, const SmallVectorImpl<ISD::InputArg> &Ins,
DebugLoc dl, DebugLoc dl,
SelectionDAG &DAG, SelectionDAG &DAG,
SmallVectorImpl<SDValue> &InVals); SmallVectorImpl<SDValue> &InVals) const;
SDValue LowerCallResult(SDValue Chain, SDValue InFlag, SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
CallingConv::ID CallConv, bool isVarArg, CallingConv::ID CallConv, bool isVarArg,
const SmallVectorImpl<ISD::InputArg> &Ins, const SmallVectorImpl<ISD::InputArg> &Ins,
DebugLoc dl, SelectionDAG &DAG, DebugLoc dl, SelectionDAG &DAG,
SmallVectorImpl<SDValue> &InVals); SmallVectorImpl<SDValue> &InVals) const;
virtual SDValue virtual SDValue
LowerFormalArguments(SDValue Chain, LowerFormalArguments(SDValue Chain,
CallingConv::ID CallConv, bool isVarArg, CallingConv::ID CallConv, bool isVarArg,
const SmallVectorImpl<ISD::InputArg> &Ins, const SmallVectorImpl<ISD::InputArg> &Ins,
DebugLoc dl, SelectionDAG &DAG, DebugLoc dl, SelectionDAG &DAG,
SmallVectorImpl<SDValue> &InVals); SmallVectorImpl<SDValue> &InVals) const;
virtual SDValue virtual SDValue
LowerCall(SDValue Chain, SDValue Callee, LowerCall(SDValue Chain, SDValue Callee,
CallingConv::ID CallConv, bool isVarArg, bool &isTailCall, CallingConv::ID CallConv, bool isVarArg, bool &isTailCall,
const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<ISD::OutputArg> &Outs,
const SmallVectorImpl<ISD::InputArg> &Ins, const SmallVectorImpl<ISD::InputArg> &Ins,
DebugLoc dl, SelectionDAG &DAG, DebugLoc dl, SelectionDAG &DAG,
SmallVectorImpl<SDValue> &InVals); SmallVectorImpl<SDValue> &InVals) const;
virtual SDValue virtual SDValue
LowerReturn(SDValue Chain, LowerReturn(SDValue Chain,
CallingConv::ID CallConv, bool isVarArg, CallingConv::ID CallConv, bool isVarArg,
const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<ISD::OutputArg> &Outs,
DebugLoc dl, SelectionDAG &DAG); DebugLoc dl, SelectionDAG &DAG) const;
const SystemZSubtarget &Subtarget; const SystemZSubtarget &Subtarget;
const SystemZTargetMachine &TM; const SystemZTargetMachine &TM;

4
llvm/lib/Target/SystemZ/SystemZTargetMachine.h
View File

@ -49,8 +49,8 @@ public:
return &InstrInfo.getRegisterInfo(); return &InstrInfo.getRegisterInfo();
} }
virtual SystemZTargetLowering *getTargetLowering() const { virtual const SystemZTargetLowering *getTargetLowering() const {
return const_cast<SystemZTargetLowering*>(&TLInfo); return &TLInfo;
} }
virtual bool addInstSelector(PassManagerBase &PM, CodeGenOpt::Level OptLevel); virtual bool addInstSelector(PassManagerBase &PM, CodeGenOpt::Level OptLevel);

1
llvm/lib/Target/X86/X86FastISel.cpp
View File

@ -15,7 +15,6 @@
#include "X86.h" #include "X86.h"
#include "X86InstrBuilder.h" #include "X86InstrBuilder.h"
#include "X86ISelLowering.h"
#include "X86RegisterInfo.h" #include "X86RegisterInfo.h"
#include "X86Subtarget.h" #include "X86Subtarget.h"
#include "X86TargetMachine.h" #include "X86TargetMachine.h"

9
llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
View File

@ -15,7 +15,6 @@
#define DEBUG_TYPE "x86-isel" #define DEBUG_TYPE "x86-isel"
#include "X86.h" #include "X86.h"
#include "X86InstrBuilder.h" #include "X86InstrBuilder.h"
#include "X86ISelLowering.h"
#include "X86MachineFunctionInfo.h" #include "X86MachineFunctionInfo.h"
#include "X86RegisterInfo.h" #include "X86RegisterInfo.h"
#include "X86Subtarget.h" #include "X86Subtarget.h"
@ -161,7 +160,7 @@ namespace {
class X86DAGToDAGISel : public SelectionDAGISel { class X86DAGToDAGISel : public SelectionDAGISel {
/// X86Lowering - This object fully describes how to lower LLVM code to an /// X86Lowering - This object fully describes how to lower LLVM code to an
/// X86-specific SelectionDAG. /// X86-specific SelectionDAG.
X86TargetLowering &X86Lowering; const X86TargetLowering &X86Lowering;
/// Subtarget - Keep a pointer to the X86Subtarget around so that we can /// Subtarget - Keep a pointer to the X86Subtarget around so that we can
/// make the right decision when generating code for different targets. /// make the right decision when generating code for different targets.
@ -1184,7 +1183,7 @@ bool X86DAGToDAGISel::SelectScalarSSELoad(SDNode *Root,
if (ISD::isNON_EXTLoad(PatternNodeWithChain.getNode()) && if (ISD::isNON_EXTLoad(PatternNodeWithChain.getNode()) &&
PatternNodeWithChain.hasOneUse() && PatternNodeWithChain.hasOneUse() &&
IsProfitableToFold(N.getOperand(0), N.getNode(), Root) && IsProfitableToFold(N.getOperand(0), N.getNode(), Root) &&
IsLegalToFold(N.getOperand(0), N.getNode(), Root)) { IsLegalToFold(N.getOperand(0), N.getNode(), Root, OptLevel)) {
LoadSDNode *LD = cast<LoadSDNode>(PatternNodeWithChain); LoadSDNode *LD = cast<LoadSDNode>(PatternNodeWithChain);
if (!SelectAddr(Root, LD->getBasePtr(), Base, Scale, Index, Disp,Segment)) if (!SelectAddr(Root, LD->getBasePtr(), Base, Scale, Index, Disp,Segment))
return false; return false;
@ -1201,7 +1200,7 @@ bool X86DAGToDAGISel::SelectScalarSSELoad(SDNode *Root,
ISD::isNON_EXTLoad(N.getOperand(0).getOperand(0).getNode()) && ISD::isNON_EXTLoad(N.getOperand(0).getOperand(0).getNode()) &&
N.getOperand(0).getOperand(0).hasOneUse() && N.getOperand(0).getOperand(0).hasOneUse() &&
IsProfitableToFold(N.getOperand(0), N.getNode(), Root) && IsProfitableToFold(N.getOperand(0), N.getNode(), Root) &&
IsLegalToFold(N.getOperand(0), N.getNode(), Root)) { IsLegalToFold(N.getOperand(0), N.getNode(), Root, OptLevel)) {
// Okay, this is a zero extending load. Fold it. // Okay, this is a zero extending load. Fold it.
LoadSDNode *LD = cast<LoadSDNode>(N.getOperand(0).getOperand(0)); LoadSDNode *LD = cast<LoadSDNode>(N.getOperand(0).getOperand(0));
if (!SelectAddr(Root, LD->getBasePtr(), Base, Scale, Index, Disp, Segment)) if (!SelectAddr(Root, LD->getBasePtr(), Base, Scale, Index, Disp, Segment))
@ -1308,7 +1307,7 @@ bool X86DAGToDAGISel::TryFoldLoad(SDNode *P, SDValue N,
SDValue &Segment) { SDValue &Segment) {
if (!ISD::isNON_EXTLoad(N.getNode()) || if (!ISD::isNON_EXTLoad(N.getNode()) ||
!IsProfitableToFold(N, P, P) || !IsProfitableToFold(N, P, P) ||
!IsLegalToFold(N, P, P)) !IsLegalToFold(N, P, P, OptLevel))
return false; return false;
return SelectAddr(P, N.getOperand(1), Base, Scale, Index, Disp, Segment); return SelectAddr(P, N.getOperand(1), Base, Scale, Index, Disp, Segment);

175
llvm/lib/Target/X86/X86ISelLowering.cpp
View File

@ -1192,7 +1192,7 @@ bool
X86TargetLowering::CanLowerReturn(CallingConv::ID CallConv, bool isVarArg, X86TargetLowering::CanLowerReturn(CallingConv::ID CallConv, bool isVarArg,
const SmallVectorImpl<EVT> &OutTys, const SmallVectorImpl<EVT> &OutTys,
const SmallVectorImpl<ISD::ArgFlagsTy> &ArgsFlags, const SmallVectorImpl<ISD::ArgFlagsTy> &ArgsFlags,
SelectionDAG &DAG) { SelectionDAG &DAG) const {
SmallVector<CCValAssign, 16> RVLocs; SmallVector<CCValAssign, 16> RVLocs;
CCState CCInfo(CallConv, isVarArg, getTargetMachine(), CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
RVLocs, *DAG.getContext()); RVLocs, *DAG.getContext());
@ -1203,7 +1203,7 @@ SDValue
X86TargetLowering::LowerReturn(SDValue Chain, X86TargetLowering::LowerReturn(SDValue Chain,
CallingConv::ID CallConv, bool isVarArg, CallingConv::ID CallConv, bool isVarArg,
const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<ISD::OutputArg> &Outs,
DebugLoc dl, SelectionDAG &DAG) { DebugLoc dl, SelectionDAG &DAG) const {
MachineFunction &MF = DAG.getMachineFunction(); MachineFunction &MF = DAG.getMachineFunction();
X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>(); X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
@ -1300,7 +1300,7 @@ X86TargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
CallingConv::ID CallConv, bool isVarArg, CallingConv::ID CallConv, bool isVarArg,
const SmallVectorImpl<ISD::InputArg> &Ins, const SmallVectorImpl<ISD::InputArg> &Ins,
DebugLoc dl, SelectionDAG &DAG, DebugLoc dl, SelectionDAG &DAG,
SmallVectorImpl<SDValue> &InVals) { SmallVectorImpl<SDValue> &InVals) const {
// Assign locations to each value returned by this call. // Assign locations to each value returned by this call.
SmallVector<CCValAssign, 16> RVLocs; SmallVector<CCValAssign, 16> RVLocs;
@ -1397,7 +1397,8 @@ ArgsAreStructReturn(const SmallVectorImpl<ISD::InputArg> &Ins) {
/// IsCalleePop - Determines whether the callee is required to pop its /// IsCalleePop - Determines whether the callee is required to pop its
/// own arguments. Callee pop is necessary to support tail calls. /// own arguments. Callee pop is necessary to support tail calls.
bool X86TargetLowering::IsCalleePop(bool IsVarArg, CallingConv::ID CallingConv){ bool X86TargetLowering::IsCalleePop(bool IsVarArg,
CallingConv::ID CallingConv) const {
if (IsVarArg) if (IsVarArg)
return false; return false;
@ -1470,7 +1471,7 @@ X86TargetLowering::LowerMemArgument(SDValue Chain,
DebugLoc dl, SelectionDAG &DAG, DebugLoc dl, SelectionDAG &DAG,
const CCValAssign &VA, const CCValAssign &VA,
MachineFrameInfo *MFI, MachineFrameInfo *MFI,
unsigned i) { unsigned i) const {
// Create the nodes corresponding to a load from this parameter slot. // Create the nodes corresponding to a load from this parameter slot.
ISD::ArgFlagsTy Flags = Ins[i].Flags; ISD::ArgFlagsTy Flags = Ins[i].Flags;
bool AlwaysUseMutable = FuncIsMadeTailCallSafe(CallConv); bool AlwaysUseMutable = FuncIsMadeTailCallSafe(CallConv);
@ -1509,7 +1510,8 @@ X86TargetLowering::LowerFormalArguments(SDValue Chain,
const SmallVectorImpl<ISD::InputArg> &Ins, const SmallVectorImpl<ISD::InputArg> &Ins,
DebugLoc dl, DebugLoc dl,
SelectionDAG &DAG, SelectionDAG &DAG,
SmallVectorImpl<SDValue> &InVals) { SmallVectorImpl<SDValue> &InVals)
const {
MachineFunction &MF = DAG.getMachineFunction(); MachineFunction &MF = DAG.getMachineFunction();
X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>(); X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
@ -1752,7 +1754,7 @@ X86TargetLowering::LowerMemOpCallTo(SDValue Chain,
SDValue StackPtr, SDValue Arg, SDValue StackPtr, SDValue Arg,
DebugLoc dl, SelectionDAG &DAG, DebugLoc dl, SelectionDAG &DAG,
const CCValAssign &VA, const CCValAssign &VA,
ISD::ArgFlagsTy Flags) { ISD::ArgFlagsTy Flags) const {
const unsigned FirstStackArgOffset = (Subtarget->isTargetWin64() ? 32 : 0); const unsigned FirstStackArgOffset = (Subtarget->isTargetWin64() ? 32 : 0);
unsigned LocMemOffset = FirstStackArgOffset + VA.getLocMemOffset(); unsigned LocMemOffset = FirstStackArgOffset + VA.getLocMemOffset();
SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset); SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
@ -1771,7 +1773,7 @@ SDValue
X86TargetLowering::EmitTailCallLoadRetAddr(SelectionDAG &DAG, X86TargetLowering::EmitTailCallLoadRetAddr(SelectionDAG &DAG,
SDValue &OutRetAddr, SDValue Chain, SDValue &OutRetAddr, SDValue Chain,
bool IsTailCall, bool Is64Bit, bool IsTailCall, bool Is64Bit,
int FPDiff, DebugLoc dl) { int FPDiff, DebugLoc dl) const {
// Adjust the Return address stack slot. // Adjust the Return address stack slot.
EVT VT = getPointerTy(); EVT VT = getPointerTy();
OutRetAddr = getReturnAddressFrameIndex(DAG); OutRetAddr = getReturnAddressFrameIndex(DAG);
@ -1808,7 +1810,7 @@ X86TargetLowering::LowerCall(SDValue Chain, SDValue Callee,
const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<ISD::OutputArg> &Outs,
const SmallVectorImpl<ISD::InputArg> &Ins, const SmallVectorImpl<ISD::InputArg> &Ins,
DebugLoc dl, SelectionDAG &DAG, DebugLoc dl, SelectionDAG &DAG,
SmallVectorImpl<SDValue> &InVals) { SmallVectorImpl<SDValue> &InVals) const {
MachineFunction &MF = DAG.getMachineFunction(); MachineFunction &MF = DAG.getMachineFunction();
bool Is64Bit = Subtarget->is64Bit(); bool Is64Bit = Subtarget->is64Bit();
bool IsStructRet = CallIsStructReturn(Outs); bool IsStructRet = CallIsStructReturn(Outs);
@ -2237,8 +2239,9 @@ X86TargetLowering::LowerCall(SDValue Chain, SDValue Callee,
/// GetAlignedArgumentStackSize - Make the stack size align e.g 16n + 12 aligned /// GetAlignedArgumentStackSize - Make the stack size align e.g 16n + 12 aligned
/// for a 16 byte align requirement. /// for a 16 byte align requirement.
unsigned X86TargetLowering::GetAlignedArgumentStackSize(unsigned StackSize, unsigned
SelectionDAG& DAG) { X86TargetLowering::GetAlignedArgumentStackSize(unsigned StackSize,
SelectionDAG& DAG) const {
MachineFunction &MF = DAG.getMachineFunction(); MachineFunction &MF = DAG.getMachineFunction();
const TargetMachine &TM = MF.getTarget(); const TargetMachine &TM = MF.getTarget();
const TargetFrameInfo &TFI = *TM.getFrameInfo(); const TargetFrameInfo &TFI = *TM.getFrameInfo();
@ -2423,7 +2426,7 @@ X86TargetLowering::createFastISel(MachineFunction &mf,
#ifndef NDEBUG #ifndef NDEBUG
, SmallSet<const Instruction *, 8> &cil , SmallSet<const Instruction *, 8> &cil
#endif #endif
) { ) const {
return X86::createFastISel(mf, vm, bm, am return X86::createFastISel(mf, vm, bm, am
#ifndef NDEBUG #ifndef NDEBUG
, cil , cil
@ -2437,7 +2440,7 @@ X86TargetLowering::createFastISel(MachineFunction &mf,
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
SDValue X86TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) { SDValue X86TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) const {
MachineFunction &MF = DAG.getMachineFunction(); MachineFunction &MF = DAG.getMachineFunction();
X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>(); X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
int ReturnAddrIndex = FuncInfo->getRAIndex(); int ReturnAddrIndex = FuncInfo->getRAIndex();
@ -3498,7 +3501,8 @@ static bool isVectorShift(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
/// ///
static SDValue LowerBuildVectorv16i8(SDValue Op, unsigned NonZeros, static SDValue LowerBuildVectorv16i8(SDValue Op, unsigned NonZeros,
unsigned NumNonZero, unsigned NumZero, unsigned NumNonZero, unsigned NumZero,
SelectionDAG &DAG, TargetLowering &TLI) { SelectionDAG &DAG,
const TargetLowering &TLI) {
if (NumNonZero > 8) if (NumNonZero > 8)
return SDValue(); return SDValue();
@ -3543,8 +3547,9 @@ static SDValue LowerBuildVectorv16i8(SDValue Op, unsigned NonZeros,
/// LowerBuildVectorv8i16 - Custom lower build_vector of v8i16. /// LowerBuildVectorv8i16 - Custom lower build_vector of v8i16.
/// ///
static SDValue LowerBuildVectorv8i16(SDValue Op, unsigned NonZeros, static SDValue LowerBuildVectorv8i16(SDValue Op, unsigned NonZeros,
unsigned NumNonZero, unsigned NumZero, unsigned NumNonZero, unsigned NumZero,
SelectionDAG &DAG, TargetLowering &TLI) { SelectionDAG &DAG,
const TargetLowering &TLI) {
if (NumNonZero > 4) if (NumNonZero > 4)
return SDValue(); return SDValue();
@ -3586,7 +3591,7 @@ static SDValue getVShift(bool isLeft, EVT VT, SDValue SrcOp,
SDValue SDValue
X86TargetLowering::LowerAsSplatVectorLoad(SDValue SrcOp, EVT VT, DebugLoc dl, X86TargetLowering::LowerAsSplatVectorLoad(SDValue SrcOp, EVT VT, DebugLoc dl,
SelectionDAG &DAG) { SelectionDAG &DAG) const {
// Check if the scalar load can be widened into a vector load. And if // Check if the scalar load can be widened into a vector load. And if
// the address is "base + cst" see if the cst can be "absorbed" into // the address is "base + cst" see if the cst can be "absorbed" into
@ -3718,7 +3723,7 @@ static SDValue EltsFromConsecutiveLoads(EVT VT, SmallVectorImpl<SDValue> &Elts,
} }
SDValue SDValue
X86TargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) { X86TargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const {
DebugLoc dl = Op.getDebugLoc(); DebugLoc dl = Op.getDebugLoc();
// All zero's are handled with pxor, all one's are handled with pcmpeqd. // All zero's are handled with pxor, all one's are handled with pcmpeqd.
if (ISD::isBuildVectorAllZeros(Op.getNode()) if (ISD::isBuildVectorAllZeros(Op.getNode())
@ -3984,7 +3989,7 @@ X86TargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) {
} }
SDValue SDValue
X86TargetLowering::LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) { X86TargetLowering::LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) const {
// We support concatenate two MMX registers and place them in a MMX // We support concatenate two MMX registers and place them in a MMX
// register. This is better than doing a stack convert. // register. This is better than doing a stack convert.
DebugLoc dl = Op.getDebugLoc(); DebugLoc dl = Op.getDebugLoc();
@ -4017,7 +4022,8 @@ X86TargetLowering::LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
// 4. [all] mov + pshuflw + pshufhw + N x (pextrw + pinsrw) // 4. [all] mov + pshuflw + pshufhw + N x (pextrw + pinsrw)
static static
SDValue LowerVECTOR_SHUFFLEv8i16(ShuffleVectorSDNode *SVOp, SDValue LowerVECTOR_SHUFFLEv8i16(ShuffleVectorSDNode *SVOp,
SelectionDAG &DAG, X86TargetLowering &TLI) { SelectionDAG &DAG,
const X86TargetLowering &TLI) {
SDValue V1 = SVOp->getOperand(0); SDValue V1 = SVOp->getOperand(0);
SDValue V2 = SVOp->getOperand(1); SDValue V2 = SVOp->getOperand(1);
DebugLoc dl = SVOp->getDebugLoc(); DebugLoc dl = SVOp->getDebugLoc();
@ -4260,7 +4266,8 @@ SDValue LowerVECTOR_SHUFFLEv8i16(ShuffleVectorSDNode *SVOp,
// 3. [all] v8i16 shuffle + N x pextrw + rotate + pinsrw // 3. [all] v8i16 shuffle + N x pextrw + rotate + pinsrw
static static
SDValue LowerVECTOR_SHUFFLEv16i8(ShuffleVectorSDNode *SVOp, SDValue LowerVECTOR_SHUFFLEv16i8(ShuffleVectorSDNode *SVOp,
SelectionDAG &DAG, X86TargetLowering &TLI) { SelectionDAG &DAG,
const X86TargetLowering &TLI) {
SDValue V1 = SVOp->getOperand(0); SDValue V1 = SVOp->getOperand(0);
SDValue V2 = SVOp->getOperand(1); SDValue V2 = SVOp->getOperand(1);
DebugLoc dl = SVOp->getDebugLoc(); DebugLoc dl = SVOp->getDebugLoc();
@ -4406,7 +4413,7 @@ SDValue LowerVECTOR_SHUFFLEv16i8(ShuffleVectorSDNode *SVOp,
static static
SDValue RewriteAsNarrowerShuffle(ShuffleVectorSDNode *SVOp, SDValue RewriteAsNarrowerShuffle(ShuffleVectorSDNode *SVOp,
SelectionDAG &DAG, SelectionDAG &DAG,
TargetLowering &TLI, DebugLoc dl) { const TargetLowering &TLI, DebugLoc dl) {
EVT VT = SVOp->getValueType(0); EVT VT = SVOp->getValueType(0);
SDValue V1 = SVOp->getOperand(0); SDValue V1 = SVOp->getOperand(0);
SDValue V2 = SVOp->getOperand(1); SDValue V2 = SVOp->getOperand(1);
@ -4638,7 +4645,7 @@ LowerVECTOR_SHUFFLE_4wide(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
} }
SDValue SDValue
X86TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) { X86TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const {
ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op); ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
SDValue V1 = Op.getOperand(0); SDValue V1 = Op.getOperand(0);
SDValue V2 = Op.getOperand(1); SDValue V2 = Op.getOperand(1);
@ -4825,7 +4832,7 @@ X86TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) {
SDValue SDValue
X86TargetLowering::LowerEXTRACT_VECTOR_ELT_SSE4(SDValue Op, X86TargetLowering::LowerEXTRACT_VECTOR_ELT_SSE4(SDValue Op,
SelectionDAG &DAG) { SelectionDAG &DAG) const {
EVT VT = Op.getValueType(); EVT VT = Op.getValueType();
DebugLoc dl = Op.getDebugLoc(); DebugLoc dl = Op.getDebugLoc();
if (VT.getSizeInBits() == 8) { if (VT.getSizeInBits() == 8) {
@ -4879,7 +4886,8 @@ X86TargetLowering::LowerEXTRACT_VECTOR_ELT_SSE4(SDValue Op,
SDValue SDValue
X86TargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) { X86TargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op,
SelectionDAG &DAG) const {
if (!isa<ConstantSDNode>(Op.getOperand(1))) if (!isa<ConstantSDNode>(Op.getOperand(1)))
return SDValue(); return SDValue();
@ -4943,7 +4951,8 @@ X86TargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) {
} }
SDValue SDValue
X86TargetLowering::LowerINSERT_VECTOR_ELT_SSE4(SDValue Op, SelectionDAG &DAG){ X86TargetLowering::LowerINSERT_VECTOR_ELT_SSE4(SDValue Op,
SelectionDAG &DAG) const {
EVT VT = Op.getValueType(); EVT VT = Op.getValueType();
EVT EltVT = VT.getVectorElementType(); EVT EltVT = VT.getVectorElementType();
DebugLoc dl = Op.getDebugLoc(); DebugLoc dl = Op.getDebugLoc();
@ -4992,7 +5001,7 @@ X86TargetLowering::LowerINSERT_VECTOR_ELT_SSE4(SDValue Op, SelectionDAG &DAG){
} }
SDValue SDValue
X86TargetLowering::LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) { X86TargetLowering::LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const {
EVT VT = Op.getValueType(); EVT VT = Op.getValueType();
EVT EltVT = VT.getVectorElementType(); EVT EltVT = VT.getVectorElementType();
@ -5021,7 +5030,7 @@ X86TargetLowering::LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) {
} }
SDValue SDValue
X86TargetLowering::LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) { X86TargetLowering::LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) const {
DebugLoc dl = Op.getDebugLoc(); DebugLoc dl = Op.getDebugLoc();
if (Op.getValueType() == MVT::v2f32) if (Op.getValueType() == MVT::v2f32)
return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2f32, return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2f32,
@ -5052,7 +5061,7 @@ X86TargetLowering::LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) {
// be used to form addressing mode. These wrapped nodes will be selected // be used to form addressing mode. These wrapped nodes will be selected
// into MOV32ri. // into MOV32ri.
SDValue SDValue
X86TargetLowering::LowerConstantPool(SDValue Op, SelectionDAG &DAG) { X86TargetLowering::LowerConstantPool(SDValue Op, SelectionDAG &DAG) const {
ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op); ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
// In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
@ -5085,7 +5094,7 @@ X86TargetLowering::LowerConstantPool(SDValue Op, SelectionDAG &DAG) {
return Result; return Result;
} }
SDValue X86TargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) { SDValue X86TargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) const {
JumpTableSDNode *JT = cast<JumpTableSDNode>(Op); JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
// In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
@ -5119,7 +5128,7 @@ SDValue X86TargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) {
} }
SDValue SDValue
X86TargetLowering::LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) { X86TargetLowering::LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) const {
const char *Sym = cast<ExternalSymbolSDNode>(Op)->getSymbol(); const char *Sym = cast<ExternalSymbolSDNode>(Op)->getSymbol();
// In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
@ -5155,7 +5164,7 @@ X86TargetLowering::LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) {
} }
SDValue SDValue
X86TargetLowering::LowerBlockAddress(SDValue Op, SelectionDAG &DAG) { X86TargetLowering::LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const {
// Create the TargetBlockAddressAddress node. // Create the TargetBlockAddressAddress node.
unsigned char OpFlags = unsigned char OpFlags =
Subtarget->ClassifyBlockAddressReference(); Subtarget->ClassifyBlockAddressReference();
@ -5229,7 +5238,7 @@ X86TargetLowering::LowerGlobalAddress(const GlobalValue *GV, DebugLoc dl,
} }
SDValue SDValue
X86TargetLowering::LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) { X86TargetLowering::LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const {
const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal(); const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset(); int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset();
return LowerGlobalAddress(GV, Op.getDebugLoc(), Offset, DAG); return LowerGlobalAddress(GV, Op.getDebugLoc(), Offset, DAG);
@ -5329,7 +5338,7 @@ static SDValue LowerToTLSExecModel(GlobalAddressSDNode *GA, SelectionDAG &DAG,
} }
SDValue SDValue
X86TargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) { X86TargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const {
// TODO: implement the "local dynamic" model // TODO: implement the "local dynamic" model
// TODO: implement the "initial exec"model for pic executables // TODO: implement the "initial exec"model for pic executables
assert(Subtarget->isTargetELF() && assert(Subtarget->isTargetELF() &&
@ -5365,7 +5374,7 @@ X86TargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) {
/// LowerShift - Lower SRA_PARTS and friends, which return two i32 values and /// LowerShift - Lower SRA_PARTS and friends, which return two i32 values and
/// take a 2 x i32 value to shift plus a shift amount. /// take a 2 x i32 value to shift plus a shift amount.
SDValue X86TargetLowering::LowerShift(SDValue Op, SelectionDAG &DAG) { SDValue X86TargetLowering::LowerShift(SDValue Op, SelectionDAG &DAG) const {
assert(Op.getNumOperands() == 3 && "Not a double-shift!"); assert(Op.getNumOperands() == 3 && "Not a double-shift!");
EVT VT = Op.getValueType(); EVT VT = Op.getValueType();
unsigned VTBits = VT.getSizeInBits(); unsigned VTBits = VT.getSizeInBits();
@ -5409,7 +5418,8 @@ SDValue X86TargetLowering::LowerShift(SDValue Op, SelectionDAG &DAG) {
return DAG.getMergeValues(Ops, 2, dl); return DAG.getMergeValues(Ops, 2, dl);
} }
SDValue X86TargetLowering::LowerSINT_TO_FP(SDValue Op, SelectionDAG &DAG) { SDValue X86TargetLowering::LowerSINT_TO_FP(SDValue Op,
SelectionDAG &DAG) const {
EVT SrcVT = Op.getOperand(0).getValueType(); EVT SrcVT = Op.getOperand(0).getValueType();
if (SrcVT.isVector()) { if (SrcVT.isVector()) {
@ -5445,7 +5455,7 @@ SDValue X86TargetLowering::LowerSINT_TO_FP(SDValue Op, SelectionDAG &DAG) {
SDValue X86TargetLowering::BuildFILD(SDValue Op, EVT SrcVT, SDValue Chain, SDValue X86TargetLowering::BuildFILD(SDValue Op, EVT SrcVT, SDValue Chain,
SDValue StackSlot, SDValue StackSlot,
SelectionDAG &DAG) { SelectionDAG &DAG) const {
// Build the FILD // Build the FILD
DebugLoc dl = Op.getDebugLoc(); DebugLoc dl = Op.getDebugLoc();
SDVTList Tys; SDVTList Tys;
@ -5482,7 +5492,8 @@ SDValue X86TargetLowering::BuildFILD(SDValue Op, EVT SrcVT, SDValue Chain,
} }
// LowerUINT_TO_FP_i64 - 64-bit unsigned integer to double expansion. // LowerUINT_TO_FP_i64 - 64-bit unsigned integer to double expansion.
SDValue X86TargetLowering::LowerUINT_TO_FP_i64(SDValue Op, SelectionDAG &DAG) { SDValue X86TargetLowering::LowerUINT_TO_FP_i64(SDValue Op,
SelectionDAG &DAG) const {
// This algorithm is not obvious. Here it is in C code, more or less: // This algorithm is not obvious. Here it is in C code, more or less:
/* /*
double uint64_to_double( uint32_t hi, uint32_t lo ) { double uint64_to_double( uint32_t hi, uint32_t lo ) {
@ -5566,7 +5577,8 @@ SDValue X86TargetLowering::LowerUINT_TO_FP_i64(SDValue Op, SelectionDAG &DAG) {
} }
// LowerUINT_TO_FP_i32 - 32-bit unsigned integer to float expansion. // LowerUINT_TO_FP_i32 - 32-bit unsigned integer to float expansion.
SDValue X86TargetLowering::LowerUINT_TO_FP_i32(SDValue Op, SelectionDAG &DAG) { SDValue X86TargetLowering::LowerUINT_TO_FP_i32(SDValue Op,
SelectionDAG &DAG) const {
DebugLoc dl = Op.getDebugLoc(); DebugLoc dl = Op.getDebugLoc();
// FP constant to bias correct the final result. // FP constant to bias correct the final result.
SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL), SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL),
@ -5611,7 +5623,8 @@ SDValue X86TargetLowering::LowerUINT_TO_FP_i32(SDValue Op, SelectionDAG &DAG) {
return Sub; return Sub;
} }
SDValue X86TargetLowering::LowerUINT_TO_FP(SDValue Op, SelectionDAG &DAG) { SDValue X86TargetLowering::LowerUINT_TO_FP(SDValue Op,
SelectionDAG &DAG) const {
SDValue N0 = Op.getOperand(0); SDValue N0 = Op.getOperand(0);
DebugLoc dl = Op.getDebugLoc(); DebugLoc dl = Op.getDebugLoc();
@ -5647,7 +5660,7 @@ SDValue X86TargetLowering::LowerUINT_TO_FP(SDValue Op, SelectionDAG &DAG) {
} }
std::pair<SDValue,SDValue> X86TargetLowering:: std::pair<SDValue,SDValue> X86TargetLowering::
FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG, bool IsSigned) { FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG, bool IsSigned) const {
DebugLoc dl = Op.getDebugLoc(); DebugLoc dl = Op.getDebugLoc();
EVT DstTy = Op.getValueType(); EVT DstTy = Op.getValueType();
@ -5709,7 +5722,8 @@ FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG, bool IsSigned) {
return std::make_pair(FIST, StackSlot); return std::make_pair(FIST, StackSlot);
} }
SDValue X86TargetLowering::LowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG) { SDValue X86TargetLowering::LowerFP_TO_SINT(SDValue Op,
SelectionDAG &DAG) const {
if (Op.getValueType().isVector()) { if (Op.getValueType().isVector()) {
if (Op.getValueType() == MVT::v2i32 && if (Op.getValueType() == MVT::v2i32 &&
Op.getOperand(0).getValueType() == MVT::v2f64) { Op.getOperand(0).getValueType() == MVT::v2f64) {
@ -5728,7 +5742,8 @@ SDValue X86TargetLowering::LowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG) {
FIST, StackSlot, NULL, 0, false, false, 0); FIST, StackSlot, NULL, 0, false, false, 0);
} }
SDValue X86TargetLowering::LowerFP_TO_UINT(SDValue Op, SelectionDAG &DAG) { SDValue X86TargetLowering::LowerFP_TO_UINT(SDValue Op,
SelectionDAG &DAG) const {
std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG, false); std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG, false);
SDValue FIST = Vals.first, StackSlot = Vals.second; SDValue FIST = Vals.first, StackSlot = Vals.second;
assert(FIST.getNode() && "Unexpected failure"); assert(FIST.getNode() && "Unexpected failure");
@ -5738,7 +5753,8 @@ SDValue X86TargetLowering::LowerFP_TO_UINT(SDValue Op, SelectionDAG &DAG) {
FIST, StackSlot, NULL, 0, false, false, 0); FIST, StackSlot, NULL, 0, false, false, 0);
} }
SDValue X86TargetLowering::LowerFABS(SDValue Op, SelectionDAG &DAG) { SDValue X86TargetLowering::LowerFABS(SDValue Op,
SelectionDAG &DAG) const {
LLVMContext *Context = DAG.getContext(); LLVMContext *Context = DAG.getContext();
DebugLoc dl = Op.getDebugLoc(); DebugLoc dl = Op.getDebugLoc();
EVT VT = Op.getValueType(); EVT VT = Op.getValueType();
@ -5765,7 +5781,7 @@ SDValue X86TargetLowering::LowerFABS(SDValue Op, SelectionDAG &DAG) {
return DAG.getNode(X86ISD::FAND, dl, VT, Op.getOperand(0), Mask); return DAG.getNode(X86ISD::FAND, dl, VT, Op.getOperand(0), Mask);
} }
SDValue X86TargetLowering::LowerFNEG(SDValue Op, SelectionDAG &DAG) { SDValue X86TargetLowering::LowerFNEG(SDValue Op, SelectionDAG &DAG) const {
LLVMContext *Context = DAG.getContext(); LLVMContext *Context = DAG.getContext();
DebugLoc dl = Op.getDebugLoc(); DebugLoc dl = Op.getDebugLoc();
EVT VT = Op.getValueType(); EVT VT = Op.getValueType();
@ -5800,7 +5816,7 @@ SDValue X86TargetLowering::LowerFNEG(SDValue Op, SelectionDAG &DAG) {
} }
} }
SDValue X86TargetLowering::LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) { SDValue X86TargetLowering::LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const {
LLVMContext *Context = DAG.getContext(); LLVMContext *Context = DAG.getContext();
SDValue Op0 = Op.getOperand(0); SDValue Op0 = Op.getOperand(0);
SDValue Op1 = Op.getOperand(1); SDValue Op1 = Op.getOperand(1);
@ -5876,7 +5892,7 @@ SDValue X86TargetLowering::LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) {
/// Emit nodes that will be selected as "test Op0,Op0", or something /// Emit nodes that will be selected as "test Op0,Op0", or something
/// equivalent. /// equivalent.
SDValue X86TargetLowering::EmitTest(SDValue Op, unsigned X86CC, SDValue X86TargetLowering::EmitTest(SDValue Op, unsigned X86CC,
SelectionDAG &DAG) { SelectionDAG &DAG) const {
DebugLoc dl = Op.getDebugLoc(); DebugLoc dl = Op.getDebugLoc();
// CF and OF aren't always set the way we want. Determine which // CF and OF aren't always set the way we want. Determine which
@ -6009,7 +6025,7 @@ SDValue X86TargetLowering::EmitTest(SDValue Op, unsigned X86CC,
/// Emit nodes that will be selected as "cmp Op0,Op1", or something /// Emit nodes that will be selected as "cmp Op0,Op1", or something
/// equivalent. /// equivalent.
SDValue X86TargetLowering::EmitCmp(SDValue Op0, SDValue Op1, unsigned X86CC, SDValue X86TargetLowering::EmitCmp(SDValue Op0, SDValue Op1, unsigned X86CC,
SelectionDAG &DAG) { SelectionDAG &DAG) const {
if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op1)) if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op1))
if (C->getAPIntValue() == 0) if (C->getAPIntValue() == 0)
return EmitTest(Op0, X86CC, DAG); return EmitTest(Op0, X86CC, DAG);
@ -6079,7 +6095,7 @@ static SDValue LowerToBT(SDValue And, ISD::CondCode CC,
return SDValue(); return SDValue();
} }
SDValue X86TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) { SDValue X86TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
assert(Op.getValueType() == MVT::i8 && "SetCC type must be 8-bit integer"); assert(Op.getValueType() == MVT::i8 && "SetCC type must be 8-bit integer");
SDValue Op0 = Op.getOperand(0); SDValue Op0 = Op.getOperand(0);
SDValue Op1 = Op.getOperand(1); SDValue Op1 = Op.getOperand(1);
@ -6133,7 +6149,7 @@ SDValue X86TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) {
DAG.getConstant(X86CC, MVT::i8), Cond); DAG.getConstant(X86CC, MVT::i8), Cond);
} }
SDValue X86TargetLowering::LowerVSETCC(SDValue Op, SelectionDAG &DAG) { SDValue X86TargetLowering::LowerVSETCC(SDValue Op, SelectionDAG &DAG) const {
SDValue Cond; SDValue Cond;
SDValue Op0 = Op.getOperand(0); SDValue Op0 = Op.getOperand(0);
SDValue Op1 = Op.getOperand(1); SDValue Op1 = Op.getOperand(1);
@ -6269,7 +6285,7 @@ static bool isX86LogicalCmp(SDValue Op) {
return false; return false;
} }
SDValue X86TargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) { SDValue X86TargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const {
bool addTest = true; bool addTest = true;
SDValue Cond = Op.getOperand(0); SDValue Cond = Op.getOperand(0);
DebugLoc dl = Op.getDebugLoc(); DebugLoc dl = Op.getDebugLoc();
@ -6389,7 +6405,7 @@ static bool isXor1OfSetCC(SDValue Op) {
return false; return false;
} }
SDValue X86TargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) { SDValue X86TargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) const {
bool addTest = true; bool addTest = true;
SDValue Chain = Op.getOperand(0); SDValue Chain = Op.getOperand(0);
SDValue Cond = Op.getOperand(1); SDValue Cond = Op.getOperand(1);
@ -6541,7 +6557,7 @@ SDValue X86TargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) {
// correct sequence. // correct sequence.
SDValue SDValue
X86TargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op, X86TargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
SelectionDAG &DAG) { SelectionDAG &DAG) const {
assert(Subtarget->isTargetCygMing() && assert(Subtarget->isTargetCygMing() &&
"This should be used only on Cygwin/Mingw targets"); "This should be used only on Cygwin/Mingw targets");
DebugLoc dl = Op.getDebugLoc(); DebugLoc dl = Op.getDebugLoc();
@ -6577,7 +6593,7 @@ X86TargetLowering::EmitTargetCodeForMemset(SelectionDAG &DAG, DebugLoc dl,
SDValue Size, unsigned Align, SDValue Size, unsigned Align,
bool isVolatile, bool isVolatile,
const Value *DstSV, const Value *DstSV,
uint64_t DstSVOff) { uint64_t DstSVOff) const {
ConstantSDNode *ConstantSize = dyn_cast<ConstantSDNode>(Size); ConstantSDNode *ConstantSize = dyn_cast<ConstantSDNode>(Size);
// If not DWORD aligned or size is more than the threshold, call the library. // If not DWORD aligned or size is more than the threshold, call the library.
@ -6716,8 +6732,10 @@ X86TargetLowering::EmitTargetCodeForMemcpy(SelectionDAG &DAG, DebugLoc dl,
SDValue Chain, SDValue Dst, SDValue Src, SDValue Chain, SDValue Dst, SDValue Src,
SDValue Size, unsigned Align, SDValue Size, unsigned Align,
bool isVolatile, bool AlwaysInline, bool isVolatile, bool AlwaysInline,
const Value *DstSV, uint64_t DstSVOff, const Value *DstSV,
const Value *SrcSV, uint64_t SrcSVOff) { uint64_t DstSVOff,
const Value *SrcSV,
uint64_t SrcSVOff) const {
// This requires the copy size to be a constant, preferrably // This requires the copy size to be a constant, preferrably
// within a subtarget-specific limit. // within a subtarget-specific limit.
ConstantSDNode *ConstantSize = dyn_cast<ConstantSDNode>(Size); ConstantSDNode *ConstantSize = dyn_cast<ConstantSDNode>(Size);
@ -6783,7 +6801,7 @@ X86TargetLowering::EmitTargetCodeForMemcpy(SelectionDAG &DAG, DebugLoc dl,
&Results[0], Results.size()); &Results[0], Results.size());
} }
SDValue X86TargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) { SDValue X86TargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const {
MachineFunction &MF = DAG.getMachineFunction(); MachineFunction &MF = DAG.getMachineFunction();
X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>(); X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
@ -6843,7 +6861,7 @@ SDValue X86TargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) {
&MemOps[0], MemOps.size()); &MemOps[0], MemOps.size());
} }
SDValue X86TargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG) { SDValue X86TargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG) const {
// X86-64 va_list is a struct { i32, i32, i8*, i8* }. // X86-64 va_list is a struct { i32, i32, i8*, i8* }.
assert(Subtarget->is64Bit() && "This code only handles 64-bit va_arg!"); assert(Subtarget->is64Bit() && "This code only handles 64-bit va_arg!");
SDValue Chain = Op.getOperand(0); SDValue Chain = Op.getOperand(0);
@ -6854,7 +6872,7 @@ SDValue X86TargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG) {
return SDValue(); return SDValue();
} }
SDValue X86TargetLowering::LowerVACOPY(SDValue Op, SelectionDAG &DAG) { SDValue X86TargetLowering::LowerVACOPY(SDValue Op, SelectionDAG &DAG) const {
// X86-64 va_list is a struct { i32, i32, i8*, i8* }. // X86-64 va_list is a struct { i32, i32, i8*, i8* }.
assert(Subtarget->is64Bit() && "This code only handles 64-bit va_copy!"); assert(Subtarget->is64Bit() && "This code only handles 64-bit va_copy!");
SDValue Chain = Op.getOperand(0); SDValue Chain = Op.getOperand(0);
@ -6870,7 +6888,7 @@ SDValue X86TargetLowering::LowerVACOPY(SDValue Op, SelectionDAG &DAG) {
} }
SDValue SDValue
X86TargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) { X86TargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const {
DebugLoc dl = Op.getDebugLoc(); DebugLoc dl = Op.getDebugLoc();
unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue(); unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
switch (IntNo) { switch (IntNo) {
@ -7111,7 +7129,8 @@ X86TargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) {
} }
} }
SDValue X86TargetLowering::LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) { SDValue X86TargetLowering::LowerRETURNADDR(SDValue Op,
SelectionDAG &DAG) const {
unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue(); unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
DebugLoc dl = Op.getDebugLoc(); DebugLoc dl = Op.getDebugLoc();
@ -7132,7 +7151,7 @@ SDValue X86TargetLowering::LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) {
RetAddrFI, NULL, 0, false, false, 0); RetAddrFI, NULL, 0, false, false, 0);
} }
SDValue X86TargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) { SDValue X86TargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const {
MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
MFI->setFrameAddressIsTaken(true); MFI->setFrameAddressIsTaken(true);
EVT VT = Op.getValueType(); EVT VT = Op.getValueType();
@ -7147,12 +7166,11 @@ SDValue X86TargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) {
} }
SDValue X86TargetLowering::LowerFRAME_TO_ARGS_OFFSET(SDValue Op, SDValue X86TargetLowering::LowerFRAME_TO_ARGS_OFFSET(SDValue Op,
SelectionDAG &DAG) { SelectionDAG &DAG) const {
return DAG.getIntPtrConstant(2*TD->getPointerSize()); return DAG.getIntPtrConstant(2*TD->getPointerSize());
} }
SDValue X86TargetLowering::LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) SDValue X86TargetLowering::LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const {
{
MachineFunction &MF = DAG.getMachineFunction(); MachineFunction &MF = DAG.getMachineFunction();
SDValue Chain = Op.getOperand(0); SDValue Chain = Op.getOperand(0);
SDValue Offset = Op.getOperand(1); SDValue Offset = Op.getOperand(1);
@ -7176,7 +7194,7 @@ SDValue X86TargetLowering::LowerEH_RETURN(SDValue Op, SelectionDAG &DAG)
} }
SDValue X86TargetLowering::LowerTRAMPOLINE(SDValue Op, SDValue X86TargetLowering::LowerTRAMPOLINE(SDValue Op,
SelectionDAG &DAG) { SelectionDAG &DAG) const {
SDValue Root = Op.getOperand(0); SDValue Root = Op.getOperand(0);
SDValue Trmp = Op.getOperand(1); // trampoline SDValue Trmp = Op.getOperand(1); // trampoline
SDValue FPtr = Op.getOperand(2); // nested function SDValue FPtr = Op.getOperand(2); // nested function
@ -7316,7 +7334,8 @@ SDValue X86TargetLowering::LowerTRAMPOLINE(SDValue Op,
} }
} }
SDValue X86TargetLowering::LowerFLT_ROUNDS_(SDValue Op, SelectionDAG &DAG) { SDValue X86TargetLowering::LowerFLT_ROUNDS_(SDValue Op,
SelectionDAG &DAG) const {
/* /*
The rounding mode is in bits 11:10 of FPSR, and has the following The rounding mode is in bits 11:10 of FPSR, and has the following
settings: settings:
@ -7378,7 +7397,7 @@ SDValue X86TargetLowering::LowerFLT_ROUNDS_(SDValue Op, SelectionDAG &DAG) {
ISD::TRUNCATE : ISD::ZERO_EXTEND), dl, VT, RetVal); ISD::TRUNCATE : ISD::ZERO_EXTEND), dl, VT, RetVal);
} }
SDValue X86TargetLowering::LowerCTLZ(SDValue Op, SelectionDAG &DAG) { SDValue X86TargetLowering::LowerCTLZ(SDValue Op, SelectionDAG &DAG) const {
EVT VT = Op.getValueType(); EVT VT = Op.getValueType();
EVT OpVT = VT; EVT OpVT = VT;
unsigned NumBits = VT.getSizeInBits(); unsigned NumBits = VT.getSizeInBits();
@ -7412,7 +7431,7 @@ SDValue X86TargetLowering::LowerCTLZ(SDValue Op, SelectionDAG &DAG) {
return Op; return Op;
} }
SDValue X86TargetLowering::LowerCTTZ(SDValue Op, SelectionDAG &DAG) { SDValue X86TargetLowering::LowerCTTZ(SDValue Op, SelectionDAG &DAG) const {
EVT VT = Op.getValueType(); EVT VT = Op.getValueType();
EVT OpVT = VT; EVT OpVT = VT;
unsigned NumBits = VT.getSizeInBits(); unsigned NumBits = VT.getSizeInBits();
@ -7442,7 +7461,7 @@ SDValue X86TargetLowering::LowerCTTZ(SDValue Op, SelectionDAG &DAG) {
return Op; return Op;
} }
SDValue X86TargetLowering::LowerMUL_V2I64(SDValue Op, SelectionDAG &DAG) { SDValue X86TargetLowering::LowerMUL_V2I64(SDValue Op, SelectionDAG &DAG) const {
EVT VT = Op.getValueType(); EVT VT = Op.getValueType();
assert(VT == MVT::v2i64 && "Only know how to lower V2I64 multiply"); assert(VT == MVT::v2i64 && "Only know how to lower V2I64 multiply");
DebugLoc dl = Op.getDebugLoc(); DebugLoc dl = Op.getDebugLoc();
@ -7487,7 +7506,7 @@ SDValue X86TargetLowering::LowerMUL_V2I64(SDValue Op, SelectionDAG &DAG) {
} }
SDValue X86TargetLowering::LowerXALUO(SDValue Op, SelectionDAG &DAG) { SDValue X86TargetLowering::LowerXALUO(SDValue Op, SelectionDAG &DAG) const {
// Lower the "add/sub/mul with overflow" instruction into a regular ins plus // Lower the "add/sub/mul with overflow" instruction into a regular ins plus
// a "setcc" instruction that checks the overflow flag. The "brcond" lowering // a "setcc" instruction that checks the overflow flag. The "brcond" lowering
// looks for this combo and may remove the "setcc" instruction if the "setcc" // looks for this combo and may remove the "setcc" instruction if the "setcc"
@ -7555,7 +7574,7 @@ SDValue X86TargetLowering::LowerXALUO(SDValue Op, SelectionDAG &DAG) {
return Sum; return Sum;
} }
SDValue X86TargetLowering::LowerCMP_SWAP(SDValue Op, SelectionDAG &DAG) { SDValue X86TargetLowering::LowerCMP_SWAP(SDValue Op, SelectionDAG &DAG) const {
EVT T = Op.getValueType(); EVT T = Op.getValueType();
DebugLoc dl = Op.getDebugLoc(); DebugLoc dl = Op.getDebugLoc();
unsigned Reg = 0; unsigned Reg = 0;
@ -7586,7 +7605,7 @@ SDValue X86TargetLowering::LowerCMP_SWAP(SDValue Op, SelectionDAG &DAG) {
} }
SDValue X86TargetLowering::LowerREADCYCLECOUNTER(SDValue Op, SDValue X86TargetLowering::LowerREADCYCLECOUNTER(SDValue Op,
SelectionDAG &DAG) { SelectionDAG &DAG) const {
assert(Subtarget->is64Bit() && "Result not type legalized?"); assert(Subtarget->is64Bit() && "Result not type legalized?");
SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag); SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
SDValue TheChain = Op.getOperand(0); SDValue TheChain = Op.getOperand(0);
@ -7604,7 +7623,7 @@ SDValue X86TargetLowering::LowerREADCYCLECOUNTER(SDValue Op,
return DAG.getMergeValues(Ops, 2, dl); return DAG.getMergeValues(Ops, 2, dl);
} }
SDValue X86TargetLowering::LowerLOAD_SUB(SDValue Op, SelectionDAG &DAG) { SDValue X86TargetLowering::LowerLOAD_SUB(SDValue Op, SelectionDAG &DAG) const {
SDNode *Node = Op.getNode(); SDNode *Node = Op.getNode();
DebugLoc dl = Node->getDebugLoc(); DebugLoc dl = Node->getDebugLoc();
EVT T = Node->getValueType(0); EVT T = Node->getValueType(0);
@ -7620,7 +7639,7 @@ SDValue X86TargetLowering::LowerLOAD_SUB(SDValue Op, SelectionDAG &DAG) {
/// LowerOperation - Provide custom lowering hooks for some operations. /// LowerOperation - Provide custom lowering hooks for some operations.
/// ///
SDValue X86TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) { SDValue X86TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
switch (Op.getOpcode()) { switch (Op.getOpcode()) {
default: llvm_unreachable("Should not custom lower this!"); default: llvm_unreachable("Should not custom lower this!");
case ISD::ATOMIC_CMP_SWAP: return LowerCMP_SWAP(Op,DAG); case ISD::ATOMIC_CMP_SWAP: return LowerCMP_SWAP(Op,DAG);
@ -7678,7 +7697,7 @@ SDValue X86TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) {
void X86TargetLowering:: void X86TargetLowering::
ReplaceATOMIC_BINARY_64(SDNode *Node, SmallVectorImpl<SDValue>&Results, ReplaceATOMIC_BINARY_64(SDNode *Node, SmallVectorImpl<SDValue>&Results,
SelectionDAG &DAG, unsigned NewOp) { SelectionDAG &DAG, unsigned NewOp) const {
EVT T = Node->getValueType(0); EVT T = Node->getValueType(0);
DebugLoc dl = Node->getDebugLoc(); DebugLoc dl = Node->getDebugLoc();
assert (T == MVT::i64 && "Only know how to expand i64 atomics"); assert (T == MVT::i64 && "Only know how to expand i64 atomics");
@ -7703,7 +7722,7 @@ ReplaceATOMIC_BINARY_64(SDNode *Node, SmallVectorImpl<SDValue>&Results,
/// with a new node built out of custom code. /// with a new node built out of custom code.
void X86TargetLowering::ReplaceNodeResults(SDNode *N, void X86TargetLowering::ReplaceNodeResults(SDNode *N,
SmallVectorImpl<SDValue>&Results, SmallVectorImpl<SDValue>&Results,
SelectionDAG &DAG) { SelectionDAG &DAG) const {
DebugLoc dl = N->getDebugLoc(); DebugLoc dl = N->getDebugLoc();
switch (N->getOpcode()) { switch (N->getOpcode()) {
default: default:
@ -9807,7 +9826,7 @@ static SDValue PerformBTCombine(SDNode *N,
APInt KnownZero, KnownOne; APInt KnownZero, KnownOne;
TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(), TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(),
!DCI.isBeforeLegalizeOps()); !DCI.isBeforeLegalizeOps());
TargetLowering &TLI = DAG.getTargetLoweringInfo(); const TargetLowering &TLI = DAG.getTargetLoweringInfo();
if (TLO.ShrinkDemandedConstant(Op1, DemandedMask) || if (TLO.ShrinkDemandedConstant(Op1, DemandedMask) ||
TLI.SimplifyDemandedBits(Op1, DemandedMask, KnownZero, KnownOne, TLO)) TLI.SimplifyDemandedBits(Op1, DemandedMask, KnownZero, KnownOne, TLO))
DCI.CommitTargetLoweringOpt(TLO); DCI.CommitTargetLoweringOpt(TLO);

146
llvm/lib/Target/X86/X86ISelLowering.h
View File

@ -430,13 +430,13 @@ namespace llvm {
/// LowerOperation - Provide custom lowering hooks for some operations. /// LowerOperation - Provide custom lowering hooks for some operations.
/// ///
virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG); virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
/// ReplaceNodeResults - Replace the results of node with an illegal result /// ReplaceNodeResults - Replace the results of node with an illegal result
/// type with new values built out of custom code. /// type with new values built out of custom code.
/// ///
virtual void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results, virtual void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results,
SelectionDAG &DAG); SelectionDAG &DAG) const;
virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const; virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
@ -478,7 +478,7 @@ namespace llvm {
virtual bool virtual bool
isGAPlusOffset(SDNode *N, const GlobalValue* &GA, int64_t &Offset) const; isGAPlusOffset(SDNode *N, const GlobalValue* &GA, int64_t &Offset) const;
SDValue getReturnAddressFrameIndex(SelectionDAG &DAG); SDValue getReturnAddressFrameIndex(SelectionDAG &DAG) const;
virtual bool ExpandInlineAsm(CallInst *CI) const; virtual bool ExpandInlineAsm(CallInst *CI) const;
@ -563,7 +563,7 @@ namespace llvm {
return !X86ScalarSSEf64 || VT == MVT::f80; return !X86ScalarSSEf64 || VT == MVT::f80;
} }
virtual const X86Subtarget* getSubtarget() { virtual const X86Subtarget* getSubtarget() const {
return Subtarget; return Subtarget;
} }
@ -584,7 +584,7 @@ namespace llvm {
#ifndef NDEBUG #ifndef NDEBUG
, SmallSet<const Instruction *, 8> & , SmallSet<const Instruction *, 8> &
#endif #endif
); ) const;
/// getFunctionAlignment - Return the Log2 alignment of this function. /// getFunctionAlignment - Return the Log2 alignment of this function.
virtual unsigned getFunctionAlignment(const Function *F) const; virtual unsigned getFunctionAlignment(const Function *F) const;
@ -619,17 +619,17 @@ namespace llvm {
CallingConv::ID CallConv, bool isVarArg, CallingConv::ID CallConv, bool isVarArg,
const SmallVectorImpl<ISD::InputArg> &Ins, const SmallVectorImpl<ISD::InputArg> &Ins,
DebugLoc dl, SelectionDAG &DAG, DebugLoc dl, SelectionDAG &DAG,
SmallVectorImpl<SDValue> &InVals); SmallVectorImpl<SDValue> &InVals) const;
SDValue LowerMemArgument(SDValue Chain, SDValue LowerMemArgument(SDValue Chain,
CallingConv::ID CallConv, CallingConv::ID CallConv,
const SmallVectorImpl<ISD::InputArg> &ArgInfo, const SmallVectorImpl<ISD::InputArg> &ArgInfo,
DebugLoc dl, SelectionDAG &DAG, DebugLoc dl, SelectionDAG &DAG,
const CCValAssign &VA, MachineFrameInfo *MFI, const CCValAssign &VA, MachineFrameInfo *MFI,
unsigned i); unsigned i) const;
SDValue LowerMemOpCallTo(SDValue Chain, SDValue StackPtr, SDValue Arg, SDValue LowerMemOpCallTo(SDValue Chain, SDValue StackPtr, SDValue Arg,
DebugLoc dl, SelectionDAG &DAG, DebugLoc dl, SelectionDAG &DAG,
const CCValAssign &VA, const CCValAssign &VA,
ISD::ArgFlagsTy Flags); ISD::ArgFlagsTy Flags) const;
// Call lowering helpers. // Call lowering helpers.
@ -644,114 +644,118 @@ namespace llvm {
const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<ISD::OutputArg> &Outs,
const SmallVectorImpl<ISD::InputArg> &Ins, const SmallVectorImpl<ISD::InputArg> &Ins,
SelectionDAG& DAG) const; SelectionDAG& DAG) const;
bool IsCalleePop(bool isVarArg, CallingConv::ID CallConv); bool IsCalleePop(bool isVarArg, CallingConv::ID CallConv) const;
SDValue EmitTailCallLoadRetAddr(SelectionDAG &DAG, SDValue &OutRetAddr, SDValue EmitTailCallLoadRetAddr(SelectionDAG &DAG, SDValue &OutRetAddr,
SDValue Chain, bool IsTailCall, bool Is64Bit, SDValue Chain, bool IsTailCall, bool Is64Bit,
int FPDiff, DebugLoc dl); int FPDiff, DebugLoc dl) const;
CCAssignFn *CCAssignFnForNode(CallingConv::ID CallConv) const; CCAssignFn *CCAssignFnForNode(CallingConv::ID CallConv) const;
unsigned GetAlignedArgumentStackSize(unsigned StackSize, SelectionDAG &DAG); unsigned GetAlignedArgumentStackSize(unsigned StackSize,
SelectionDAG &DAG) const;
std::pair<SDValue,SDValue> FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG, std::pair<SDValue,SDValue> FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG,
bool isSigned); bool isSigned) const;
SDValue LowerAsSplatVectorLoad(SDValue SrcOp, EVT VT, DebugLoc dl, SDValue LowerAsSplatVectorLoad(SDValue SrcOp, EVT VT, DebugLoc dl,
SelectionDAG &DAG); SelectionDAG &DAG) const;
SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG); SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG); SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG); SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG); SDValue LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerEXTRACT_VECTOR_ELT_SSE4(SDValue Op, SelectionDAG &DAG); SDValue LowerEXTRACT_VECTOR_ELT_SSE4(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG); SDValue LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerINSERT_VECTOR_ELT_SSE4(SDValue Op, SelectionDAG &DAG); SDValue LowerINSERT_VECTOR_ELT_SSE4(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG); SDValue LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG); SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG); SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerGlobalAddress(const GlobalValue *GV, DebugLoc dl, SDValue LowerGlobalAddress(const GlobalValue *GV, DebugLoc dl,
int64_t Offset, SelectionDAG &DAG) const; int64_t Offset, SelectionDAG &DAG) const;
SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG); SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG); SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerExternalSymbol(SDValue Op, SelectionDAG &DAG); SDValue LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerShift(SDValue Op, SelectionDAG &DAG); SDValue LowerShift(SDValue Op, SelectionDAG &DAG) const;
SDValue BuildFILD(SDValue Op, EVT SrcVT, SDValue Chain, SDValue StackSlot, SDValue BuildFILD(SDValue Op, EVT SrcVT, SDValue Chain, SDValue StackSlot,
SelectionDAG &DAG); SelectionDAG &DAG) const;
SDValue LowerSINT_TO_FP(SDValue Op, SelectionDAG &DAG); SDValue LowerSINT_TO_FP(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerUINT_TO_FP(SDValue Op, SelectionDAG &DAG); SDValue LowerUINT_TO_FP(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerUINT_TO_FP_i64(SDValue Op, SelectionDAG &DAG); SDValue LowerUINT_TO_FP_i64(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerUINT_TO_FP_i32(SDValue Op, SelectionDAG &DAG); SDValue LowerUINT_TO_FP_i32(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG); SDValue LowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerFP_TO_UINT(SDValue Op, SelectionDAG &DAG); SDValue LowerFP_TO_UINT(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerFABS(SDValue Op, SelectionDAG &DAG); SDValue LowerFABS(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerFNEG(SDValue Op, SelectionDAG &DAG); SDValue LowerFNEG(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG); SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG); SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerVSETCC(SDValue Op, SelectionDAG &DAG); SDValue LowerVSETCC(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerSELECT(SDValue Op, SelectionDAG &DAG); SDValue LowerSELECT(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerBRCOND(SDValue Op, SelectionDAG &DAG); SDValue LowerBRCOND(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerMEMSET(SDValue Op, SelectionDAG &DAG); SDValue LowerMEMSET(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG); SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG); SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG); SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerVAARG(SDValue Op, SelectionDAG &DAG); SDValue LowerVAARG(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerVACOPY(SDValue Op, SelectionDAG &DAG); SDValue LowerVACOPY(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG); SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG); SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG); SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerFRAME_TO_ARGS_OFFSET(SDValue Op, SelectionDAG &DAG); SDValue LowerFRAME_TO_ARGS_OFFSET(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerEH_RETURN(SDValue Op, SelectionDAG &DAG); SDValue LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerTRAMPOLINE(SDValue Op, SelectionDAG &DAG); SDValue LowerTRAMPOLINE(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerFLT_ROUNDS_(SDValue Op, SelectionDAG &DAG); SDValue LowerFLT_ROUNDS_(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerCTLZ(SDValue Op, SelectionDAG &DAG); SDValue LowerCTLZ(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerCTTZ(SDValue Op, SelectionDAG &DAG); SDValue LowerCTTZ(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerMUL_V2I64(SDValue Op, SelectionDAG &DAG); SDValue LowerMUL_V2I64(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerXALUO(SDValue Op, SelectionDAG &DAG); SDValue LowerXALUO(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerCMP_SWAP(SDValue Op, SelectionDAG &DAG); SDValue LowerCMP_SWAP(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerLOAD_SUB(SDValue Op, SelectionDAG &DAG); SDValue LowerLOAD_SUB(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerREADCYCLECOUNTER(SDValue Op, SelectionDAG &DAG); SDValue LowerREADCYCLECOUNTER(SDValue Op, SelectionDAG &DAG) const;
virtual SDValue virtual SDValue
LowerFormalArguments(SDValue Chain, LowerFormalArguments(SDValue Chain,
CallingConv::ID CallConv, bool isVarArg, CallingConv::ID CallConv, bool isVarArg,
const SmallVectorImpl<ISD::InputArg> &Ins, const SmallVectorImpl<ISD::InputArg> &Ins,
DebugLoc dl, SelectionDAG &DAG, DebugLoc dl, SelectionDAG &DAG,
SmallVectorImpl<SDValue> &InVals); SmallVectorImpl<SDValue> &InVals) const;
virtual SDValue virtual SDValue
LowerCall(SDValue Chain, SDValue Callee, LowerCall(SDValue Chain, SDValue Callee,
CallingConv::ID CallConv, bool isVarArg, bool &isTailCall, CallingConv::ID CallConv, bool isVarArg, bool &isTailCall,
const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<ISD::OutputArg> &Outs,
const SmallVectorImpl<ISD::InputArg> &Ins, const SmallVectorImpl<ISD::InputArg> &Ins,
DebugLoc dl, SelectionDAG &DAG, DebugLoc dl, SelectionDAG &DAG,
SmallVectorImpl<SDValue> &InVals); SmallVectorImpl<SDValue> &InVals) const;
virtual SDValue virtual SDValue
LowerReturn(SDValue Chain, LowerReturn(SDValue Chain,
CallingConv::ID CallConv, bool isVarArg, CallingConv::ID CallConv, bool isVarArg,
const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<ISD::OutputArg> &Outs,
DebugLoc dl, SelectionDAG &DAG); DebugLoc dl, SelectionDAG &DAG) const;
virtual bool virtual bool
CanLowerReturn(CallingConv::ID CallConv, bool isVarArg, CanLowerReturn(CallingConv::ID CallConv, bool isVarArg,
const SmallVectorImpl<EVT> &OutTys, const SmallVectorImpl<EVT> &OutTys,
const SmallVectorImpl<ISD::ArgFlagsTy> &ArgsFlags, const SmallVectorImpl<ISD::ArgFlagsTy> &ArgsFlags,
SelectionDAG &DAG); SelectionDAG &DAG) const;
void ReplaceATOMIC_BINARY_64(SDNode *N, SmallVectorImpl<SDValue> &Results, void ReplaceATOMIC_BINARY_64(SDNode *N, SmallVectorImpl<SDValue> &Results,
SelectionDAG &DAG, unsigned NewOp); SelectionDAG &DAG, unsigned NewOp) const;
SDValue EmitTargetCodeForMemset(SelectionDAG &DAG, DebugLoc dl, SDValue EmitTargetCodeForMemset(SelectionDAG &DAG, DebugLoc dl,
SDValue Chain, SDValue Chain,
SDValue Dst, SDValue Src, SDValue Dst, SDValue Src,
SDValue Size, unsigned Align, SDValue Size, unsigned Align,
bool isVolatile, bool isVolatile,
const Value *DstSV, uint64_t DstSVOff); const Value *DstSV,
uint64_t DstSVOff) const;
SDValue EmitTargetCodeForMemcpy(SelectionDAG &DAG, DebugLoc dl, SDValue EmitTargetCodeForMemcpy(SelectionDAG &DAG, DebugLoc dl,
SDValue Chain, SDValue Chain,
SDValue Dst, SDValue Src, SDValue Dst, SDValue Src,
SDValue Size, unsigned Align, SDValue Size, unsigned Align,
bool isVolatile, bool AlwaysInline, bool isVolatile, bool AlwaysInline,
const Value *DstSV, uint64_t DstSVOff, const Value *DstSV,
const Value *SrcSV, uint64_t SrcSVOff); uint64_t DstSVOff,
const Value *SrcSV,
uint64_t SrcSVOff) const;
/// Utility function to emit string processing sse4.2 instructions /// Utility function to emit string processing sse4.2 instructions
/// that return in xmm0. /// that return in xmm0.
@ -808,12 +812,12 @@ namespace llvm {
/// Emit nodes that will be selected as "test Op0,Op0", or something /// Emit nodes that will be selected as "test Op0,Op0", or something
/// equivalent, for use with the given x86 condition code. /// equivalent, for use with the given x86 condition code.
SDValue EmitTest(SDValue Op0, unsigned X86CC, SelectionDAG &DAG); SDValue EmitTest(SDValue Op0, unsigned X86CC, SelectionDAG &DAG) const;
/// Emit nodes that will be selected as "cmp Op0,Op1", or something /// Emit nodes that will be selected as "cmp Op0,Op1", or something
/// equivalent, for use with the given x86 condition code. /// equivalent, for use with the given x86 condition code.
SDValue EmitCmp(SDValue Op0, SDValue Op1, unsigned X86CC, SDValue EmitCmp(SDValue Op0, SDValue Op1, unsigned X86CC,
SelectionDAG &DAG); SelectionDAG &DAG) const;
}; };
namespace X86 { namespace X86 {

4
llvm/lib/Target/X86/X86TargetMachine.h
View File

@ -51,8 +51,8 @@ public:
virtual const TargetFrameInfo *getFrameInfo() const { return &FrameInfo; } virtual const TargetFrameInfo *getFrameInfo() const { return &FrameInfo; }
virtual X86JITInfo *getJITInfo() { return &JITInfo; } virtual X86JITInfo *getJITInfo() { return &JITInfo; }
virtual const X86Subtarget *getSubtargetImpl() const{ return &Subtarget; } virtual const X86Subtarget *getSubtargetImpl() const{ return &Subtarget; }
virtual X86TargetLowering *getTargetLowering() const { virtual const X86TargetLowering *getTargetLowering() const {
return const_cast<X86TargetLowering*>(&TLInfo); return &TLInfo;
} }
virtual const X86RegisterInfo *getRegisterInfo() const { virtual const X86RegisterInfo *getRegisterInfo() const {
return &InstrInfo.getRegisterInfo(); return &InstrInfo.getRegisterInfo();

3
llvm/lib/Target/XCore/XCoreISelDAGToDAG.cpp
View File

@ -12,7 +12,6 @@
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
#include "XCore.h" #include "XCore.h"
#include "XCoreISelLowering.h"
#include "XCoreTargetMachine.h" #include "XCoreTargetMachine.h"
#include "llvm/DerivedTypes.h" #include "llvm/DerivedTypes.h"
#include "llvm/Function.h" #include "llvm/Function.h"
@ -40,7 +39,7 @@ using namespace llvm;
/// ///
namespace { namespace {
class XCoreDAGToDAGISel : public SelectionDAGISel { class XCoreDAGToDAGISel : public SelectionDAGISel {
XCoreTargetLowering &Lowering; const XCoreTargetLowering &Lowering;
const XCoreSubtarget &Subtarget; const XCoreSubtarget &Subtarget;
public: public:

53
llvm/lib/Target/XCore/XCoreISelLowering.cpp
View File

@ -158,7 +158,7 @@ XCoreTargetLowering::XCoreTargetLowering(XCoreTargetMachine &XTM)
} }
SDValue XCoreTargetLowering:: SDValue XCoreTargetLowering::
LowerOperation(SDValue Op, SelectionDAG &DAG) { LowerOperation(SDValue Op, SelectionDAG &DAG) const {
switch (Op.getOpcode()) switch (Op.getOpcode())
{ {
case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG); case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
@ -187,7 +187,7 @@ LowerOperation(SDValue Op, SelectionDAG &DAG) {
/// type with new values built out of custom code. /// type with new values built out of custom code.
void XCoreTargetLowering::ReplaceNodeResults(SDNode *N, void XCoreTargetLowering::ReplaceNodeResults(SDNode *N,
SmallVectorImpl<SDValue>&Results, SmallVectorImpl<SDValue>&Results,
SelectionDAG &DAG) { SelectionDAG &DAG) const {
switch (N->getOpcode()) { switch (N->getOpcode()) {
default: default:
llvm_unreachable("Don't know how to custom expand this!"); llvm_unreachable("Don't know how to custom expand this!");
@ -210,7 +210,7 @@ getFunctionAlignment(const Function *) const {
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
SDValue XCoreTargetLowering:: SDValue XCoreTargetLowering::
LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const
{ {
DebugLoc dl = Op.getDebugLoc(); DebugLoc dl = Op.getDebugLoc();
SDValue Cond = DAG.getNode(ISD::SETCC, dl, MVT::i32, Op.getOperand(2), SDValue Cond = DAG.getNode(ISD::SETCC, dl, MVT::i32, Op.getOperand(2),
@ -220,7 +220,8 @@ LowerSELECT_CC(SDValue Op, SelectionDAG &DAG)
} }
SDValue XCoreTargetLowering:: SDValue XCoreTargetLowering::
getGlobalAddressWrapper(SDValue GA, const GlobalValue *GV, SelectionDAG &DAG) getGlobalAddressWrapper(SDValue GA, const GlobalValue *GV,
SelectionDAG &DAG) const
{ {
// FIXME there is no actual debug info here // FIXME there is no actual debug info here
DebugLoc dl = GA.getDebugLoc(); DebugLoc dl = GA.getDebugLoc();
@ -241,7 +242,7 @@ getGlobalAddressWrapper(SDValue GA, const GlobalValue *GV, SelectionDAG &DAG)
} }
SDValue XCoreTargetLowering:: SDValue XCoreTargetLowering::
LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const
{ {
const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal(); const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
SDValue GA = DAG.getTargetGlobalAddress(GV, MVT::i32); SDValue GA = DAG.getTargetGlobalAddress(GV, MVT::i32);
@ -262,7 +263,7 @@ static inline bool isZeroLengthArray(const Type *Ty) {
} }
SDValue XCoreTargetLowering:: SDValue XCoreTargetLowering::
LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const
{ {
// FIXME there isn't really debug info here // FIXME there isn't really debug info here
DebugLoc dl = Op.getDebugLoc(); DebugLoc dl = Op.getDebugLoc();
@ -296,7 +297,7 @@ LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG)
} }
SDValue XCoreTargetLowering:: SDValue XCoreTargetLowering::
LowerBlockAddress(SDValue Op, SelectionDAG &DAG) LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const
{ {
DebugLoc DL = Op.getDebugLoc(); DebugLoc DL = Op.getDebugLoc();
@ -307,7 +308,7 @@ LowerBlockAddress(SDValue Op, SelectionDAG &DAG)
} }
SDValue XCoreTargetLowering:: SDValue XCoreTargetLowering::
LowerConstantPool(SDValue Op, SelectionDAG &DAG) LowerConstantPool(SDValue Op, SelectionDAG &DAG) const
{ {
ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op); ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
// FIXME there isn't really debug info here // FIXME there isn't really debug info here
@ -329,7 +330,7 @@ unsigned XCoreTargetLowering::getJumpTableEncoding() const {
} }
SDValue XCoreTargetLowering:: SDValue XCoreTargetLowering::
LowerBR_JT(SDValue Op, SelectionDAG &DAG) LowerBR_JT(SDValue Op, SelectionDAG &DAG) const
{ {
SDValue Chain = Op.getOperand(0); SDValue Chain = Op.getOperand(0);
SDValue Table = Op.getOperand(1); SDValue Table = Op.getOperand(1);
@ -391,7 +392,7 @@ IsWordAlignedBasePlusConstantOffset(SDValue Addr, SDValue &AlignedBase,
} }
SDValue XCoreTargetLowering:: SDValue XCoreTargetLowering::
LowerLOAD(SDValue Op, SelectionDAG &DAG) LowerLOAD(SDValue Op, SelectionDAG &DAG) const
{ {
LoadSDNode *LD = cast<LoadSDNode>(Op); LoadSDNode *LD = cast<LoadSDNode>(Op);
assert(LD->getExtensionType() == ISD::NON_EXTLOAD && assert(LD->getExtensionType() == ISD::NON_EXTLOAD &&
@ -494,7 +495,7 @@ LowerLOAD(SDValue Op, SelectionDAG &DAG)
} }
SDValue XCoreTargetLowering:: SDValue XCoreTargetLowering::
LowerSTORE(SDValue Op, SelectionDAG &DAG) LowerSTORE(SDValue Op, SelectionDAG &DAG) const
{ {
StoreSDNode *ST = cast<StoreSDNode>(Op); StoreSDNode *ST = cast<StoreSDNode>(Op);
assert(!ST->isTruncatingStore() && "Unexpected store type"); assert(!ST->isTruncatingStore() && "Unexpected store type");
@ -554,7 +555,7 @@ LowerSTORE(SDValue Op, SelectionDAG &DAG)
} }
SDValue XCoreTargetLowering:: SDValue XCoreTargetLowering::
LowerSMUL_LOHI(SDValue Op, SelectionDAG &DAG) LowerSMUL_LOHI(SDValue Op, SelectionDAG &DAG) const
{ {
assert(Op.getValueType() == MVT::i32 && Op.getOpcode() == ISD::SMUL_LOHI && assert(Op.getValueType() == MVT::i32 && Op.getOpcode() == ISD::SMUL_LOHI &&
"Unexpected operand to lower!"); "Unexpected operand to lower!");
@ -571,7 +572,7 @@ LowerSMUL_LOHI(SDValue Op, SelectionDAG &DAG)
} }
SDValue XCoreTargetLowering:: SDValue XCoreTargetLowering::
LowerUMUL_LOHI(SDValue Op, SelectionDAG &DAG) LowerUMUL_LOHI(SDValue Op, SelectionDAG &DAG) const
{ {
assert(Op.getValueType() == MVT::i32 && Op.getOpcode() == ISD::UMUL_LOHI && assert(Op.getValueType() == MVT::i32 && Op.getOpcode() == ISD::UMUL_LOHI &&
"Unexpected operand to lower!"); "Unexpected operand to lower!");
@ -647,7 +648,7 @@ isADDADDMUL(SDValue Op, SDValue &Mul0, SDValue &Mul1, SDValue &Addend0,
} }
SDValue XCoreTargetLowering:: SDValue XCoreTargetLowering::
TryExpandADDWithMul(SDNode *N, SelectionDAG &DAG) TryExpandADDWithMul(SDNode *N, SelectionDAG &DAG) const
{ {
SDValue Mul; SDValue Mul;
SDValue Other; SDValue Other;
@ -707,7 +708,7 @@ TryExpandADDWithMul(SDNode *N, SelectionDAG &DAG)
} }
SDValue XCoreTargetLowering:: SDValue XCoreTargetLowering::
ExpandADDSUB(SDNode *N, SelectionDAG &DAG) ExpandADDSUB(SDNode *N, SelectionDAG &DAG) const
{ {
assert(N->getValueType(0) == MVT::i64 && assert(N->getValueType(0) == MVT::i64 &&
(N->getOpcode() == ISD::ADD || N->getOpcode() == ISD::SUB) && (N->getOpcode() == ISD::ADD || N->getOpcode() == ISD::SUB) &&
@ -747,7 +748,7 @@ ExpandADDSUB(SDNode *N, SelectionDAG &DAG)
} }
SDValue XCoreTargetLowering:: SDValue XCoreTargetLowering::
LowerVAARG(SDValue Op, SelectionDAG &DAG) LowerVAARG(SDValue Op, SelectionDAG &DAG) const
{ {
llvm_unreachable("unimplemented"); llvm_unreachable("unimplemented");
// FIX Arguments passed by reference need a extra dereference. // FIX Arguments passed by reference need a extra dereference.
@ -769,7 +770,7 @@ LowerVAARG(SDValue Op, SelectionDAG &DAG)
} }
SDValue XCoreTargetLowering:: SDValue XCoreTargetLowering::
LowerVASTART(SDValue Op, SelectionDAG &DAG) LowerVASTART(SDValue Op, SelectionDAG &DAG) const
{ {
DebugLoc dl = Op.getDebugLoc(); DebugLoc dl = Op.getDebugLoc();
// vastart stores the address of the VarArgsFrameIndex slot into the // vastart stores the address of the VarArgsFrameIndex slot into the
@ -782,7 +783,8 @@ LowerVASTART(SDValue Op, SelectionDAG &DAG)
false, false, 0); false, false, 0);
} }
SDValue XCoreTargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) { SDValue XCoreTargetLowering::LowerFRAMEADDR(SDValue Op,
SelectionDAG &DAG) const {
DebugLoc dl = Op.getDebugLoc(); DebugLoc dl = Op.getDebugLoc();
// Depths > 0 not supported yet! // Depths > 0 not supported yet!
if (cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue() > 0) if (cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue() > 0)
@ -812,7 +814,7 @@ XCoreTargetLowering::LowerCall(SDValue Chain, SDValue Callee,
const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<ISD::OutputArg> &Outs,
const SmallVectorImpl<ISD::InputArg> &Ins, const SmallVectorImpl<ISD::InputArg> &Ins,
DebugLoc dl, SelectionDAG &DAG, DebugLoc dl, SelectionDAG &DAG,
SmallVectorImpl<SDValue> &InVals) { SmallVectorImpl<SDValue> &InVals) const {
// XCore target does not yet support tail call optimization. // XCore target does not yet support tail call optimization.
isTailCall = false; isTailCall = false;
@ -839,7 +841,7 @@ XCoreTargetLowering::LowerCCCCallTo(SDValue Chain, SDValue Callee,
const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<ISD::OutputArg> &Outs,
const SmallVectorImpl<ISD::InputArg> &Ins, const SmallVectorImpl<ISD::InputArg> &Ins,
DebugLoc dl, SelectionDAG &DAG, DebugLoc dl, SelectionDAG &DAG,
SmallVectorImpl<SDValue> &InVals) { SmallVectorImpl<SDValue> &InVals) const {
// Analyze operands of the call, assigning locations to each operand. // Analyze operands of the call, assigning locations to each operand.
SmallVector<CCValAssign, 16> ArgLocs; SmallVector<CCValAssign, 16> ArgLocs;
@ -962,7 +964,7 @@ XCoreTargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
CallingConv::ID CallConv, bool isVarArg, CallingConv::ID CallConv, bool isVarArg,
const SmallVectorImpl<ISD::InputArg> &Ins, const SmallVectorImpl<ISD::InputArg> &Ins,
DebugLoc dl, SelectionDAG &DAG, DebugLoc dl, SelectionDAG &DAG,
SmallVectorImpl<SDValue> &InVals) { SmallVectorImpl<SDValue> &InVals) const {
// Assign locations to each value returned by this call. // Assign locations to each value returned by this call.
SmallVector<CCValAssign, 16> RVLocs; SmallVector<CCValAssign, 16> RVLocs;
@ -994,7 +996,8 @@ XCoreTargetLowering::LowerFormalArguments(SDValue Chain,
const SmallVectorImpl<ISD::InputArg> &Ins, const SmallVectorImpl<ISD::InputArg> &Ins,
DebugLoc dl, DebugLoc dl,
SelectionDAG &DAG, SelectionDAG &DAG,
SmallVectorImpl<SDValue> &InVals) { SmallVectorImpl<SDValue> &InVals)
const {
switch (CallConv) switch (CallConv)
{ {
default: default:
@ -1018,7 +1021,7 @@ XCoreTargetLowering::LowerCCCArguments(SDValue Chain,
&Ins, &Ins,
DebugLoc dl, DebugLoc dl,
SelectionDAG &DAG, SelectionDAG &DAG,
SmallVectorImpl<SDValue> &InVals) { SmallVectorImpl<SDValue> &InVals) const {
MachineFunction &MF = DAG.getMachineFunction(); MachineFunction &MF = DAG.getMachineFunction();
MachineFrameInfo *MFI = MF.getFrameInfo(); MachineFrameInfo *MFI = MF.getFrameInfo();
MachineRegisterInfo &RegInfo = MF.getRegInfo(); MachineRegisterInfo &RegInfo = MF.getRegInfo();
@ -1132,7 +1135,7 @@ bool XCoreTargetLowering::
CanLowerReturn(CallingConv::ID CallConv, bool isVarArg, CanLowerReturn(CallingConv::ID CallConv, bool isVarArg,
const SmallVectorImpl<EVT> &OutTys, const SmallVectorImpl<EVT> &OutTys,
const SmallVectorImpl<ISD::ArgFlagsTy> &ArgsFlags, const SmallVectorImpl<ISD::ArgFlagsTy> &ArgsFlags,
SelectionDAG &DAG) { SelectionDAG &DAG) const {
SmallVector<CCValAssign, 16> RVLocs; SmallVector<CCValAssign, 16> RVLocs;
CCState CCInfo(CallConv, isVarArg, getTargetMachine(), CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
RVLocs, *DAG.getContext()); RVLocs, *DAG.getContext());
@ -1143,7 +1146,7 @@ SDValue
XCoreTargetLowering::LowerReturn(SDValue Chain, XCoreTargetLowering::LowerReturn(SDValue Chain,
CallingConv::ID CallConv, bool isVarArg, CallingConv::ID CallConv, bool isVarArg,
const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<ISD::OutputArg> &Outs,
DebugLoc dl, SelectionDAG &DAG) { DebugLoc dl, SelectionDAG &DAG) const {
// CCValAssign - represent the assignment of // CCValAssign - represent the assignment of
// the return value to a location // the return value to a location

52
llvm/lib/Target/XCore/XCoreISelLowering.h
View File

@ -83,13 +83,13 @@ namespace llvm {
virtual unsigned getJumpTableEncoding() const; virtual unsigned getJumpTableEncoding() const;
/// LowerOperation - Provide custom lowering hooks for some operations. /// LowerOperation - Provide custom lowering hooks for some operations.
virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG); virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
/// ReplaceNodeResults - Replace the results of node with an illegal result /// ReplaceNodeResults - Replace the results of node with an illegal result
/// type with new values built out of custom code. /// type with new values built out of custom code.
/// ///
virtual void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results, virtual void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results,
SelectionDAG &DAG); SelectionDAG &DAG) const;
/// getTargetNodeName - This method returns the name of a target specific /// getTargetNodeName - This method returns the name of a target specific
// DAG node. // DAG node.
@ -115,37 +115,37 @@ namespace llvm {
bool isVarArg, bool isVarArg,
const SmallVectorImpl<ISD::InputArg> &Ins, const SmallVectorImpl<ISD::InputArg> &Ins,
DebugLoc dl, SelectionDAG &DAG, DebugLoc dl, SelectionDAG &DAG,
SmallVectorImpl<SDValue> &InVals); SmallVectorImpl<SDValue> &InVals) const;
SDValue LowerCCCCallTo(SDValue Chain, SDValue Callee, SDValue LowerCCCCallTo(SDValue Chain, SDValue Callee,
CallingConv::ID CallConv, bool isVarArg, CallingConv::ID CallConv, bool isVarArg,
bool isTailCall, bool isTailCall,
const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<ISD::OutputArg> &Outs,
const SmallVectorImpl<ISD::InputArg> &Ins, const SmallVectorImpl<ISD::InputArg> &Ins,
DebugLoc dl, SelectionDAG &DAG, DebugLoc dl, SelectionDAG &DAG,
SmallVectorImpl<SDValue> &InVals); SmallVectorImpl<SDValue> &InVals) const;
SDValue LowerCallResult(SDValue Chain, SDValue InFlag, SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
CallingConv::ID CallConv, bool isVarArg, CallingConv::ID CallConv, bool isVarArg,
const SmallVectorImpl<ISD::InputArg> &Ins, const SmallVectorImpl<ISD::InputArg> &Ins,
DebugLoc dl, SelectionDAG &DAG, DebugLoc dl, SelectionDAG &DAG,
SmallVectorImpl<SDValue> &InVals); SmallVectorImpl<SDValue> &InVals) const;
SDValue getReturnAddressFrameIndex(SelectionDAG &DAG); SDValue getReturnAddressFrameIndex(SelectionDAG &DAG) const;
SDValue getGlobalAddressWrapper(SDValue GA, const GlobalValue *GV, SDValue getGlobalAddressWrapper(SDValue GA, const GlobalValue *GV,
SelectionDAG &DAG); SelectionDAG &DAG) const;
// Lower Operand specifics // Lower Operand specifics
SDValue LowerLOAD(SDValue Op, SelectionDAG &DAG); SDValue LowerLOAD(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerSTORE(SDValue Op, SelectionDAG &DAG); SDValue LowerSTORE(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG); SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG); SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG); SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG); SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerBR_JT(SDValue Op, SelectionDAG &DAG); SDValue LowerBR_JT(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG); SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerVAARG(SDValue Op, SelectionDAG &DAG); SDValue LowerVAARG(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG); SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerUMUL_LOHI(SDValue Op, SelectionDAG &DAG); SDValue LowerUMUL_LOHI(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerSMUL_LOHI(SDValue Op, SelectionDAG &DAG); SDValue LowerSMUL_LOHI(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG); SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
// Inline asm support // Inline asm support
std::vector<unsigned> std::vector<unsigned>
@ -153,8 +153,8 @@ namespace llvm {
EVT VT) const; EVT VT) const;
// Expand specifics // Expand specifics
SDValue TryExpandADDWithMul(SDNode *Op, SelectionDAG &DAG); SDValue TryExpandADDWithMul(SDNode *Op, SelectionDAG &DAG) const;
SDValue ExpandADDSUB(SDNode *Op, SelectionDAG &DAG); SDValue ExpandADDSUB(SDNode *Op, SelectionDAG &DAG) const;
virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const; virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
@ -171,7 +171,7 @@ namespace llvm {
bool isVarArg, bool isVarArg,
const SmallVectorImpl<ISD::InputArg> &Ins, const SmallVectorImpl<ISD::InputArg> &Ins,
DebugLoc dl, SelectionDAG &DAG, DebugLoc dl, SelectionDAG &DAG,
SmallVectorImpl<SDValue> &InVals); SmallVectorImpl<SDValue> &InVals) const;
virtual SDValue virtual SDValue
LowerCall(SDValue Chain, SDValue Callee, LowerCall(SDValue Chain, SDValue Callee,
@ -180,19 +180,19 @@ namespace llvm {
const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<ISD::OutputArg> &Outs,
const SmallVectorImpl<ISD::InputArg> &Ins, const SmallVectorImpl<ISD::InputArg> &Ins,
DebugLoc dl, SelectionDAG &DAG, DebugLoc dl, SelectionDAG &DAG,
SmallVectorImpl<SDValue> &InVals); SmallVectorImpl<SDValue> &InVals) const;
virtual SDValue virtual SDValue
LowerReturn(SDValue Chain, LowerReturn(SDValue Chain,
CallingConv::ID CallConv, bool isVarArg, CallingConv::ID CallConv, bool isVarArg,
const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<ISD::OutputArg> &Outs,
DebugLoc dl, SelectionDAG &DAG); DebugLoc dl, SelectionDAG &DAG) const;
virtual bool virtual bool
CanLowerReturn(CallingConv::ID CallConv, bool isVarArg, CanLowerReturn(CallingConv::ID CallConv, bool isVarArg,
const SmallVectorImpl<EVT> &OutTys, const SmallVectorImpl<EVT> &OutTys,
const SmallVectorImpl<ISD::ArgFlagsTy> &ArgsFlags, const SmallVectorImpl<ISD::ArgFlagsTy> &ArgsFlags,
SelectionDAG &DAG); SelectionDAG &DAG) const;
}; };
} }

4
llvm/lib/Target/XCore/XCoreTargetMachine.h
View File

@ -36,8 +36,8 @@ public:
virtual const XCoreInstrInfo *getInstrInfo() const { return &InstrInfo; } virtual const XCoreInstrInfo *getInstrInfo() const { return &InstrInfo; }
virtual const XCoreFrameInfo *getFrameInfo() const { return &FrameInfo; } virtual const XCoreFrameInfo *getFrameInfo() const { return &FrameInfo; }
virtual const XCoreSubtarget *getSubtargetImpl() const { return &Subtarget; } virtual const XCoreSubtarget *getSubtargetImpl() const { return &Subtarget; }
virtual XCoreTargetLowering *getTargetLowering() const { virtual const XCoreTargetLowering *getTargetLowering() const {
return const_cast<XCoreTargetLowering*>(&TLInfo); return &TLInfo;
} }
virtual const TargetRegisterInfo *getRegisterInfo() const { virtual const TargetRegisterInfo *getRegisterInfo() const {