[XCore] Add missing u10 / lu10 instructions.

These instructions are not targeted by the compiler but they are
needed for the MC layer.

llvm-svn: 175404

llvm/lib/Target/XCore/XCoreInstrInfo.td

@@ -661,7 +661,6 @@ let Uses = [SP], Defs = [SP], mayLoad = 1 in
 defm KRESTSP : FU6_LU6_np<0b0111101111, "krestsp">;
 
 // U10
-// TODO ldwcpl, blacp
 
 let Defs = [R11], isReMaterializable = 1, neverHasSideEffects = 1 in
 def LDAPF_u10 : _FU10<0b110110, (outs), (ins i32imm:$a), "ldap r11, $a", []>;
@@ -677,6 +676,10 @@ def LDAPF_lu10_ba : _FLU10<0b110110, (outs), (ins i32imm:$a), "ldap r11, $a",
 let isCall=1,
 // All calls clobber the link register and the non-callee-saved registers:
 Defs = [R0, R1, R2, R3, R11, LR], Uses = [SP] in {
+def BLACP_u10 : _FU10<0b111000, (outs), (ins i32imm:$a), "bla cp[$a]", []>;
+
+def BLACP_lu10 : _FLU10<0b111000, (outs), (ins i32imm:$a), "bla cp[$a]", []>;
+
 def BLRF_u10 : _FU10<0b110100, (outs), (ins calltarget:$a), "bl $a",
                      [(XCoreBranchLink immU10:$a)]>;
 
@@ -684,6 +687,14 @@ def BLRF_lu10 : _FLU10<0b110100, (outs), (ins calltarget:$a), "bl $a",
                        [(XCoreBranchLink immU20:$a)]>;
 }
 
+let Defs = [R11], mayLoad = 1, isReMaterializable = 1,
+    neverHasSideEffects = 1 in {
+def LDWCP_u10 : _FU10<0b111001, (outs), (ins i32imm:$a), "ldw r11, cp[$a]", []>;
+
+def LDWCP_lu10 : _FLU10<0b111001, (outs), (ins i32imm:$a), "ldw r11, cp[$a]",
+                        []>;
+}
+
 // Two operand short
 // TODO eet, eef, tsetmr
 def NOT : _F2R<0b100010, (outs GRRegs:$dst), (ins GRRegs:$b),

llvm/test/MC/Disassembler/XCore/xcore.txt

@@ -589,6 +589,18 @@
 # CHECK: bl 38631
 0x25 0xf0 0xe7 0xd2
 
+# CHECK: bla cp[500]
+0xf4 0xe1
+
+# CHECK: bla cp[413742]
+0x94 0xf1 0x2e 0xe0
+
+# CHECK: ldw r11, cp[132]
+0x84 0xe4
+
+# CHECK: ldw r11, cp[3444]
+0x35 0xf0 0xf4 0x6e
+
 # l6r instructions
 
 # CHECK: lmul r11, r0, r2, r5, r8, r10