forked from OSchip/llvm-project
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ea686e2845
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@ -80,24 +80,26 @@ class Scheduler : public HardwareUnit {
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// the instruction stage (see Instruction::InstrStage).
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//
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// An Instruction dispatched to the Scheduler is added to the WaitSet if not
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// all its register operands are available, and at least one latency is unknown.
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// By construction, the WaitSet only contains instructions that are in the
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// IS_DISPATCHED stage.
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// all its register operands are available, and at least one latency is
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// unknown. By construction, the WaitSet only contains instructions that are
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// in the IS_DISPATCHED stage.
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//
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// An Instruction transitions from the WaitSet to the PendingSet if the
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// instruction is not ready yet, but the latency of every register read is known.
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// Instructions in the PendingSet are expected to be in the IS_PENDING stage.
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// instruction is not ready yet, but the latency of every register read is
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// known. Instructions in the PendingSet can only be in the IS_PENDING or
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// IS_READY stage. Only IS_READY instructions that are waiting on memory
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// dependencies can be added to the PendingSet.
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//
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// Instructions in the PendingSet are immediately dominated only by
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// instructions that have already been issued to the underlying pipelines.
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// In the presence of bottlenecks caused by data dependencies, the PendingSet
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// can be inspected to identify problematic data dependencies between
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// instructions that have already been issued to the underlying pipelines. In
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// the presence of bottlenecks caused by data dependencies, the PendingSet can
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// be inspected to identify problematic data dependencies between
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// instructions.
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//
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// An instruction is moved to the ReadySet when all register operands become
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// available, and all memory dependencies are met. Instructions that are
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// moved from the PendingSet to the ReadySet transition in state from
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// 'IS_PENDING' to 'IS_READY'.
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// moved from the PendingSet to the ReadySet must transition to the 'IS_READY'
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// stage.
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//
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// On every cycle, the Scheduler checks if it can promote instructions from the
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// PendingSet to the ReadySet.
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@ -127,7 +127,8 @@ void Instruction::dispatch(unsigned RCUToken) {
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RCUTokenID = RCUToken;
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// Check if input operands are already available.
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update();
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if (updateDispatched())
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updatePending();
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}
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void Instruction::execute() {
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