forked from OSchip/llvm-project
[x86] add tests for masked loads with constant masks
llvm-svn: 262758
This commit is contained in:
Sanjay Patel
parent
243fe2b3a0
commit
216b275994
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@ -935,33 +935,210 @@ define <4 x float> @test19(<4 x i32> %trigger, <4 x float>* %addr) {
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ret <4 x float> %res
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}
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define <4 x float> @test20(<4 x i32> %trigger, <4 x float>* %addr, <4 x float> %src0) {
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; AVX-LABEL: test20:
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;;; Loads with Constant Masks - these should be optimized to use something other than a variable blend.
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; 128-bit FP vectors are supported with AVX.
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define <4 x float> @mload_constmask_v4f32(<4 x float>* %addr, <4 x float> %dst) {
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; AVX-LABEL: mload_constmask_v4f32:
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; AVX: ## BB#0:
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; AVX-NEXT: vmovaps {{.*#+}} xmm0 = [4294967295,0,4294967295,4294967295]
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; AVX-NEXT: vmaskmovps (%rdi), %xmm0, %xmm2
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; AVX-NEXT: vblendvps %xmm0, %xmm2, %xmm1, %xmm0
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; AVX-NEXT: vmovaps {{.*#+}} xmm1 = [4294967295,0,4294967295,4294967295]
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; AVX-NEXT: vmaskmovps (%rdi), %xmm1, %xmm2
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; AVX-NEXT: vblendvps %xmm1, %xmm2, %xmm0, %xmm0
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; AVX-NEXT: retq
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;
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; AVX512F-LABEL: test20:
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; AVX512F-LABEL: mload_constmask_v4f32:
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; AVX512F: ## BB#0:
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; AVX512F-NEXT: vmovaps {{.*#+}} xmm0 = [4294967295,0,4294967295,4294967295]
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; AVX512F-NEXT: vmaskmovps (%rdi), %xmm0, %xmm2
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; AVX512F-NEXT: vblendvps %xmm0, %xmm2, %xmm1, %xmm0
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; AVX512F-NEXT: vmovaps {{.*#+}} xmm1 = [4294967295,0,4294967295,4294967295]
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; AVX512F-NEXT: vmaskmovps (%rdi), %xmm1, %xmm2
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; AVX512F-NEXT: vblendvps %xmm1, %xmm2, %xmm0, %xmm0
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; AVX512F-NEXT: retq
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;
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; SKX-LABEL: test20:
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; SKX-LABEL: mload_constmask_v4f32:
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; SKX: ## BB#0:
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; SKX-NEXT: movb $13, %al
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; SKX-NEXT: kmovw %eax, %k1
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; SKX-NEXT: vmovaps (%rdi), %xmm1 {%k1}
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; SKX-NEXT: vmovaps %zmm1, %zmm0
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; SKX-NEXT: vmovups (%rdi), %xmm0 {%k1}
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; SKX-NEXT: retq
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%mask = icmp eq <4 x i32> %trigger, zeroinitializer
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%res = call <4 x float> @llvm.masked.load.v4f32(<4 x float>* %addr, i32 16, <4 x i1><i1 true, i1 false, i1 true, i1 true>, <4 x float> %src0)
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%res = call <4 x float> @llvm.masked.load.v4f32(<4 x float>* %addr, i32 4, <4 x i1> <i1 1, i1 0, i1 1, i1 1>, <4 x float> %dst)
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ret <4 x float> %res
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}
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; 128-bit integer vectors are supported with AVX2.
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define <4 x i32> @mload_constmask_v4i32(<4 x i32>* %addr, <4 x i32> %dst) {
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; AVX1-LABEL: mload_constmask_v4i32:
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; AVX1: ## BB#0:
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; AVX1-NEXT: vmovaps {{.*#+}} xmm1 = [0,4294967295,4294967295,4294967295]
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; AVX1-NEXT: vmaskmovps (%rdi), %xmm1, %xmm2
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; AVX1-NEXT: vblendvps %xmm1, %xmm2, %xmm0, %xmm0
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; AVX1-NEXT: retq
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;
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; AVX2-LABEL: mload_constmask_v4i32:
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; AVX2: ## BB#0:
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; AVX2-NEXT: vmovdqa {{.*#+}} xmm1 = [0,4294967295,4294967295,4294967295]
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; AVX2-NEXT: vpmaskmovd (%rdi), %xmm1, %xmm2
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; AVX2-NEXT: vblendvps %xmm1, %xmm2, %xmm0, %xmm0
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; AVX2-NEXT: retq
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;
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; AVX512F-LABEL: mload_constmask_v4i32:
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; AVX512F: ## BB#0:
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; AVX512F-NEXT: vmovdqa {{.*#+}} xmm1 = [0,4294967295,4294967295,4294967295]
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; AVX512F-NEXT: vpmaskmovd (%rdi), %xmm1, %xmm2
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; AVX512F-NEXT: vblendvps %xmm1, %xmm2, %xmm0, %xmm0
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; AVX512F-NEXT: retq
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;
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; SKX-LABEL: mload_constmask_v4i32:
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; SKX: ## BB#0:
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; SKX-NEXT: movb $14, %al
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; SKX-NEXT: kmovw %eax, %k1
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; SKX-NEXT: vmovdqu32 (%rdi), %xmm0 {%k1}
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; SKX-NEXT: retq
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%res = call <4 x i32> @llvm.masked.load.v4i32(<4 x i32>* %addr, i32 4, <4 x i1> <i1 0, i1 1, i1 1, i1 1>, <4 x i32> %dst)
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ret <4 x i32> %res
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}
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; 256-bit FP vectors are supported with AVX.
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define <8 x float> @mload_constmask_v8f32(<8 x float>* %addr, <8 x float> %dst) {
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; AVX-LABEL: mload_constmask_v8f32:
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; AVX: ## BB#0:
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; AVX-NEXT: vmovaps {{.*#+}} ymm1 = [4294967295,4294967295,4294967295,0,0,0,0,0]
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; AVX-NEXT: vmaskmovps (%rdi), %ymm1, %ymm2
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; AVX-NEXT: vblendvps %ymm1, %ymm2, %ymm0, %ymm0
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; AVX-NEXT: retq
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;
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; AVX512F-LABEL: mload_constmask_v8f32:
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; AVX512F: ## BB#0:
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; AVX512F-NEXT: movw $7, %ax
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; AVX512F-NEXT: kmovw %eax, %k1
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; AVX512F-NEXT: vmovups (%rdi), %zmm0 {%k1}
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; AVX512F-NEXT: retq
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;
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; SKX-LABEL: mload_constmask_v8f32:
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; SKX: ## BB#0:
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; SKX-NEXT: movb $7, %al
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; SKX-NEXT: kmovw %eax, %k1
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; SKX-NEXT: vmovups (%rdi), %ymm0 {%k1}
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; SKX-NEXT: retq
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%res = call <8 x float> @llvm.masked.load.v8f32(<8 x float>* %addr, i32 4, <8 x i1> <i1 1, i1 1, i1 1, i1 0, i1 0, i1 0, i1 0, i1 0>, <8 x float> %dst)
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ret <8 x float> %res
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}
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define <4 x double> @mload_constmask_v4f64(<4 x double>* %addr, <4 x double> %dst) {
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; AVX-LABEL: mload_constmask_v4f64:
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; AVX: ## BB#0:
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; AVX-NEXT: vmovapd {{.*#+}} ymm1 = [18446744073709551615,18446744073709551615,18446744073709551615,0]
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; AVX-NEXT: vmaskmovpd (%rdi), %ymm1, %ymm2
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; AVX-NEXT: vblendvpd %ymm1, %ymm2, %ymm0, %ymm0
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; AVX-NEXT: retq
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;
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; AVX512F-LABEL: mload_constmask_v4f64:
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; AVX512F: ## BB#0:
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; AVX512F-NEXT: vmovapd {{.*#+}} ymm1 = [18446744073709551615,18446744073709551615,18446744073709551615,0]
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; AVX512F-NEXT: vmaskmovpd (%rdi), %ymm1, %ymm2
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; AVX512F-NEXT: vblendvpd %ymm1, %ymm2, %ymm0, %ymm0
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; AVX512F-NEXT: retq
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;
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; SKX-LABEL: mload_constmask_v4f64:
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; SKX: ## BB#0:
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; SKX-NEXT: movb $7, %al
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; SKX-NEXT: kmovw %eax, %k1
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; SKX-NEXT: vmovupd (%rdi), %ymm0 {%k1}
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; SKX-NEXT: retq
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%res = call <4 x double> @llvm.masked.load.v4f64(<4 x double>* %addr, i32 4, <4 x i1> <i1 1, i1 1, i1 1, i1 0>, <4 x double> %dst)
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ret <4 x double> %res
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}
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; 256-bit integer vectors are supported with AVX2.
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define <8 x i32> @mload_constmask_v8i32(<8 x i32>* %addr, <8 x i32> %dst) {
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; AVX1-LABEL: mload_constmask_v8i32:
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; AVX1: ## BB#0:
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; AVX1-NEXT: vmovaps {{.*#+}} ymm1 = [4294967295,4294967295,4294967295,0,0,0,0,4294967295]
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; AVX1-NEXT: vmaskmovps (%rdi), %ymm1, %ymm2
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; AVX1-NEXT: vblendvps %ymm1, %ymm2, %ymm0, %ymm0
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; AVX1-NEXT: retq
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;
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; AVX2-LABEL: mload_constmask_v8i32:
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; AVX2: ## BB#0:
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; AVX2-NEXT: vmovdqa {{.*#+}} ymm1 = [4294967295,4294967295,4294967295,0,0,0,0,4294967295]
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; AVX2-NEXT: vpmaskmovd (%rdi), %ymm1, %ymm2
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; AVX2-NEXT: vblendvps %ymm1, %ymm2, %ymm0, %ymm0
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; AVX2-NEXT: retq
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;
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; AVX512F-LABEL: mload_constmask_v8i32:
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; AVX512F: ## BB#0:
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; AVX512F-NEXT: movw $135, %ax
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; AVX512F-NEXT: kmovw %eax, %k1
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; AVX512F-NEXT: vmovdqu32 (%rdi), %zmm0 {%k1}
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; AVX512F-NEXT: retq
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;
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; SKX-LABEL: mload_constmask_v8i32:
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; SKX: ## BB#0:
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; SKX-NEXT: movb $-121, %al
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; SKX-NEXT: kmovw %eax, %k1
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; SKX-NEXT: vmovdqu32 (%rdi), %ymm0 {%k1}
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; SKX-NEXT: retq
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%res = call <8 x i32> @llvm.masked.load.v8i32(<8 x i32>* %addr, i32 4, <8 x i1> <i1 1, i1 1, i1 1, i1 0, i1 0, i1 0, i1 0, i1 1>, <8 x i32> %dst)
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ret <8 x i32> %res
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}
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define <4 x i64> @mload_constmask_v4i64(<4 x i64>* %addr, <4 x i64> %dst) {
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; AVX1-LABEL: mload_constmask_v4i64:
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; AVX1: ## BB#0:
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; AVX1-NEXT: vmovapd {{.*#+}} ymm1 = [18446744073709551615,0,0,18446744073709551615]
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; AVX1-NEXT: vmaskmovpd (%rdi), %ymm1, %ymm2
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; AVX1-NEXT: vblendvpd %ymm1, %ymm2, %ymm0, %ymm0
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; AVX1-NEXT: retq
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;
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; AVX2-LABEL: mload_constmask_v4i64:
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; AVX2: ## BB#0:
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; AVX2-NEXT: vmovdqa {{.*#+}} ymm1 = [18446744073709551615,0,0,18446744073709551615]
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; AVX2-NEXT: vpmaskmovq (%rdi), %ymm1, %ymm2
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; AVX2-NEXT: vblendvpd %ymm1, %ymm2, %ymm0, %ymm0
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; AVX2-NEXT: retq
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;
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; AVX512F-LABEL: mload_constmask_v4i64:
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; AVX512F: ## BB#0:
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; AVX512F-NEXT: vmovdqa {{.*#+}} ymm1 = [18446744073709551615,0,0,18446744073709551615]
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; AVX512F-NEXT: vpmaskmovq (%rdi), %ymm1, %ymm2
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; AVX512F-NEXT: vblendvpd %ymm1, %ymm2, %ymm0, %ymm0
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; AVX512F-NEXT: retq
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;
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; SKX-LABEL: mload_constmask_v4i64:
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; SKX: ## BB#0:
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; SKX-NEXT: movb $9, %al
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; SKX-NEXT: kmovw %eax, %k1
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; SKX-NEXT: vmovdqu64 (%rdi), %ymm0 {%k1}
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; SKX-NEXT: retq
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%res = call <4 x i64> @llvm.masked.load.v4i64(<4 x i64>* %addr, i32 4, <4 x i1> <i1 1, i1 0, i1 0, i1 1>, <4 x i64> %dst)
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ret <4 x i64> %res
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}
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; 512-bit FP vectors are supported with AVX512.
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define <8 x double> @mload_constmask_v8f64(<8 x double>* %addr, <8 x double> %dst) {
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; AVX-LABEL: mload_constmask_v8f64:
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; AVX: ## BB#0:
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; AVX-NEXT: vmovapd {{.*#+}} ymm2 = [18446744073709551615,18446744073709551615,18446744073709551615,0]
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; AVX-NEXT: vmaskmovpd (%rdi), %ymm2, %ymm3
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; AVX-NEXT: vblendvpd %ymm2, %ymm3, %ymm0, %ymm0
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; AVX-NEXT: vmovapd {{.*#+}} ymm2 = [0,0,0,18446744073709551615]
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; AVX-NEXT: vmaskmovpd 32(%rdi), %ymm2, %ymm3
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; AVX-NEXT: vblendvpd %ymm2, %ymm3, %ymm1, %ymm1
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; AVX-NEXT: retq
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;
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; AVX512-LABEL: mload_constmask_v8f64:
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; AVX512: ## BB#0:
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; AVX512-NEXT: movb $-121, %al
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; AVX512-NEXT: kmovw %eax, %k1
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; AVX512-NEXT: vmovupd (%rdi), %zmm0 {%k1}
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; AVX512-NEXT: retq
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%res = call <8 x double> @llvm.masked.load.v8f64(<8 x double>* %addr, i32 4, <8 x i1> <i1 1, i1 1, i1 1, i1 0, i1 0, i1 0, i1 0, i1 1>, <8 x double> %dst)
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ret <8 x double> %res
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}
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define void @test21(<4 x i32> %trigger, <4 x i32>* %addr, <4 x i32> %val) {
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; AVX1-LABEL: test21:
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; AVX1: ## BB#0:
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