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[ARM] Select a number of fp16 rounding functions 

This add patterns for fp16 round and ceil etc. Same as the float and double
patterns.

Differential Revision: https://reviews.llvm.org/D62326

llvm-svn: 361718
This commit is contained in:
David Green 2019-05-26 11:13:00 +00:00
parent c9f4b7d201
commit 21542cd6f4
4 changed files with 72 additions and 59 deletions
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2
llvm/lib/Target/ARM/ARMISelLowering.cpp
View File

@ -1156,6 +1156,8 @@ ARMTargetLowering::ARMTargetLowering(const TargetMachine &TM,
setOperationAction(ISD::FLOG, MVT::f16, Promote);
setOperationAction(ISD::FLOG10, MVT::f16, Promote);
setOperationAction(ISD::FLOG2, MVT::f16, Promote);
setOperationAction(ISD::FROUND, MVT::f16, Legal);
}
if (Subtarget->hasNEON()) {

8
llvm/lib/Target/ARM/ARMInstrVFP.td
View File

@ -930,9 +930,9 @@ def VNEGH : AHuI<0b11101, 0b11, 0b0001, 0b01, 0,
multiclass vrint_inst_zrx<string opc, bit op, bit op2, SDPatternOperator node> {
def H : AHuI<0b11101, 0b11, 0b0110, 0b11, 0,
(outs SPR:$Sd), (ins SPR:$Sm),
(outs HPR:$Sd), (ins HPR:$Sm),
NoItinerary, !strconcat("vrint", opc), ".f16\t$Sd, $Sm",
[]>,
[(set (f16 HPR:$Sd), (node (f16 HPR:$Sm)))]>,
Requires<[HasFullFP16]> {
let Inst{7} = op2;
let Inst{16} = op;
@ -975,9 +975,9 @@ multiclass vrint_inst_anpm<string opc, bits<2> rm,
let PostEncoderMethod = "", DecoderNamespace = "VFPV8",
isUnpredicable = 1 in {
def H : AHuInp<0b11101, 0b11, 0b1000, 0b01, 0,
(outs SPR:$Sd), (ins SPR:$Sm),
(outs HPR:$Sd), (ins HPR:$Sm),
NoItinerary, !strconcat("vrint", opc, ".f16\t$Sd, $Sm"),
[]>,
[(set (f16 HPR:$Sd), (node (f16 HPR:$Sm)))]>,
Requires<[HasFullFP16]> {
let Inst{17-16} = rm;
}

108
llvm/test/CodeGen/ARM/fp16-fullfp16.ll
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@ -488,53 +488,77 @@ define void @test_copysign(half* %p, half* %q) {
ret void
}
; FIXME
;define void @test_floor(half* %p) {
; %a = load half, half* %p, align 2
; %r = call half @llvm.floor.f16(half %a)
; store half %r, half* %p
; ret void
;}
define void @test_floor(half* %p) {
; CHECK-LABEL: test_floor:
; CHECK: vldr.16 s0, [r0]
; CHECK-NEXT: vrintm.f16 s0, s0
; CHECK-NEXT: vstr.16 s0, [r0]
; CHECK-NEXT: bx lr
%a = load half, half* %p, align 2
%r = call half @llvm.floor.f16(half %a)
store half %r, half* %p
ret void
}
; FIXME
;define void @test_ceil(half* %p) {
; %a = load half, half* %p, align 2
; %r = call half @llvm.ceil.f16(half %a)
; store half %r, half* %p
; ret void
;}
define void @test_ceil(half* %p) {
; CHECK-LABEL: test_ceil:
; CHECK: vldr.16 s0, [r0]
; CHECK-NEXT: vrintp.f16 s0, s0
; CHECK-NEXT: vstr.16 s0, [r0]
; CHECK-NEXT: bx lr
%a = load half, half* %p, align 2
%r = call half @llvm.ceil.f16(half %a)
store half %r, half* %p
ret void
}
; FIXME
;define void @test_trunc(half* %p) {
; %a = load half, half* %p, align 2
; %r = call half @llvm.trunc.f16(half %a)
; store half %r, half* %p
; ret void
;}
define void @test_trunc(half* %p) {
; CHECK-LABEL: test_trunc:
; CHECK: vldr.16 s0, [r0]
; CHECK-NEXT: vrintz.f16 s0, s0
; CHECK-NEXT: vstr.16 s0, [r0]
; CHECK-NEXT: bx lr
%a = load half, half* %p, align 2
%r = call half @llvm.trunc.f16(half %a)
store half %r, half* %p
ret void
}
; FIXME
;define void @test_rint(half* %p) {
; %a = load half, half* %p, align 2
; %r = call half @llvm.rint.f16(half %a)
; store half %r, half* %p
; ret void
;}
define void @test_rint(half* %p) {
; CHECK-LABEL: test_rint:
; CHECK: vldr.16 s0, [r0]
; CHECK-NEXT: vrintx.f16 s0, s0
; CHECK-NEXT: vstr.16 s0, [r0]
; CHECK-NEXT: bx lr
%a = load half, half* %p, align 2
%r = call half @llvm.rint.f16(half %a)
store half %r, half* %p
ret void
}
; FIXME
;define void @test_nearbyint(half* %p) {
; %a = load half, half* %p, align 2
; %r = call half @llvm.nearbyint.f16(half %a)
; store half %r, half* %p
; ret void
;}
define void @test_nearbyint(half* %p) {
; CHECK-LABEL: test_nearbyint:
; CHECK: vldr.16 s0, [r0]
; CHECK-NEXT: vrintr.f16 s0, s0
; CHECK-NEXT: vstr.16 s0, [r0]
; CHECK-NEXT: bx lr
%a = load half, half* %p, align 2
%r = call half @llvm.nearbyint.f16(half %a)
store half %r, half* %p
ret void
}
; FIXME
;define void @test_round(half* %p) {
; %a = load half, half* %p, align 2
; %r = call half @llvm.round.f16(half %a)
; store half %r, half* %p
; ret void
;}
define void @test_round(half* %p) {
; CHECK-LABEL: test_round:
; CHECK: vldr.16 s0, [r0]
; CHECK-NEXT: vrinta.f16 s0, s0
; CHECK-NEXT: vstr.16 s0, [r0]
; CHECK-NEXT: bx lr
%a = load half, half* %p, align 2
%r = call half @llvm.round.f16(half %a)
store half %r, half* %p
ret void
}
define void @test_fmuladd(half* %p, half* %q, half* %r) {
; CHECK-LABEL: test_fmuladd:

13
llvm/test/CodeGen/ARM/fp16-instructions.ll
View File

@ -43,8 +43,6 @@ entry:
; CHECK-HARDFP-FULLFP16: {{.*}} lr
}
; 1. VABS: TODO
; 2. VADD
define float @Add(float %a.coerce, float %b.coerce) {
entry:
@ -691,15 +689,6 @@ entry:
; CHECK-HARDFP-FULLFP16: vnmul.f16 s0, s0, s1
}
; TODO:
; 28. VRINTA
; 29. VRINTM
; 30. VRINTN
; 31. VRINTP
; 32. VRINTR
; 33. VRINTX
; 34. VRINTZ
; 35. VSELEQ
define half @select_cc1(half* %a0) {
%1 = load half, half* %a0
@ -955,8 +944,6 @@ entry:
; CHECK-SOFTFP-FP16-T32-NEXT: vcvtb.f16.f32 s0, [[S4]]
}
; 39. VSQRT - TODO
; 40. VSUB
define float @Sub(float %a.coerce, float %b.coerce) {
entry: