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Adjust to new TargetMachine interface 

llvm-svn: 13956
This commit is contained in:
Chris Lattner 2004-06-02 05:57:12 +00:00
parent 185fa54c68
commit 2150542af9
11 changed files with 18 additions and 19 deletions
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9
llvm/lib/CodeGen/LiveIntervals.cpp
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@ -122,7 +122,7 @@ bool LiveIntervals::runOnMachineFunction(MachineFunction &fn) {
// perform a final pass over the instructions and compute spill // perform a final pass over the instructions and compute spill
// weights, coalesce virtual registers and remove identity moves // weights, coalesce virtual registers and remove identity moves
const LoopInfo& loopInfo = getAnalysis<LoopInfo>(); const LoopInfo& loopInfo = getAnalysis<LoopInfo>();
const TargetInstrInfo& tii = tm_->getInstrInfo(); const TargetInstrInfo& tii = *tm_->getInstrInfo();
for (MachineFunction::iterator mbbi = mf_->begin(), mbbe = mf_->end(); for (MachineFunction::iterator mbbi = mf_->begin(), mbbe = mf_->end();
mbbi != mbbe; ++mbbi) { mbbi != mbbe; ++mbbi) {
@ -424,7 +424,7 @@ void LiveIntervals::computeIntervals()
for (MachineBasicBlock::iterator mi = mbb->begin(), miEnd = mbb->end(); for (MachineBasicBlock::iterator mi = mbb->begin(), miEnd = mbb->end();
mi != miEnd; ++mi) { mi != miEnd; ++mi) {
const TargetInstrDescriptor& tid = const TargetInstrDescriptor& tid =
tm_->getInstrInfo().get(mi->getOpcode()); tm_->getInstrInfo()->get(mi->getOpcode());
DEBUG(std::cerr << getInstructionIndex(mi) << "\t"; DEBUG(std::cerr << getInstructionIndex(mi) << "\t";
mi->print(std::cerr, *tm_)); mi->print(std::cerr, *tm_));
@ -455,7 +455,7 @@ void LiveIntervals::joinIntervals()
{ {
DEBUG(std::cerr << "********** JOINING INTERVALS ***********\n"); DEBUG(std::cerr << "********** JOINING INTERVALS ***********\n");
const TargetInstrInfo& tii = tm_->getInstrInfo(); const TargetInstrInfo& tii = *tm_->getInstrInfo();
for (MachineFunction::iterator mbbi = mf_->begin(), mbbe = mf_->end(); for (MachineFunction::iterator mbbi = mf_->begin(), mbbe = mf_->end();
mbbi != mbbe; ++mbbi) { mbbi != mbbe; ++mbbi) {
@ -464,8 +464,7 @@ void LiveIntervals::joinIntervals()
for (MachineBasicBlock::iterator mi = mbb->begin(), mie = mbb->end(); for (MachineBasicBlock::iterator mi = mbb->begin(), mie = mbb->end();
mi != mie; ++mi) { mi != mie; ++mi) {
const TargetInstrDescriptor& tid = const TargetInstrDescriptor& tid = tii.get(mi->getOpcode());
tm_->getInstrInfo().get(mi->getOpcode());
DEBUG(std::cerr << getInstructionIndex(mi) << '\t'; DEBUG(std::cerr << getInstructionIndex(mi) << '\t';
mi->print(std::cerr, *tm_);); mi->print(std::cerr, *tm_););

2
llvm/lib/CodeGen/LiveVariables.cpp
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@ -159,7 +159,7 @@ void LiveVariables::HandlePhysRegDef(unsigned Reg, MachineInstr *MI) {
} }
bool LiveVariables::runOnMachineFunction(MachineFunction &MF) { bool LiveVariables::runOnMachineFunction(MachineFunction &MF) {
const TargetInstrInfo &TII = MF.getTarget().getInstrInfo(); const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo();
RegInfo = MF.getTarget().getRegisterInfo(); RegInfo = MF.getTarget().getRegisterInfo();
assert(RegInfo && "Target doesn't have register information?"); assert(RegInfo && "Target doesn't have register information?");

2
llvm/lib/CodeGen/MachineBasicBlock.cpp
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@ -81,7 +81,7 @@ void ilist_traits<MachineInstr>::transferNodesFromList(
MachineBasicBlock::iterator MachineBasicBlock::getFirstTerminator() MachineBasicBlock::iterator MachineBasicBlock::getFirstTerminator()
{ {
const TargetInstrInfo& TII = getParent()->getTarget().getInstrInfo(); const TargetInstrInfo& TII = *getParent()->getTarget().getInstrInfo();
iterator I = end(); iterator I = end();
while (I != begin() && TII.isTerminatorInstr((--I)->getOpcode())); while (I != begin() && TII.isTerminatorInstr((--I)->getOpcode()));
if (I != end() && !TII.isTerminatorInstr(I->getOpcode())) ++I; if (I != end() && !TII.isTerminatorInstr(I->getOpcode())) ++I;

2
llvm/lib/CodeGen/MachineInstr.cpp
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@ -322,7 +322,7 @@ void MachineInstr::print(std::ostream &OS, const TargetMachine &TM) const {
OS << " = "; OS << " = ";
++StartOp; // Don't print this operand again! ++StartOp; // Don't print this operand again!
} }
OS << TM.getInstrInfo().getName(getOpcode()); OS << TM.getInstrInfo()->getName(getOpcode());
for (unsigned i = StartOp, e = getNumOperands(); i != e; ++i) { for (unsigned i = StartOp, e = getNumOperands(); i != e; ++i) {
const MachineOperand& mop = getOperand(i); const MachineOperand& mop = getOperand(i);

2
llvm/lib/CodeGen/Makefile
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@ -8,7 +8,7 @@
##===----------------------------------------------------------------------===## ##===----------------------------------------------------------------------===##
LEVEL = ../.. LEVEL = ../..
PARALLEL_DIRS = InstrSched SelectionDAG #PARALLEL_DIRS = InstrSched SelectionDAG
LIBRARYNAME = codegen LIBRARYNAME = codegen
include $(LEVEL)/Makefile.common include $(LEVEL)/Makefile.common

2
llvm/lib/CodeGen/PHIElimination.cpp
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@ -66,7 +66,7 @@ bool PNE::EliminatePHINodes(MachineFunction &MF, MachineBasicBlock &MBB) {
return false; // Quick exit for normal case... return false; // Quick exit for normal case...
LiveVariables *LV = getAnalysisToUpdate<LiveVariables>(); LiveVariables *LV = getAnalysisToUpdate<LiveVariables>();
const TargetInstrInfo &MII = MF.getTarget().getInstrInfo(); const TargetInstrInfo &MII = *MF.getTarget().getInstrInfo();
const MRegisterInfo *RegInfo = MF.getTarget().getRegisterInfo(); const MRegisterInfo *RegInfo = MF.getTarget().getRegisterInfo();
// VRegPHIUseCount - Keep track of the number of times each virtual register // VRegPHIUseCount - Keep track of the number of times each virtual register

8
llvm/lib/CodeGen/PrologEpilogInserter.cpp
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@ -82,7 +82,7 @@ FunctionPass *llvm::createPrologEpilogCodeInserter() { return new PEI(); }
/// ///
void PEI::saveCallerSavedRegisters(MachineFunction &Fn) { void PEI::saveCallerSavedRegisters(MachineFunction &Fn) {
const MRegisterInfo *RegInfo = Fn.getTarget().getRegisterInfo(); const MRegisterInfo *RegInfo = Fn.getTarget().getRegisterInfo();
const TargetFrameInfo &FrameInfo = Fn.getTarget().getFrameInfo(); const TargetFrameInfo &FrameInfo = *Fn.getTarget().getFrameInfo();
// Get the callee saved register list... // Get the callee saved register list...
const unsigned *CSRegs = RegInfo->getCalleeSaveRegs(); const unsigned *CSRegs = RegInfo->getCalleeSaveRegs();
@ -170,7 +170,7 @@ void PEI::saveCallerSavedRegisters(MachineFunction &Fn) {
} }
// Add code to restore the callee-save registers in each exiting block. // Add code to restore the callee-save registers in each exiting block.
const TargetInstrInfo &TII = Fn.getTarget().getInstrInfo(); const TargetInstrInfo &TII = *Fn.getTarget().getInstrInfo();
for (MachineFunction::iterator FI = Fn.begin(), E = Fn.end(); FI != E; ++FI) { for (MachineFunction::iterator FI = Fn.begin(), E = Fn.end(); FI != E; ++FI) {
// If last instruction is a return instruction, add an epilogue // If last instruction is a return instruction, add an epilogue
if (!FI->empty() && TII.isReturn(FI->back().getOpcode())) { if (!FI->empty() && TII.isReturn(FI->back().getOpcode())) {
@ -191,7 +191,7 @@ void PEI::saveCallerSavedRegisters(MachineFunction &Fn) {
/// abstract stack objects... /// abstract stack objects...
/// ///
void PEI::calculateFrameObjectOffsets(MachineFunction &Fn) { void PEI::calculateFrameObjectOffsets(MachineFunction &Fn) {
const TargetFrameInfo &TFI = Fn.getTarget().getFrameInfo(); const TargetFrameInfo &TFI = *Fn.getTarget().getFrameInfo();
bool StackGrowsDown = bool StackGrowsDown =
TFI.getStackGrowthDirection() == TargetFrameInfo::StackGrowsDown; TFI.getStackGrowthDirection() == TargetFrameInfo::StackGrowsDown;
@ -245,7 +245,7 @@ void PEI::insertPrologEpilogCode(MachineFunction &Fn) {
Fn.getTarget().getRegisterInfo()->emitPrologue(Fn); Fn.getTarget().getRegisterInfo()->emitPrologue(Fn);
// Add epilogue to restore the callee-save registers in each exiting block // Add epilogue to restore the callee-save registers in each exiting block
const TargetInstrInfo &TII = Fn.getTarget().getInstrInfo(); const TargetInstrInfo &TII = *Fn.getTarget().getInstrInfo();
for (MachineFunction::iterator I = Fn.begin(), E = Fn.end(); I != E; ++I) { for (MachineFunction::iterator I = Fn.begin(), E = Fn.end(); I != E; ++I) {
// If last instruction is a return instruction, add an epilogue // If last instruction is a return instruction, add an epilogue
if (!I->empty() && TII.isReturn(I->back().getOpcode())) if (!I->empty() && TII.isReturn(I->back().getOpcode()))

2
llvm/lib/CodeGen/RegAllocLocal.cpp
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@ -520,7 +520,7 @@ void RA::AllocateBasicBlock(MachineBasicBlock &MBB) {
// loop over each instruction // loop over each instruction
MachineBasicBlock::iterator MI = MBB.begin(); MachineBasicBlock::iterator MI = MBB.begin();
for (; MI != MBB.end(); ++MI) { for (; MI != MBB.end(); ++MI) {
const TargetInstrDescriptor &TID = TM->getInstrInfo().get(MI->getOpcode()); const TargetInstrDescriptor &TID = TM->getInstrInfo()->get(MI->getOpcode());
DEBUG(std::cerr << "\nStarting RegAlloc of: " << *MI; DEBUG(std::cerr << "\nStarting RegAlloc of: " << *MI;
std::cerr << " Regs have values: "; std::cerr << " Regs have values: ";
for (unsigned i = 0; i != RegInfo->getNumRegs(); ++i) for (unsigned i = 0; i != RegInfo->getNumRegs(); ++i)

4
llvm/lib/CodeGen/RegAllocSimple.cpp
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@ -159,7 +159,7 @@ void RegAllocSimple::AllocateBasicBlock(MachineBasicBlock &MBB) {
// a preliminary pass that will invalidate any registers that // a preliminary pass that will invalidate any registers that
// are used by the instruction (including implicit uses) // are used by the instruction (including implicit uses)
unsigned Opcode = MI->getOpcode(); unsigned Opcode = MI->getOpcode();
const TargetInstrDescriptor &Desc = TM->getInstrInfo().get(Opcode); const TargetInstrDescriptor &Desc = TM->getInstrInfo()->get(Opcode);
const unsigned *Regs = Desc.ImplicitUses; const unsigned *Regs = Desc.ImplicitUses;
while (*Regs) while (*Regs)
RegsUsed[*Regs++] = true; RegsUsed[*Regs++] = true;
@ -184,7 +184,7 @@ void RegAllocSimple::AllocateBasicBlock(MachineBasicBlock &MBB) {
unsigned physReg = Virt2PhysRegMap[virtualReg]; unsigned physReg = Virt2PhysRegMap[virtualReg];
if (physReg == 0) { if (physReg == 0) {
if (op.isDef()) { if (op.isDef()) {
if (!TM->getInstrInfo().isTwoAddrInstr(MI->getOpcode()) || i) { if (!TM->getInstrInfo()->isTwoAddrInstr(MI->getOpcode()) || i) {
physReg = getFreeReg(virtualReg); physReg = getFreeReg(virtualReg);
} else { } else {
// must be same register number as the first operand // must be same register number as the first operand

2
llvm/lib/CodeGen/TwoAddressInstructionPass.cpp
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@ -77,7 +77,7 @@ bool TwoAddressInstructionPass::runOnMachineFunction(MachineFunction &MF) {
DEBUG(std::cerr << "Machine Function\n"); DEBUG(std::cerr << "Machine Function\n");
const TargetMachine &TM = MF.getTarget(); const TargetMachine &TM = MF.getTarget();
const MRegisterInfo &MRI = *TM.getRegisterInfo(); const MRegisterInfo &MRI = *TM.getRegisterInfo();
const TargetInstrInfo &TII = TM.getInstrInfo(); const TargetInstrInfo &TII = *TM.getInstrInfo();
LiveVariables* LV = getAnalysisToUpdate<LiveVariables>(); LiveVariables* LV = getAnalysisToUpdate<LiveVariables>();
bool MadeChange = false; bool MadeChange = false;

2
llvm/lib/CodeGen/VirtRegMap.cpp
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@ -191,7 +191,7 @@ namespace {
bool runOnMachineFunction(MachineFunction& mf, const VirtRegMap& vrm) { bool runOnMachineFunction(MachineFunction& mf, const VirtRegMap& vrm) {
mf_ = &mf; mf_ = &mf;
tm_ = &mf_->getTarget(); tm_ = &mf_->getTarget();
tii_ = &tm_->getInstrInfo(); tii_ = tm_->getInstrInfo();
mri_ = tm_->getRegisterInfo(); mri_ = tm_->getRegisterInfo();
vrm_ = &vrm; vrm_ = &vrm;
p2vMap_.assign(mri_->getNumRegs(), 0); p2vMap_.assign(mri_->getNumRegs(), 0);