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GlobalISel: Check address space when looking up iPTR size 

Fixes AMDGPU patterns for 32-bit address spaces always failing. Tests
will be included in future patches when additional issues are solved.

llvm-svn: 365319
This commit is contained in:
Matt Arsenault 2019-07-08 13:48:04 +00:00
parent 1159fe3f6e
commit 214f67ece5
1 changed files with 5 additions and 3 deletions
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8
llvm/include/llvm/CodeGen/GlobalISel/InstructionSelectorImpl.h
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@ -478,17 +478,19 @@ bool InstructionSelector::executeMatchTable(
<< InsnID << "]->getOperand(" << OpIdx
<< "), SizeInBits=" << SizeInBits << ")\n");
assert(State.MIs[InsnID] != nullptr && "Used insn before defined");
MachineOperand &MO = State.MIs[InsnID]->getOperand(OpIdx);
const LLT Ty = MRI.getType(MO.getReg());
// iPTR must be looked up in the target.
if (SizeInBits == 0) {
MachineFunction *MF = State.MIs[InsnID]->getParent()->getParent();
SizeInBits = MF->getDataLayout().getPointerSizeInBits(0);
const unsigned AddrSpace = Ty.getAddressSpace();
SizeInBits = MF->getDataLayout().getPointerSizeInBits(AddrSpace);
}
assert(SizeInBits != 0 && "Pointer size must be known");
MachineOperand &MO = State.MIs[InsnID]->getOperand(OpIdx);
if (MO.isReg()) {
const LLT &Ty = MRI.getType(MO.getReg());
if (!Ty.isPointer() || Ty.getSizeInBits() != SizeInBits)
if (handleReject() == RejectAndGiveUp)
return false;