forked from OSchip/llvm-project
[AMDGPU] Remove no-ret atomic ops selection in the post-isel hook
No-ret atomic ops are now selected in tblgen. Differential Revision: https://reviews.llvm.org/D124086
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@ -11698,47 +11698,6 @@ void SITargetLowering::AdjustInstrPostInstrSelection(MachineInstr &MI,
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return;
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return;
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}
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}
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// Replace unused atomics with the no return version.
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int NoRetAtomicOp = AMDGPU::getAtomicNoRetOp(MI.getOpcode());
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if (NoRetAtomicOp != -1) {
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if (!Node->hasAnyUseOfValue(0)) {
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int CPolIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(),
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AMDGPU::OpName::cpol);
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if (CPolIdx != -1) {
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MachineOperand &CPol = MI.getOperand(CPolIdx);
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CPol.setImm(CPol.getImm() & ~AMDGPU::CPol::GLC);
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}
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MI.removeOperand(0);
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MI.setDesc(TII->get(NoRetAtomicOp));
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return;
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}
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// For mubuf_atomic_cmpswap, we need to have tablegen use an extract_subreg
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// instruction, because the return type of these instructions is a vec2 of
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// the memory type, so it can be tied to the input operand.
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// This means these instructions always have a use, so we need to add a
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// special case to check if the atomic has only one extract_subreg use,
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// which itself has no uses.
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if ((Node->hasNUsesOfValue(1, 0) &&
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Node->use_begin()->isMachineOpcode() &&
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Node->use_begin()->getMachineOpcode() == AMDGPU::EXTRACT_SUBREG &&
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!Node->use_begin()->hasAnyUseOfValue(0))) {
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Register Def = MI.getOperand(0).getReg();
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// Change this into a noret atomic.
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MI.setDesc(TII->get(NoRetAtomicOp));
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MI.removeOperand(0);
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// If we only remove the def operand from the atomic instruction, the
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// extract_subreg will be left with a use of a vreg without a def.
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// So we need to insert an implicit_def to avoid machine verifier
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// errors.
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BuildMI(*MI.getParent(), MI, MI.getDebugLoc(),
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TII->get(AMDGPU::IMPLICIT_DEF), Def);
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}
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return;
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}
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if (TII->isMIMG(MI) && !MI.mayStore())
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if (TII->isMIMG(MI) && !MI.mayStore())
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AddIMGInit(MI);
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AddIMGInit(MI);
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}
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}
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