forked from OSchip/llvm-project
[X86] movdiri and movdir64b instructions
Reviewers: craig.topper llvm-svn: 330638
This commit is contained in:
Gabor Buella
parent
b387b6e6dc
commit
213a7cda1f
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@ -6293,3 +6293,15 @@ let TargetPrefix = "x86" in {
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def int_x86_tpause : GCCBuiltin<"__builtin_ia32_tpause">,
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Intrinsic<[llvm_i8_ty], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], []>;
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}
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//===----------------------------------------------------------------------===//
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// Direct Move Instructions
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let TargetPrefix = "x86" in {
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def int_x86_directstore32 : GCCBuiltin<"__builtin_ia32_directstore_u32">,
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Intrinsic<[], [llvm_ptr_ty, llvm_i32_ty], []>;
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def int_x86_directstore64 : GCCBuiltin<"__builtin_ia32_directstore_u64">,
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Intrinsic<[], [llvm_ptr_ty, llvm_i64_ty], []>;
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def int_x86_movdir64b : GCCBuiltin<"__builtin_ia32_movdir64b">,
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Intrinsic<[], [llvm_ptr_ty, llvm_ptr_ty], []>;
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}
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@ -1264,6 +1264,10 @@ bool sys::getHostCPUFeatures(StringMap<bool> &Features) {
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Features["ibt"] = HasLeaf7 && ((EDX >> 20) & 1);
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// Direct move instruction support.
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Features["movdiri"] = HasLeaf7 && ((ECX >> 27) & 1);
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Features["movdir64b"] = HasLeaf7 && ((ECX >> 28) & 1);
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bool HasLeafD = MaxLevel >= 0xd &&
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!getX86CpuIDAndInfoEx(0xd, 0x1, &EAX, &EBX, &ECX, &EDX);
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@ -1057,14 +1057,15 @@ static int getID(struct InternalInstruction* insn, const void *miiArg) {
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}
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/*
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* Absolute moves and umonitor need special handling.
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* Absolute moves, umonitor, and movdir64b need special handling.
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* -For 16-bit mode because the meaning of the AdSize and OpSize prefixes are
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* inverted w.r.t.
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* -For 32-bit mode we need to ensure the ADSIZE prefix is observed in
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* any position.
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*/
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if ((insn->opcodeType == ONEBYTE && ((insn->opcode & 0xFC) == 0xA0)) ||
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(insn->opcodeType == TWOBYTE && (insn->opcode == 0xAE))) {
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(insn->opcodeType == TWOBYTE && (insn->opcode == 0xAE)) ||
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(insn->opcodeType == THREEBYTE_38 && insn->opcode == 0xF8)) {
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/* Make sure we observed the prefixes in any position. */
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if (insn->hasAdSize)
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attrMask |= ATTR_ADSIZE;
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@ -1074,6 +1075,7 @@ static int getID(struct InternalInstruction* insn, const void *miiArg) {
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/* In 16-bit, invert the attributes. */
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if (insn->mode == MODE_16BIT) {
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attrMask ^= ATTR_ADSIZE;
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/* The OpSize attribute is only valid with the absolute moves. */
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if (insn->opcodeType == ONEBYTE && ((insn->opcode & 0xFC) == 0xA0))
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attrMask ^= ATTR_OPSIZE;
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@ -379,6 +379,12 @@ def FeatureRetpolineExternalThunk
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"Enable retpoline, but with an externally provided thunk.",
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[FeatureRetpoline]>;
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// Direct Move instructions.
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def FeatureMOVDIRI : SubtargetFeature<"movdiri", "HasMOVDIRI", "true",
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"Support movdiri instruction">;
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def FeatureMOVDIR64B : SubtargetFeature<"movdir64b", "HasMOVDIR64B", "true",
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"Support movdir64b instruction">;
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//===----------------------------------------------------------------------===//
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// Register File Description
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//===----------------------------------------------------------------------===//
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@ -629,6 +635,8 @@ class TremontProc<string Name> : ProcModel<Name, SLMModel,
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ProcIntelTRM,
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FeatureCLDEMOTE,
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FeatureGFNI,
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FeatureMOVDIRI,
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FeatureMOVDIR64B,
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FeatureRDPID,
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FeatureSGX,
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FeatureWAITPKG
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@ -892,6 +892,8 @@ def HasLAHFSAHF : Predicate<"Subtarget->hasLAHFSAHF()">;
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def HasMWAITX : Predicate<"Subtarget->hasMWAITX()">;
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def HasCLZERO : Predicate<"Subtarget->hasCLZERO()">;
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def HasCLDEMOTE : Predicate<"Subtarget->hasCLDEMOTE()">;
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def HasMOVDIRI : Predicate<"Subtarget->hasMOVDIRI()">;
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def HasMOVDIR64B : Predicate<"Subtarget->hasMOVDIR64B()">;
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def FPStackf32 : Predicate<"!Subtarget->hasSSE1()">;
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def FPStackf64 : Predicate<"!Subtarget->hasSSE2()">;
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def HasMPX : Predicate<"Subtarget->hasMPX()">;
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@ -2801,6 +2803,9 @@ include "X86InstrSGX.td"
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// System instructions.
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include "X86InstrSystem.td"
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// Direct Move instructions.
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include "X86InstrMovdir.td"
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// Compiler Pseudo Instructions and Pat Patterns
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include "X86InstrCompiler.td"
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include "X86InstrVecCompiler.td"
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@ -0,0 +1,31 @@
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//===-- X86InstrMovdir.td - Direct Move Instructions ------*- tablegen -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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// MOVDIRI - Move doubleword/quadword as direct store
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def MOVDIRI32 : I<0xF9, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
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"movdiri\t{$src, $dst|$dst, $src}",
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[(int_x86_directstore32 addr:$dst, GR32:$src)]>,
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T8, Requires<[HasMOVDIRI]>;
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def MOVDIRI64 : RI<0xF9, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
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"movdiri\t{$src, $dst|$dst, $src}",
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[(int_x86_directstore64 addr:$dst, GR64:$src)]>,
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T8, Requires<[In64BitMode, HasMOVDIRI]>;
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// MOVDIR64B - Move 64 bytes as direct store
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def MOVDIR64B16 : I<0xF8, MRMSrcMem, (outs), (ins GR16:$dst, i512mem:$src),
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"movdir64b\t{$src, $dst|$dst, $src}", []>,
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T8PD, AdSize16, Requires<[HasMOVDIR64B, Not64BitMode]>;
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def MOVDIR64B32 : I<0xF8, MRMSrcMem, (outs), (ins GR32:$dst, i512mem:$src),
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"movdir64b\t{$src, $dst|$dst, $src}",
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[(int_x86_movdir64b GR32:$dst, addr:$src)]>,
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T8PD, AdSize32, Requires<[HasMOVDIR64B]>;
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def MOVDIR64B64 : I<0xF8, MRMSrcMem, (outs), (ins GR64:$dst, i512mem:$src),
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"movdir64b\t{$src, $dst|$dst, $src}",
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[(int_x86_movdir64b GR64:$dst, addr:$src)]>,
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T8PD, AdSize64, Requires<[HasMOVDIR64B, In64BitMode]>;
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@ -317,6 +317,8 @@ void X86Subtarget::initializeEnvironment() {
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HasMWAITX = false;
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HasCLZERO = false;
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HasCLDEMOTE = false;
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HasMOVDIRI = false;
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HasMOVDIR64B = false;
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HasMPX = false;
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HasSHSTK = false;
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HasIBT = false;
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@ -209,6 +209,12 @@ protected:
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/// Processor has Cache Line Demote instruction
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bool HasCLDEMOTE;
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/// Processor has MOVDIRI instruction (direct store integer).
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bool HasMOVDIRI;
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/// Processor has MOVDIR64B instruction (direct store 64 bytes).
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bool HasMOVDIR64B;
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/// Processor has Prefetch with intent to Write instruction
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bool HasPREFETCHWT1;
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@ -582,6 +588,8 @@ public:
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bool hasMWAITX() const { return HasMWAITX; }
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bool hasCLZERO() const { return HasCLZERO; }
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bool hasCLDEMOTE() const { return HasCLDEMOTE; }
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bool hasMOVDIRI() const { return HasMOVDIRI; }
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bool hasMOVDIR64B() const { return HasMOVDIR64B; }
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bool isSHLDSlow() const { return IsSHLDSlow; }
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bool isPMULLDSlow() const { return IsPMULLDSlow; }
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bool isUnalignedMem16Slow() const { return IsUAMem16Slow; }
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@ -0,0 +1,41 @@
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+movdiri -mattr=+movdir64b | FileCheck %s --check-prefix=X64
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; RUN: llc < %s -mtriple=i386-unknown-unknown -mattr=+movdiri -mattr=+movdir64b | FileCheck %s --check-prefix=X32
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define void @test_movdiri(i8* %p, i32 %v) {
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; X64-LABEL: test_movdiri:
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; X64: # %bb.0: # %entry
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; X64-NEXT: movdiri %esi, (%rdi)
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; X64-NEXT: retq
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;
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; X32-LABEL: test_movdiri:
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; X32: # %bb.0: # %entry
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; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
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; X32-NEXT: movl {{[0-9]+}}(%esp), %ecx
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; X32-NEXT: movdiri %eax, (%ecx)
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; X32-NEXT: retl
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entry:
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call void @llvm.x86.directstore32(i8* %p, i32 %v)
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ret void
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}
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declare void @llvm.x86.directstore32(i8*, i32)
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define void @test_movdir64b(i8* %dst, i8* %src) {
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; X64-LABEL: test_movdir64b:
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; X64: # %bb.0: # %entry
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; X64-NEXT: movdir64b (%rsi), %rdi
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; X64-NEXT: retq
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;
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; X32-LABEL: test_movdir64b:
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; X32: # %bb.0: # %entry
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; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
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; X32-NEXT: movl {{[0-9]+}}(%esp), %ecx
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; X32-NEXT: movdir64b (%eax), %ecx
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; X32-NEXT: retl
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entry:
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call void @llvm.x86.movdir64b(i8* %dst, i8* %src)
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ret void
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}
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declare void @llvm.x86.movdir64b(i8*, i8*)
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@ -0,0 +1,14 @@
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+movdiri | FileCheck %s
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define void @test_movdiri(i8* %p, i64 %v) {
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; CHECK-LABEL: test_movdiri:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: movdiri %rsi, (%rdi)
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; CHECK-NEXT: retq
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entry:
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call void @llvm.x86.directstore64(i8* %p, i64 %v)
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ret void
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}
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declare void @llvm.x86.directstore64(i8*, i64)
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@ -800,3 +800,9 @@
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# CHECK: umonitor %eax
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0x67 0xf3 0x0f 0xae 0xf0
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#CHECK: movdir64b (%esi), %eax
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0x67 0x66 0x0f 0x38 0xf8 0x06
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#CHECK: movdir64b (%si), %ax
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0x66 0x0f 0x38 0xf8 0x04
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@ -859,3 +859,15 @@
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# CHECK: tpause %eax
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0x66 0x0f 0xae 0xf0
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#CHECK: movdiri %eax, 64(%edx,%edi)
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0x0f 0x38 0xf9 0x44 0x3a 0x40
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#CHECK: movdir64b 485498096, %ecx
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0x66 0x0f 0x38 0xf8 0x0d 0xf0 0x1c 0xf0 0x1c
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#CHECK: movdir64b (%esi), %eax
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0x66 0x0f 0x38 0xf8 0x06
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#CHECK: movdir64b (%si), %ax
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0x67 0x66 0x0f 0x38 0xf8 0x04
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@ -555,3 +555,12 @@
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# CHECK: bswapq %rbx
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0x48 0x0f 0xcb
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#CHECK: movdiri %r13d, 64(%rdx,%rax,4)
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0x44 0x0f 0x38 0xf9 0x6c 0x82 0x40
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#CHECK: movdir64b 485498096, %rax
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0x66 0x0f 0x38 0xf8 0x04 0x25 0xf0 0x1c 0xf0 0x1c
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#CHECK: movdir64b 485498096, %eax
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0x67 0x66 0x0f 0x38 0xf8 0x04 0x25 0xf0 0x1c 0xf0 0x1c
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@ -981,3 +981,11 @@ umonitor %ax
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// CHECK: umonitor %eax
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// CHECK: encoding: [0x67,0xf3,0x0f,0xae,0xf0]
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umonitor %eax
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// CHECK: movdir64b (%esi), %eax
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// CHECK: encoding: [0x67,0x66,0x0f,0x38,0xf8,0x06]
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movdir64b (%esi), %eax
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// CHECK: movdir64b (%si), %ax
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// CHECK: encoding: [0x66,0x0f,0x38,0xf8,0x04]
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movdir64b (%si), %ax
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@ -10768,3 +10768,27 @@ btcl $4, (%eax)
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// CHECK: tpause %eax
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// CHECK: encoding: [0x66,0x0f,0xae,0xf0]
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tpause %eax
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// CHECK: movdiri %eax, 64(%edx,%edi)
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// CHECK: # encoding: [0x0f,0x38,0xf9,0x44,0x3a,0x40]
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movdiri %eax, 64(%edx,%edi)
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// CHECK: movdir64b 485498096, %ecx
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// CHECK: # encoding: [0x66,0x0f,0x38,0xf8,0x0d,0xf0,0x1c,0xf0,0x1c]
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movdir64b 485498096, %ecx
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// CHECK: movdir64b 485498096, %cx
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// CHECK: # encoding: [0x67,0x66,0x0f,0x38,0xf8,0x0d,0xf0,0x1c,0xf0,0x1c]
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movdir64b 485498096, %cx
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// CHECK: movdir64b (%edx), %eax
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// CHECK: # encoding: [0x66,0x0f,0x38,0xf8,0x02]
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movdir64b (%edx), %eax
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// CHECK: movdir64b (%esi), %eax
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// CHECK: # encoding: [0x66,0x0f,0x38,0xf8,0x06]
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movdir64b (%esi), %eax
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// CHECK: movdir64b (%si), %ax
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// CHECK: # encoding: [0x67,0x66,0x0f,0x38,0xf8,0x04]
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movdir64b (%si), %ax
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@ -1599,6 +1599,30 @@ tpause %r15
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// CHECK: encoding: [0x66,0x0f,0xae,0xf3]
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tpause %ebx
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// CHECK: movdiri %r15, 485498096
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// CHECK: # encoding: [0x4c,0x0f,0x38,0xf9,0x3c,0x25,0xf0,0x1c,0xf0,0x1c]
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movdiri %r15, 485498096
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// CHECK: movdiri %r15, (%rdx)
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// CHECK: # encoding: [0x4c,0x0f,0x38,0xf9,0x3a]
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movdiri %r15, (%rdx)
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// CHECK: movdiri %r15, 64(%rdx)
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// CHECK: # encoding: [0x4c,0x0f,0x38,0xf9,0x7a,0x40]
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movdiri %r15, 64(%rdx)
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// CHECK: movdir64b 485498096, %rax
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// CHECK: # encoding: [0x66,0x0f,0x38,0xf8,0x04,0x25,0xf0,0x1c,0xf0,0x1c]
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movdir64b 485498096, %rax
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// CHECK: movdir64b 485498096, %eax
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// CHECK: # encoding: [0x67,0x66,0x0f,0x38,0xf8,0x04,0x25,0xf0,0x1c,0xf0,0x1c]
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movdir64b 485498096, %eax
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// CHECK: movdir64b (%rdx), %r15
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// CHECK: # encoding: [0x66,0x44,0x0f,0x38,0xf8,0x3a]
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movdir64b (%rdx), %r15
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// __asm __volatile(
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// "pushf \n\t"
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// "popf \n\t"
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@ -301,6 +301,8 @@ InstructionContext RecognizableInstr::insnContext() const {
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insnContext = IC_64BIT_XD_OPSIZE;
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else if (OpSize == X86Local::OpSize16 && OpPrefix == X86Local::XS)
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insnContext = IC_64BIT_XS_OPSIZE;
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else if (AdSize == X86Local::AdSize32 && OpPrefix == X86Local::PD)
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insnContext = IC_64BIT_OPSIZE_ADSIZE;
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else if (OpSize == X86Local::OpSize16 && AdSize == X86Local::AdSize32)
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insnContext = IC_64BIT_OPSIZE_ADSIZE;
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else if (OpSize == X86Local::OpSize16 || OpPrefix == X86Local::PD)
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@ -328,6 +330,8 @@ InstructionContext RecognizableInstr::insnContext() const {
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insnContext = IC_XD_ADSIZE;
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else if (AdSize == X86Local::AdSize16 && OpPrefix == X86Local::XS)
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insnContext = IC_XS_ADSIZE;
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else if (AdSize == X86Local::AdSize16 && OpPrefix == X86Local::PD)
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insnContext = IC_OPSIZE_ADSIZE;
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else if (OpSize == X86Local::OpSize16 && AdSize == X86Local::AdSize16)
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insnContext = IC_OPSIZE_ADSIZE;
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else if (OpSize == X86Local::OpSize16 || OpPrefix == X86Local::PD)
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