forked from OSchip/llvm-project
[AArch64 NEON] Custom lower conversion between vector integer and vector floating point if element bit-width doesn't match.
llvm-svn: 199462
This commit is contained in:
Kevin Qin
parent
18d92262c5
commit
212d9b4a56
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@ -375,6 +375,34 @@ AArch64TargetLowering::AArch64TargetLowering(AArch64TargetMachine &TM)
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setOperationAction(ISD::FROUND, MVT::v1f64, Legal);
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setOperationAction(ISD::FROUND, MVT::v2f64, Legal);
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setOperationAction(ISD::SINT_TO_FP, MVT::v1i8, Custom);
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setOperationAction(ISD::SINT_TO_FP, MVT::v1i16, Custom);
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setOperationAction(ISD::SINT_TO_FP, MVT::v1i32, Custom);
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setOperationAction(ISD::SINT_TO_FP, MVT::v4i16, Custom);
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setOperationAction(ISD::SINT_TO_FP, MVT::v2i32, Custom);
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setOperationAction(ISD::SINT_TO_FP, MVT::v2i64, Custom);
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setOperationAction(ISD::UINT_TO_FP, MVT::v1i8, Custom);
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setOperationAction(ISD::UINT_TO_FP, MVT::v1i16, Custom);
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setOperationAction(ISD::UINT_TO_FP, MVT::v1i32, Custom);
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setOperationAction(ISD::UINT_TO_FP, MVT::v4i16, Custom);
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setOperationAction(ISD::UINT_TO_FP, MVT::v2i32, Custom);
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setOperationAction(ISD::UINT_TO_FP, MVT::v2i64, Custom);
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setOperationAction(ISD::FP_TO_SINT, MVT::v1i8, Custom);
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setOperationAction(ISD::FP_TO_SINT, MVT::v1i16, Custom);
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setOperationAction(ISD::FP_TO_SINT, MVT::v1i32, Custom);
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setOperationAction(ISD::FP_TO_SINT, MVT::v4i16, Custom);
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setOperationAction(ISD::FP_TO_SINT, MVT::v2i32, Custom);
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setOperationAction(ISD::FP_TO_SINT, MVT::v2i64, Custom);
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setOperationAction(ISD::FP_TO_UINT, MVT::v1i8, Custom);
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setOperationAction(ISD::FP_TO_UINT, MVT::v1i16, Custom);
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setOperationAction(ISD::FP_TO_UINT, MVT::v1i32, Custom);
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setOperationAction(ISD::FP_TO_UINT, MVT::v4i16, Custom);
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setOperationAction(ISD::FP_TO_UINT, MVT::v2i32, Custom);
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setOperationAction(ISD::FP_TO_UINT, MVT::v2i64, Custom);
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// Vector ExtLoad and TruncStore are expanded.
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for (unsigned I = MVT::FIRST_VECTOR_VALUETYPE;
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I <= MVT::LAST_VECTOR_VALUETYPE; ++I) {
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@ -2119,9 +2147,42 @@ AArch64TargetLowering::LowerFP_EXTEND(SDValue Op, SelectionDAG &DAG) const {
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return LowerF128ToCall(Op, DAG, LC);
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}
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static SDValue LowerVectorFP_TO_INT(SDValue Op, SelectionDAG &DAG,
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bool IsSigned) {
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SDLoc dl(Op);
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EVT VT = Op.getValueType();
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SDValue Vec = Op.getOperand(0);
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EVT OpVT = Vec.getValueType();
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unsigned Opc = IsSigned ? ISD::FP_TO_SINT : ISD::FP_TO_UINT;
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if (VT.getVectorNumElements() == 1) {
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assert(OpVT == MVT::v1f64 && "Unexpected vector type!");
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if (VT.getSizeInBits() == OpVT.getSizeInBits())
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return Op;
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return DAG.UnrollVectorOp(Op.getNode());
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}
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if (VT.getSizeInBits() > OpVT.getSizeInBits()) {
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assert(Vec.getValueType() == MVT::v2f32 && VT == MVT::v2i64 &&
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"Unexpected vector type!");
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Vec = DAG.getNode(ISD::FP_EXTEND, dl, MVT::v2f64, Vec);
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return DAG.getNode(Opc, dl, VT, Vec);
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} else if (VT.getSizeInBits() < OpVT.getSizeInBits()) {
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EVT CastVT = EVT::getIntegerVT(*DAG.getContext(),
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OpVT.getVectorElementType().getSizeInBits());
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CastVT =
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EVT::getVectorVT(*DAG.getContext(), CastVT, VT.getVectorNumElements());
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Vec = DAG.getNode(Opc, dl, CastVT, Vec);
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return DAG.getNode(ISD::TRUNCATE, dl, VT, Vec);
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}
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return DAG.getNode(Opc, dl, VT, Vec);
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}
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SDValue
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AArch64TargetLowering::LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG,
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bool IsSigned) const {
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if (Op.getValueType().isVector())
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return LowerVectorFP_TO_INT(Op, DAG, IsSigned);
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if (Op.getOperand(0).getValueType() != MVT::f128) {
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// It's legal except when f128 is involved
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return Op;
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@ -2467,9 +2528,42 @@ AArch64TargetLowering::LowerGlobalTLSAddress(SDValue Op,
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return DAG.getNode(ISD::ADD, DL, PtrVT, ThreadBase, TPOff);
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}
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static SDValue LowerVectorINT_TO_FP(SDValue Op, SelectionDAG &DAG,
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bool IsSigned) {
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SDLoc dl(Op);
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EVT VT = Op.getValueType();
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SDValue Vec = Op.getOperand(0);
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unsigned Opc = IsSigned ? ISD::SINT_TO_FP : ISD::UINT_TO_FP;
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if (VT.getVectorNumElements() == 1) {
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assert(VT == MVT::v1f64 && "Unexpected vector type!");
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if (VT.getSizeInBits() == Vec.getValueSizeInBits())
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return Op;
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return DAG.UnrollVectorOp(Op.getNode());
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}
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if (VT.getSizeInBits() < Vec.getValueSizeInBits()) {
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assert(Vec.getValueType() == MVT::v2i64 && VT == MVT::v2f32 &&
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"Unexpected vector type!");
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Vec = DAG.getNode(Opc, dl, MVT::v2f64, Vec);
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return DAG.getNode(ISD::FP_ROUND, dl, VT, Vec, DAG.getIntPtrConstant(0));
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} else if (VT.getSizeInBits() > Vec.getValueSizeInBits()) {
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unsigned CastOpc = IsSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
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EVT CastVT = EVT::getIntegerVT(*DAG.getContext(),
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VT.getVectorElementType().getSizeInBits());
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CastVT =
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EVT::getVectorVT(*DAG.getContext(), CastVT, VT.getVectorNumElements());
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Vec = DAG.getNode(CastOpc, dl, CastVT, Vec);
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}
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return DAG.getNode(Opc, dl, VT, Vec);
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}
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SDValue
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AArch64TargetLowering::LowerINT_TO_FP(SDValue Op, SelectionDAG &DAG,
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bool IsSigned) const {
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if (Op.getValueType().isVector())
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return LowerVectorINT_TO_FP(Op, DAG, IsSigned);
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if (Op.getValueType() != MVT::f128) {
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// Legal for everything except f128.
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return Op;
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@ -1080,6 +1080,90 @@ define <2 x i64> @test_vcvtq_u64_f64(<2 x double> %a) #0 {
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ret <2 x i64> %vcvt.i
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}
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define <2 x i64> @test_vcvt_s64_f32(<2 x float> %a) #0 {
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; CHECK: fcvtl v{{[0-9]+}}.2d, v{{[0-9]+}}.2s
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; CHECK: fcvtzs v{{[0-9]+}}.2d, v{{[0-9]+}}.2d
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%vcvt.i = fptosi <2 x float> %a to <2 x i64>
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ret <2 x i64> %vcvt.i
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}
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define <2 x i64> @test_vcvt_u64_f32(<2 x float> %a) #0 {
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; CHECK: fcvtl v{{[0-9]+}}.2d, v{{[0-9]+}}.2s
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; CHECK: fcvtzu v{{[0-9]+}}.2d, v{{[0-9]+}}.2d
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%vcvt.i = fptoui <2 x float> %a to <2 x i64>
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ret <2 x i64> %vcvt.i
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}
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define <4 x i16> @test_vcvt_s16_f32(<4 x float> %a) #0 {
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; CHECK: fcvtzs v{{[0-9]+}}.4s, v{{[0-9]+}}.4s
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; CHECK: xtn v{{[0-9]+}}.4h, v{{[0-9]+}}.4s
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%vcvt.i = fptosi <4 x float> %a to <4 x i16>
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ret <4 x i16> %vcvt.i
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}
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define <4 x i16> @test_vcvt_u16_f32(<4 x float> %a) #0 {
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; CHECK: fcvtzu v{{[0-9]+}}.4s, v{{[0-9]+}}.4s
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; CHECK: xtn v{{[0-9]+}}.4h, v{{[0-9]+}}.4s
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%vcvt.i = fptoui <4 x float> %a to <4 x i16>
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ret <4 x i16> %vcvt.i
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}
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define <2 x i32> @test_vcvt_s32_f64(<2 x double> %a) #0 {
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; CHECK: fcvtzs v{{[0-9]+}}.2d, v{{[0-9]+}}.2d
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; CHECK: xtn v{{[0-9]+}}.2s, v{{[0-9]+}}.2d
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%vcvt.i = fptosi <2 x double> %a to <2 x i32>
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ret <2 x i32> %vcvt.i
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}
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define <2 x i32> @test_vcvt_u32_f64(<2 x double> %a) #0 {
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; CHECK: fcvtzu v{{[0-9]+}}.2d, v{{[0-9]+}}.2d
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; CHECK: xtn v{{[0-9]+}}.2s, v{{[0-9]+}}.2d
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%vcvt.i = fptoui <2 x double> %a to <2 x i32>
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ret <2 x i32> %vcvt.i
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}
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define <1 x i8> @test_vcvt_s8_f64(<1 x double> %a) #0 {
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; CHECK: fcvtzs w{{[0-9]+}}, d{{[0-9]+}}
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; CHECK: ins v{{[0-9]+}}.b[0], w{{[0-9]+}}
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%vcvt.i = fptosi <1 x double> %a to <1 x i8>
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ret <1 x i8> %vcvt.i
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}
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define <1 x i8> @test_vcvt_u8_f64(<1 x double> %a) #0 {
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; CHECK: fcvtzs w{{[0-9]+}}, d{{[0-9]+}}
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; CHECK: ins v{{[0-9]+}}.b[0], w{{[0-9]+}}
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%vcvt.i = fptoui <1 x double> %a to <1 x i8>
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ret <1 x i8> %vcvt.i
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}
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define <1 x i16> @test_vcvt_s16_f64(<1 x double> %a) #0 {
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; CHECK: fcvtzs w{{[0-9]+}}, d{{[0-9]+}}
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; CHECK: ins v{{[0-9]+}}.h[0], w{{[0-9]+}}
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%vcvt.i = fptosi <1 x double> %a to <1 x i16>
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ret <1 x i16> %vcvt.i
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}
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define <1 x i16> @test_vcvt_u16_f64(<1 x double> %a) #0 {
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; CHECK: fcvtzs w{{[0-9]+}}, d{{[0-9]+}}
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; CHECK: ins v{{[0-9]+}}.h[0], w{{[0-9]+}}
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%vcvt.i = fptoui <1 x double> %a to <1 x i16>
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ret <1 x i16> %vcvt.i
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}
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define <1 x i32> @test_vcvt_s32_f64_v1(<1 x double> %a) #0 {
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; CHECK: fcvtzs w{{[0-9]+}}, d{{[0-9]+}}
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; CHECK: fmov s{{[0-9]+}}, w{{[0-9]+}}
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%vcvt.i = fptosi <1 x double> %a to <1 x i32>
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ret <1 x i32> %vcvt.i
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}
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define <1 x i32> @test_vcvt_u32_f64_v1(<1 x double> %a) #0 {
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; CHECK: fcvtzu w{{[0-9]+}}, d{{[0-9]+}}
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; CHECK: fmov s{{[0-9]+}}, w{{[0-9]+}}
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%vcvt.i = fptoui <1 x double> %a to <1 x i32>
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ret <1 x i32> %vcvt.i
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}
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define <2 x i32> @test_vcvtn_s32_f32(<2 x float> %a) {
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; CHECK-LABEL: test_vcvtn_s32_f32
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; CHECK: fcvtns v{{[0-9]+}}.2s, v{{[0-9]+}}.2s
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@ -1350,6 +1434,94 @@ define <2 x double> @test_vcvtq_f64_u64(<2 x i64> %a) #0 {
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ret <2 x double> %vcvt.i
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}
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define <2 x float> @test_vcvt_f32_s64(<2 x i64> %a) #0 {
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; CHECK: scvtf v{{[0-9]+}}.2d, v{{[0-9]+}}.2d
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; CHECK: fcvtn v{{[0-9]+}}.2s, v{{[0-9]+}}.2d
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%vcvt.i = sitofp <2 x i64> %a to <2 x float>
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ret <2 x float> %vcvt.i
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}
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define <2 x float> @test_vcvt_f32_u64(<2 x i64> %a) #0 {
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; CHECK: ucvtf v{{[0-9]+}}.2d, v{{[0-9]+}}.2d
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; CHECK: fcvtn v{{[0-9]+}}.2s, v{{[0-9]+}}.2d
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%vcvt.i = uitofp <2 x i64> %a to <2 x float>
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ret <2 x float> %vcvt.i
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}
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define <4 x float> @test_vcvt_f32_s16(<4 x i16> %a) #0 {
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; CHECK: sshll v{{[0-9]+}}.4s, v{{[0-9]+}}.4h, #0
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; CHECK: scvtf v{{[0-9]+}}.4s, v{{[0-9]+}}.4s
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%vcvt.i = sitofp <4 x i16> %a to <4 x float>
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ret <4 x float> %vcvt.i
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}
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define <4 x float> @test_vcvt_f32_u16(<4 x i16> %a) #0 {
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; CHECK: ushll v{{[0-9]+}}.4s, v{{[0-9]+}}.4h, #0
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; CHECK: ucvtf v{{[0-9]+}}.4s, v{{[0-9]+}}.4s
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%vcvt.i = uitofp <4 x i16> %a to <4 x float>
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ret <4 x float> %vcvt.i
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}
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define <2 x double> @test_vcvt_f64_s32(<2 x i32> %a) #0 {
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; CHECK: sshll v{{[0-9]+}}.2d, v{{[0-9]+}}.2s, #0
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; CHECK: scvtf v{{[0-9]+}}.2d, v{{[0-9]+}}.2d
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%vcvt.i = sitofp <2 x i32> %a to <2 x double>
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ret <2 x double> %vcvt.i
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}
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define <2 x double> @test_vcvt_f64_u32(<2 x i32> %a) #0 {
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; CHECK: ushll v{{[0-9]+}}.2d, v{{[0-9]+}}.2s, #0
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; CHECK: ucvtf v{{[0-9]+}}.2d, v{{[0-9]+}}.2d
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%vcvt.i = uitofp <2 x i32> %a to <2 x double>
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ret <2 x double> %vcvt.i
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}
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define <1 x double> @test_vcvt_f64_s8(<1 x i8> %a) #0 {
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; CHECK: umov w{{[0-9]+}}, v{{[0-9]+}}.b[0]
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; CHECK: sxtb w{{[0-9]+}}, w{{[0-9]+}}
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; CHECK: scvtf d{{[0-9]+}}, w{{[0-9]+}}
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%vcvt.i = sitofp <1 x i8> %a to <1 x double>
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ret <1 x double> %vcvt.i
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}
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define <1 x double> @test_vcvt_f64_u8(<1 x i8> %a) #0 {
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; CHECK: umov w{{[0-9]+}}, v{{[0-9]+}}.b[0]
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; CHECK: and w{{[0-9]+}}, w{{[0-9]+}}, #0xff
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; CHECK: ucvtf d{{[0-9]+}}, w{{[0-9]+}}
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%vcvt.i = uitofp <1 x i8> %a to <1 x double>
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ret <1 x double> %vcvt.i
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}
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define <1 x double> @test_vcvt_f64_s16(<1 x i16> %a) #0 {
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; CHECK: umov w{{[0-9]+}}, v{{[0-9]+}}.h[0]
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; CHECK: sxth w{{[0-9]+}}, w{{[0-9]+}}
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; CHECK: scvtf d{{[0-9]+}}, w{{[0-9]+}}
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%vcvt.i = sitofp <1 x i16> %a to <1 x double>
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ret <1 x double> %vcvt.i
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}
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define <1 x double> @test_vcvt_f64_u16(<1 x i16> %a) #0 {
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; CHECK: umov w{{[0-9]+}}, v{{[0-9]+}}.h[0]
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; CHECK: and w{{[0-9]+}}, w{{[0-9]+}}, #0xffff
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; CHECK: ucvtf d{{[0-9]+}}, w{{[0-9]+}}
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%vcvt.i = uitofp <1 x i16> %a to <1 x double>
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ret <1 x double> %vcvt.i
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}
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define <1 x double> @test_vcvt_f64_s32_v1(<1 x i32> %a) #0 {
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; CHECK: fmov w{{[0-9]+}}, s{{[0-9]+}}
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; CHECK: scvtf d{{[0-9]+}}, w{{[0-9]+}}
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%vcvt.i = sitofp <1 x i32> %a to <1 x double>
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ret <1 x double> %vcvt.i
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}
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define <1 x double> @test_vcvt_f64_u32_v1(<1 x i32> %a) #0 {
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; CHECK: fmov w{{[0-9]+}}, s{{[0-9]+}}
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; CHECK: ucvtf d{{[0-9]+}}, w{{[0-9]+}}
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%vcvt.i = uitofp <1 x i32> %a to <1 x double>
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ret <1 x double> %vcvt.i
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}
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declare <2 x double> @llvm.sqrt.v2f64(<2 x double>) #2
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declare <4 x float> @llvm.sqrt.v4f32(<4 x float>) #2
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