forked from OSchip/llvm-project
[x86] Merge the bitwise operation shuffle combining into the common test
file, adding assertions across the ISA variants for it. llvm-svn: 218858
This commit is contained in:
Chandler Carruth
parent
3c7bf04c87
commit
2110501822
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@ -1,253 +0,0 @@
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; RUN: llc < %s -mtriple=x86_64-unknown-linux-gnu -mcpu=corei7 | FileCheck %s
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; Verify that the DAGCombiner correctly folds according to the following rules:
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; fold (AND (shuf (A, C), shuf (B, C)) -> shuf (AND (A, B), C)
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; fold (OR (shuf (A, C), shuf (B, C)) -> shuf (OR (A, B), C)
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; fold (XOR (shuf (A, C), shuf (B, C)) -> shuf (XOR (A, B), V_0)
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; fold (AND (shuf (C, A), shuf (C, B)) -> shuf (C, AND (A, B))
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; fold (OR (shuf (C, A), shuf (C, B)) -> shuf (C, OR (A, B))
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; fold (XOR (shuf (C, A), shuf (C, B)) -> shuf (V_0, XOR (A, B))
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define <4 x i32> @test1(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
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%shuf1 = shufflevector <4 x i32> %a, <4 x i32> %c, <4 x i32><i32 0, i32 2, i32 1, i32 3>
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%shuf2 = shufflevector <4 x i32> %b, <4 x i32> %c, <4 x i32><i32 0, i32 2, i32 1, i32 3>
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%and = and <4 x i32> %shuf1, %shuf2
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ret <4 x i32> %and
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}
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; CHECK-LABEL: test1
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; CHECK-NOT: pshufd
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; CHECK: pand
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; CHECK-NEXT: pshufd
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; CHECK-NEXT: ret
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define <4 x i32> @test2(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
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%shuf1 = shufflevector <4 x i32> %a, <4 x i32> %c, <4 x i32><i32 0, i32 2, i32 1, i32 3>
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%shuf2 = shufflevector <4 x i32> %b, <4 x i32> %c, <4 x i32><i32 0, i32 2, i32 1, i32 3>
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%or = or <4 x i32> %shuf1, %shuf2
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ret <4 x i32> %or
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}
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; CHECK-LABEL: test2
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; CHECK-NOT: pshufd
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; CHECK: por
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; CHECK-NEXT: pshufd
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; CHECK-NEXT: ret
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define <4 x i32> @test3(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
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%shuf1 = shufflevector <4 x i32> %a, <4 x i32> %c, <4 x i32><i32 0, i32 2, i32 1, i32 3>
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%shuf2 = shufflevector <4 x i32> %b, <4 x i32> %c, <4 x i32><i32 0, i32 2, i32 1, i32 3>
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%xor = xor <4 x i32> %shuf1, %shuf2
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ret <4 x i32> %xor
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}
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; CHECK-LABEL: test3
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; CHECK-NOT: pshufd
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; CHECK: pxor
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; CHECK-NEXT: pshufd
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; CHECK-NEXT: ret
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define <4 x i32> @test4(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
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%shuf1 = shufflevector <4 x i32> %c, <4 x i32> %a, <4 x i32><i32 4, i32 6, i32 5, i32 7>
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%shuf2 = shufflevector <4 x i32> %c, <4 x i32> %b, <4 x i32><i32 4, i32 6, i32 5, i32 7>
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%and = and <4 x i32> %shuf1, %shuf2
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ret <4 x i32> %and
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}
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; CHECK-LABEL: test4
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; CHECK-NOT: pshufd
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; CHECK: pand
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; CHECK-NEXT: pshufd
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; CHECK-NEXT: ret
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define <4 x i32> @test5(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
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%shuf1 = shufflevector <4 x i32> %c, <4 x i32> %a, <4 x i32><i32 4, i32 6, i32 5, i32 7>
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%shuf2 = shufflevector <4 x i32> %c, <4 x i32> %b, <4 x i32><i32 4, i32 6, i32 5, i32 7>
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%or = or <4 x i32> %shuf1, %shuf2
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ret <4 x i32> %or
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}
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; CHECK-LABEL: test5
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; CHECK-NOT: pshufd
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; CHECK: por
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; CHECK-NEXT: pshufd
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; CHECK-NEXT: ret
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define <4 x i32> @test6(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
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%shuf1 = shufflevector <4 x i32> %c, <4 x i32> %a, <4 x i32><i32 4, i32 6, i32 5, i32 7>
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%shuf2 = shufflevector <4 x i32> %c, <4 x i32> %b, <4 x i32><i32 4, i32 6, i32 5, i32 7>
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%xor = xor <4 x i32> %shuf1, %shuf2
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ret <4 x i32> %xor
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}
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; CHECK-LABEL: test6
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; CHECK-NOT: pshufd
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; CHECK: pxor
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; CHECK-NEXT: pshufd
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; CHECK-NEXT: ret
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; Verify that DAGCombiner moves the shuffle after the xor/and/or even if shuffles
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; are not performing a swizzle operations.
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define <4 x i32> @test1b(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
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%shuf1 = shufflevector <4 x i32> %a, <4 x i32> %c, <4 x i32><i32 0, i32 5, i32 2, i32 7>
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%shuf2 = shufflevector <4 x i32> %b, <4 x i32> %c, <4 x i32><i32 0, i32 5, i32 2, i32 7>
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%and = and <4 x i32> %shuf1, %shuf2
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ret <4 x i32> %and
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}
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; CHECK-LABEL: test1b
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; CHECK-NOT: blendps
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; CHECK: andps
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; CHECK-NEXT: blendps
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; CHECK-NEXT: ret
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define <4 x i32> @test2b(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
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%shuf1 = shufflevector <4 x i32> %a, <4 x i32> %c, <4 x i32><i32 0, i32 5, i32 2, i32 7>
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%shuf2 = shufflevector <4 x i32> %b, <4 x i32> %c, <4 x i32><i32 0, i32 5, i32 2, i32 7>
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%or = or <4 x i32> %shuf1, %shuf2
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ret <4 x i32> %or
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}
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; CHECK-LABEL: test2b
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; CHECK-NOT: blendps
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; CHECK: orps
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; CHECK-NEXT: blendps
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; CHECK-NEXT: ret
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define <4 x i32> @test3b(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
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%shuf1 = shufflevector <4 x i32> %a, <4 x i32> %c, <4 x i32><i32 0, i32 5, i32 2, i32 7>
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%shuf2 = shufflevector <4 x i32> %b, <4 x i32> %c, <4 x i32><i32 0, i32 5, i32 2, i32 7>
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%xor = xor <4 x i32> %shuf1, %shuf2
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ret <4 x i32> %xor
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}
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; CHECK-LABEL: test3b
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; CHECK-NOT: blendps
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; CHECK: xorps
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; CHECK-NEXT: xorps
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; CHECK-NEXT: blendps
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; CHECK-NEXT: ret
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define <4 x i32> @test4b(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
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%shuf1 = shufflevector <4 x i32> %c, <4 x i32> %a, <4 x i32><i32 0, i32 5, i32 2, i32 7>
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%shuf2 = shufflevector <4 x i32> %c, <4 x i32> %b, <4 x i32><i32 0, i32 5, i32 2, i32 7>
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%and = and <4 x i32> %shuf1, %shuf2
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ret <4 x i32> %and
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}
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; CHECK-LABEL: test4b
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; CHECK-NOT: blendps
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; CHECK: andps
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; CHECK-NEXT: blendps
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; CHECK: ret
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define <4 x i32> @test5b(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
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%shuf1 = shufflevector <4 x i32> %c, <4 x i32> %a, <4 x i32><i32 0, i32 5, i32 2, i32 7>
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%shuf2 = shufflevector <4 x i32> %c, <4 x i32> %b, <4 x i32><i32 0, i32 5, i32 2, i32 7>
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%or = or <4 x i32> %shuf1, %shuf2
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ret <4 x i32> %or
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}
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; CHECK-LABEL: test5b
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; CHECK-NOT: blendps
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; CHECK: orps
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; CHECK-NEXT: blendps
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; CHECK: ret
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define <4 x i32> @test6b(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
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%shuf1 = shufflevector <4 x i32> %c, <4 x i32> %a, <4 x i32><i32 0, i32 5, i32 2, i32 7>
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%shuf2 = shufflevector <4 x i32> %c, <4 x i32> %b, <4 x i32><i32 0, i32 5, i32 2, i32 7>
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%xor = xor <4 x i32> %shuf1, %shuf2
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ret <4 x i32> %xor
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}
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; CHECK-LABEL: test6b
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; CHECK-NOT: blendps
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; CHECK: xorps
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; CHECK-NEXT: xorps
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; CHECK-NEXT: blendps
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; CHECK: ret
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define <4 x i32> @test1c(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
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%shuf1 = shufflevector <4 x i32> %a, <4 x i32> %c, <4 x i32><i32 0, i32 2, i32 5, i32 7>
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%shuf2 = shufflevector <4 x i32> %b, <4 x i32> %c, <4 x i32><i32 0, i32 2, i32 5, i32 7>
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%and = and <4 x i32> %shuf1, %shuf2
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ret <4 x i32> %and
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}
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; CHECK-LABEL: test1c
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; CHECK-NOT: shufps
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; CHECK: andps
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; CHECK-NEXT: shufps
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; CHECK-NEXT: ret
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define <4 x i32> @test2c(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
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%shuf1 = shufflevector <4 x i32> %a, <4 x i32> %c, <4 x i32><i32 0, i32 2, i32 5, i32 7>
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%shuf2 = shufflevector <4 x i32> %b, <4 x i32> %c, <4 x i32><i32 0, i32 2, i32 5, i32 7>
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%or = or <4 x i32> %shuf1, %shuf2
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ret <4 x i32> %or
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}
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; CHECK-LABEL: test2c
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; CHECK-NOT: shufps
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; CHECK: orps
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; CHECK-NEXT: shufps
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; CHECK-NEXT: ret
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define <4 x i32> @test3c(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
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%shuf1 = shufflevector <4 x i32> %a, <4 x i32> %c, <4 x i32><i32 0, i32 2, i32 5, i32 7>
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%shuf2 = shufflevector <4 x i32> %b, <4 x i32> %c, <4 x i32><i32 0, i32 2, i32 5, i32 7>
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%xor = xor <4 x i32> %shuf1, %shuf2
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ret <4 x i32> %xor
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}
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; CHECK-LABEL: test3c
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; CHECK-NOT: shufps
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; CHECK: xorps
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; CHECK-NEXT: xorps
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; CHECK-NEXT: shufps
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; CHECK-NEXT: ret
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define <4 x i32> @test4c(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
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%shuf1 = shufflevector <4 x i32> %c, <4 x i32> %a, <4 x i32><i32 0, i32 2, i32 5, i32 7>
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%shuf2 = shufflevector <4 x i32> %c, <4 x i32> %b, <4 x i32><i32 0, i32 2, i32 5, i32 7>
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%and = and <4 x i32> %shuf1, %shuf2
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ret <4 x i32> %and
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}
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; CHECK-LABEL: test4c
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; CHECK-NOT: shufps
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; CHECK: andps
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; CHECK-NEXT: shufps
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; CHECK: ret
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define <4 x i32> @test5c(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
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%shuf1 = shufflevector <4 x i32> %c, <4 x i32> %a, <4 x i32><i32 0, i32 2, i32 5, i32 7>
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%shuf2 = shufflevector <4 x i32> %c, <4 x i32> %b, <4 x i32><i32 0, i32 2, i32 5, i32 7>
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%or = or <4 x i32> %shuf1, %shuf2
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ret <4 x i32> %or
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}
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; CHECK-LABEL: test5c
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; CHECK-NOT: shufps
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; CHECK: orps
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; CHECK-NEXT: shufps
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; CHECK: ret
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define <4 x i32> @test6c(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
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%shuf1 = shufflevector <4 x i32> %c, <4 x i32> %a, <4 x i32><i32 0, i32 2, i32 5, i32 7>
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%shuf2 = shufflevector <4 x i32> %c, <4 x i32> %b, <4 x i32><i32 0, i32 2, i32 5, i32 7>
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%xor = xor <4 x i32> %shuf1, %shuf2
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ret <4 x i32> %xor
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}
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; CHECK-LABEL: test6c
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; CHECK-NOT: shufps
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; CHECK: xorps
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; CHECK-NEXT: xorps
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; CHECK-NEXT: shufps
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; CHECK: ret
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@ -159,3 +159,471 @@ entry:
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%d = call <8 x i16> @llvm.x86.sse2.pshufh.w(<8 x i16> %c, i8 27)
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ret <8 x i16> %d
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}
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define <4 x i32> @combine_bitwise_ops_test1(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
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; SSE-LABEL: combine_bitwise_ops_test1:
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; SSE: # BB#0:
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; SSE-NEXT: pand %xmm1, %xmm0
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; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,1,3]
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; SSE-NEXT: retq
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;
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; AVX-LABEL: combine_bitwise_ops_test1:
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; AVX: # BB#0:
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; AVX-NEXT: vpand %xmm1, %xmm0, %xmm0
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; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,2,1,3]
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; AVX-NEXT: retq
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%shuf1 = shufflevector <4 x i32> %a, <4 x i32> %c, <4 x i32><i32 0, i32 2, i32 1, i32 3>
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%shuf2 = shufflevector <4 x i32> %b, <4 x i32> %c, <4 x i32><i32 0, i32 2, i32 1, i32 3>
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%and = and <4 x i32> %shuf1, %shuf2
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ret <4 x i32> %and
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}
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define <4 x i32> @combine_bitwise_ops_test2(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
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; SSE-LABEL: combine_bitwise_ops_test2:
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; SSE: # BB#0:
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; SSE-NEXT: por %xmm1, %xmm0
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; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,1,3]
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; SSE-NEXT: retq
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;
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; AVX-LABEL: combine_bitwise_ops_test2:
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; AVX: # BB#0:
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; AVX-NEXT: vpor %xmm1, %xmm0, %xmm0
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; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,2,1,3]
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; AVX-NEXT: retq
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%shuf1 = shufflevector <4 x i32> %a, <4 x i32> %c, <4 x i32><i32 0, i32 2, i32 1, i32 3>
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%shuf2 = shufflevector <4 x i32> %b, <4 x i32> %c, <4 x i32><i32 0, i32 2, i32 1, i32 3>
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%or = or <4 x i32> %shuf1, %shuf2
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ret <4 x i32> %or
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}
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define <4 x i32> @combine_bitwise_ops_test3(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
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; SSE-LABEL: combine_bitwise_ops_test3:
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; SSE: # BB#0:
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; SSE-NEXT: pxor %xmm1, %xmm0
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; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,1,3]
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; SSE-NEXT: retq
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;
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; AVX-LABEL: combine_bitwise_ops_test3:
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; AVX: # BB#0:
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; AVX-NEXT: vpxor %xmm1, %xmm0, %xmm0
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; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,2,1,3]
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; AVX-NEXT: retq
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%shuf1 = shufflevector <4 x i32> %a, <4 x i32> %c, <4 x i32><i32 0, i32 2, i32 1, i32 3>
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%shuf2 = shufflevector <4 x i32> %b, <4 x i32> %c, <4 x i32><i32 0, i32 2, i32 1, i32 3>
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%xor = xor <4 x i32> %shuf1, %shuf2
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ret <4 x i32> %xor
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}
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define <4 x i32> @combine_bitwise_ops_test4(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
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; SSE-LABEL: combine_bitwise_ops_test4:
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; SSE: # BB#0:
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; SSE-NEXT: pand %xmm1, %xmm0
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; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,1,3]
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; SSE-NEXT: retq
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;
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; AVX-LABEL: combine_bitwise_ops_test4:
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; AVX: # BB#0:
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; AVX-NEXT: vpand %xmm1, %xmm0, %xmm0
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; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,2,1,3]
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; AVX-NEXT: retq
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%shuf1 = shufflevector <4 x i32> %c, <4 x i32> %a, <4 x i32><i32 4, i32 6, i32 5, i32 7>
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||||
%shuf2 = shufflevector <4 x i32> %c, <4 x i32> %b, <4 x i32><i32 4, i32 6, i32 5, i32 7>
|
||||
%and = and <4 x i32> %shuf1, %shuf2
|
||||
ret <4 x i32> %and
|
||||
}
|
||||
|
||||
define <4 x i32> @combine_bitwise_ops_test5(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
|
||||
; SSE-LABEL: combine_bitwise_ops_test5:
|
||||
; SSE: # BB#0:
|
||||
; SSE-NEXT: por %xmm1, %xmm0
|
||||
; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,1,3]
|
||||
; SSE-NEXT: retq
|
||||
;
|
||||
; AVX-LABEL: combine_bitwise_ops_test5:
|
||||
; AVX: # BB#0:
|
||||
; AVX-NEXT: vpor %xmm1, %xmm0, %xmm0
|
||||
; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,2,1,3]
|
||||
; AVX-NEXT: retq
|
||||
%shuf1 = shufflevector <4 x i32> %c, <4 x i32> %a, <4 x i32><i32 4, i32 6, i32 5, i32 7>
|
||||
%shuf2 = shufflevector <4 x i32> %c, <4 x i32> %b, <4 x i32><i32 4, i32 6, i32 5, i32 7>
|
||||
%or = or <4 x i32> %shuf1, %shuf2
|
||||
ret <4 x i32> %or
|
||||
}
|
||||
|
||||
define <4 x i32> @combine_bitwise_ops_test6(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
|
||||
; SSE-LABEL: combine_bitwise_ops_test6:
|
||||
; SSE: # BB#0:
|
||||
; SSE-NEXT: pxor %xmm1, %xmm0
|
||||
; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,1,3]
|
||||
; SSE-NEXT: retq
|
||||
;
|
||||
; AVX-LABEL: combine_bitwise_ops_test6:
|
||||
; AVX: # BB#0:
|
||||
; AVX-NEXT: vpxor %xmm1, %xmm0, %xmm0
|
||||
; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,2,1,3]
|
||||
; AVX-NEXT: retq
|
||||
%shuf1 = shufflevector <4 x i32> %c, <4 x i32> %a, <4 x i32><i32 4, i32 6, i32 5, i32 7>
|
||||
%shuf2 = shufflevector <4 x i32> %c, <4 x i32> %b, <4 x i32><i32 4, i32 6, i32 5, i32 7>
|
||||
%xor = xor <4 x i32> %shuf1, %shuf2
|
||||
ret <4 x i32> %xor
|
||||
}
|
||||
|
||||
|
||||
; Verify that DAGCombiner moves the shuffle after the xor/and/or even if shuffles
|
||||
; are not performing a swizzle operations.
|
||||
|
||||
define <4 x i32> @combine_bitwise_ops_test1b(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
|
||||
; SSE2-LABEL: combine_bitwise_ops_test1b:
|
||||
; SSE2: # BB#0:
|
||||
; SSE2-NEXT: andps %xmm1, %xmm0
|
||||
; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2],xmm2[1,3]
|
||||
; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,1,3]
|
||||
; SSE2-NEXT: retq
|
||||
;
|
||||
; SSSE3-LABEL: combine_bitwise_ops_test1b:
|
||||
; SSSE3: # BB#0:
|
||||
; SSSE3-NEXT: andps %xmm1, %xmm0
|
||||
; SSSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2],xmm2[1,3]
|
||||
; SSSE3-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,1,3]
|
||||
; SSSE3-NEXT: retq
|
||||
;
|
||||
; SSE41-LABEL: combine_bitwise_ops_test1b:
|
||||
; SSE41: # BB#0:
|
||||
; SSE41-NEXT: andps %xmm1, %xmm0
|
||||
; SSE41-NEXT: blendps {{.*#+}} xmm0 = xmm0[0],xmm2[1],xmm0[2],xmm2[3]
|
||||
; SSE41-NEXT: retq
|
||||
;
|
||||
; AVX1-LABEL: combine_bitwise_ops_test1b:
|
||||
; AVX1: # BB#0:
|
||||
; AVX1-NEXT: vandps %xmm1, %xmm0, %xmm0
|
||||
; AVX1-NEXT: vblendps {{.*#+}} xmm0 = xmm0[0],xmm2[1],xmm0[2],xmm2[3]
|
||||
; AVX1-NEXT: retq
|
||||
;
|
||||
; AVX2-LABEL: combine_bitwise_ops_test1b:
|
||||
; AVX2: # BB#0:
|
||||
; AVX2-NEXT: vpand %xmm1, %xmm0, %xmm0
|
||||
; AVX2-NEXT: vpblendd {{.*#+}} xmm0 = xmm0[0],xmm2[1],xmm0[2],xmm2[3]
|
||||
; AVX2-NEXT: retq
|
||||
%shuf1 = shufflevector <4 x i32> %a, <4 x i32> %c, <4 x i32><i32 0, i32 5, i32 2, i32 7>
|
||||
%shuf2 = shufflevector <4 x i32> %b, <4 x i32> %c, <4 x i32><i32 0, i32 5, i32 2, i32 7>
|
||||
%and = and <4 x i32> %shuf1, %shuf2
|
||||
ret <4 x i32> %and
|
||||
}
|
||||
|
||||
define <4 x i32> @combine_bitwise_ops_test2b(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
|
||||
; SSE2-LABEL: combine_bitwise_ops_test2b:
|
||||
; SSE2: # BB#0:
|
||||
; SSE2-NEXT: orps %xmm1, %xmm0
|
||||
; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2],xmm2[1,3]
|
||||
; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,1,3]
|
||||
; SSE2-NEXT: retq
|
||||
;
|
||||
; SSSE3-LABEL: combine_bitwise_ops_test2b:
|
||||
; SSSE3: # BB#0:
|
||||
; SSSE3-NEXT: orps %xmm1, %xmm0
|
||||
; SSSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2],xmm2[1,3]
|
||||
; SSSE3-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,1,3]
|
||||
; SSSE3-NEXT: retq
|
||||
;
|
||||
; SSE41-LABEL: combine_bitwise_ops_test2b:
|
||||
; SSE41: # BB#0:
|
||||
; SSE41-NEXT: orps %xmm1, %xmm0
|
||||
; SSE41-NEXT: blendps {{.*#+}} xmm0 = xmm0[0],xmm2[1],xmm0[2],xmm2[3]
|
||||
; SSE41-NEXT: retq
|
||||
;
|
||||
; AVX1-LABEL: combine_bitwise_ops_test2b:
|
||||
; AVX1: # BB#0:
|
||||
; AVX1-NEXT: vorps %xmm1, %xmm0, %xmm0
|
||||
; AVX1-NEXT: vblendps {{.*#+}} xmm0 = xmm0[0],xmm2[1],xmm0[2],xmm2[3]
|
||||
; AVX1-NEXT: retq
|
||||
;
|
||||
; AVX2-LABEL: combine_bitwise_ops_test2b:
|
||||
; AVX2: # BB#0:
|
||||
; AVX2-NEXT: vpor %xmm1, %xmm0, %xmm0
|
||||
; AVX2-NEXT: vpblendd {{.*#+}} xmm0 = xmm0[0],xmm2[1],xmm0[2],xmm2[3]
|
||||
; AVX2-NEXT: retq
|
||||
%shuf1 = shufflevector <4 x i32> %a, <4 x i32> %c, <4 x i32><i32 0, i32 5, i32 2, i32 7>
|
||||
%shuf2 = shufflevector <4 x i32> %b, <4 x i32> %c, <4 x i32><i32 0, i32 5, i32 2, i32 7>
|
||||
%or = or <4 x i32> %shuf1, %shuf2
|
||||
ret <4 x i32> %or
|
||||
}
|
||||
|
||||
define <4 x i32> @combine_bitwise_ops_test3b(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
|
||||
; SSE2-LABEL: combine_bitwise_ops_test3b:
|
||||
; SSE2: # BB#0:
|
||||
; SSE2-NEXT: xorps %xmm1, %xmm0
|
||||
; SSE2-NEXT: xorps %xmm1, %xmm1
|
||||
; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2],xmm1[1,3]
|
||||
; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,1,3]
|
||||
; SSE2-NEXT: retq
|
||||
;
|
||||
; SSSE3-LABEL: combine_bitwise_ops_test3b:
|
||||
; SSSE3: # BB#0:
|
||||
; SSSE3-NEXT: xorps %xmm1, %xmm0
|
||||
; SSSE3-NEXT: xorps %xmm1, %xmm1
|
||||
; SSSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2],xmm1[1,3]
|
||||
; SSSE3-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,1,3]
|
||||
; SSSE3-NEXT: retq
|
||||
;
|
||||
; SSE41-LABEL: combine_bitwise_ops_test3b:
|
||||
; SSE41: # BB#0:
|
||||
; SSE41-NEXT: xorps %xmm1, %xmm0
|
||||
; SSE41-NEXT: xorps %xmm1, %xmm1
|
||||
; SSE41-NEXT: blendps {{.*#+}} xmm0 = xmm0[0],xmm1[1],xmm0[2],xmm1[3]
|
||||
; SSE41-NEXT: retq
|
||||
;
|
||||
; AVX1-LABEL: combine_bitwise_ops_test3b:
|
||||
; AVX1: # BB#0:
|
||||
; AVX1-NEXT: vxorps %xmm1, %xmm0, %xmm0
|
||||
; AVX1-NEXT: vxorps %xmm1, %xmm1, %xmm1
|
||||
; AVX1-NEXT: vblendps {{.*#+}} xmm0 = xmm0[0],xmm1[1],xmm0[2],xmm1[3]
|
||||
; AVX1-NEXT: retq
|
||||
;
|
||||
; AVX2-LABEL: combine_bitwise_ops_test3b:
|
||||
; AVX2: # BB#0:
|
||||
; AVX2-NEXT: vpxor %xmm1, %xmm0, %xmm0
|
||||
; AVX2-NEXT: vpxor %xmm1, %xmm1, %xmm1
|
||||
; AVX2-NEXT: vpblendd {{.*#+}} xmm0 = xmm0[0],xmm1[1],xmm0[2],xmm1[3]
|
||||
; AVX2-NEXT: retq
|
||||
%shuf1 = shufflevector <4 x i32> %a, <4 x i32> %c, <4 x i32><i32 0, i32 5, i32 2, i32 7>
|
||||
%shuf2 = shufflevector <4 x i32> %b, <4 x i32> %c, <4 x i32><i32 0, i32 5, i32 2, i32 7>
|
||||
%xor = xor <4 x i32> %shuf1, %shuf2
|
||||
ret <4 x i32> %xor
|
||||
}
|
||||
|
||||
define <4 x i32> @combine_bitwise_ops_test4b(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
|
||||
; SSE2-LABEL: combine_bitwise_ops_test4b:
|
||||
; SSE2: # BB#0:
|
||||
; SSE2-NEXT: andps %xmm1, %xmm0
|
||||
; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,2],xmm0[1,3]
|
||||
; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm2[0,2,1,3]
|
||||
; SSE2-NEXT: retq
|
||||
;
|
||||
; SSSE3-LABEL: combine_bitwise_ops_test4b:
|
||||
; SSSE3: # BB#0:
|
||||
; SSSE3-NEXT: andps %xmm1, %xmm0
|
||||
; SSSE3-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,2],xmm0[1,3]
|
||||
; SSSE3-NEXT: pshufd {{.*#+}} xmm0 = xmm2[0,2,1,3]
|
||||
; SSSE3-NEXT: retq
|
||||
;
|
||||
; SSE41-LABEL: combine_bitwise_ops_test4b:
|
||||
; SSE41: # BB#0:
|
||||
; SSE41-NEXT: andps %xmm1, %xmm0
|
||||
; SSE41-NEXT: blendps {{.*#+}} xmm2 = xmm2[0],xmm0[1],xmm2[2],xmm0[3]
|
||||
; SSE41-NEXT: movaps %xmm2, %xmm0
|
||||
; SSE41-NEXT: retq
|
||||
;
|
||||
; AVX1-LABEL: combine_bitwise_ops_test4b:
|
||||
; AVX1: # BB#0:
|
||||
; AVX1-NEXT: vandps %xmm1, %xmm0, %xmm0
|
||||
; AVX1-NEXT: vblendps {{.*#+}} xmm0 = xmm2[0],xmm0[1],xmm2[2],xmm0[3]
|
||||
; AVX1-NEXT: retq
|
||||
;
|
||||
; AVX2-LABEL: combine_bitwise_ops_test4b:
|
||||
; AVX2: # BB#0:
|
||||
; AVX2-NEXT: vpand %xmm1, %xmm0, %xmm0
|
||||
; AVX2-NEXT: vpblendd {{.*#+}} xmm0 = xmm2[0],xmm0[1],xmm2[2],xmm0[3]
|
||||
; AVX2-NEXT: retq
|
||||
%shuf1 = shufflevector <4 x i32> %c, <4 x i32> %a, <4 x i32><i32 0, i32 5, i32 2, i32 7>
|
||||
%shuf2 = shufflevector <4 x i32> %c, <4 x i32> %b, <4 x i32><i32 0, i32 5, i32 2, i32 7>
|
||||
%and = and <4 x i32> %shuf1, %shuf2
|
||||
ret <4 x i32> %and
|
||||
}
|
||||
|
||||
define <4 x i32> @combine_bitwise_ops_test5b(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
|
||||
; SSE2-LABEL: combine_bitwise_ops_test5b:
|
||||
; SSE2: # BB#0:
|
||||
; SSE2-NEXT: orps %xmm1, %xmm0
|
||||
; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,2],xmm0[1,3]
|
||||
; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm2[0,2,1,3]
|
||||
; SSE2-NEXT: retq
|
||||
;
|
||||
; SSSE3-LABEL: combine_bitwise_ops_test5b:
|
||||
; SSSE3: # BB#0:
|
||||
; SSSE3-NEXT: orps %xmm1, %xmm0
|
||||
; SSSE3-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,2],xmm0[1,3]
|
||||
; SSSE3-NEXT: pshufd {{.*#+}} xmm0 = xmm2[0,2,1,3]
|
||||
; SSSE3-NEXT: retq
|
||||
;
|
||||
; SSE41-LABEL: combine_bitwise_ops_test5b:
|
||||
; SSE41: # BB#0:
|
||||
; SSE41-NEXT: orps %xmm1, %xmm0
|
||||
; SSE41-NEXT: blendps {{.*#+}} xmm2 = xmm2[0],xmm0[1],xmm2[2],xmm0[3]
|
||||
; SSE41-NEXT: movaps %xmm2, %xmm0
|
||||
; SSE41-NEXT: retq
|
||||
;
|
||||
; AVX1-LABEL: combine_bitwise_ops_test5b:
|
||||
; AVX1: # BB#0:
|
||||
; AVX1-NEXT: vorps %xmm1, %xmm0, %xmm0
|
||||
; AVX1-NEXT: vblendps {{.*#+}} xmm0 = xmm2[0],xmm0[1],xmm2[2],xmm0[3]
|
||||
; AVX1-NEXT: retq
|
||||
;
|
||||
; AVX2-LABEL: combine_bitwise_ops_test5b:
|
||||
; AVX2: # BB#0:
|
||||
; AVX2-NEXT: vpor %xmm1, %xmm0, %xmm0
|
||||
; AVX2-NEXT: vpblendd {{.*#+}} xmm0 = xmm2[0],xmm0[1],xmm2[2],xmm0[3]
|
||||
; AVX2-NEXT: retq
|
||||
%shuf1 = shufflevector <4 x i32> %c, <4 x i32> %a, <4 x i32><i32 0, i32 5, i32 2, i32 7>
|
||||
%shuf2 = shufflevector <4 x i32> %c, <4 x i32> %b, <4 x i32><i32 0, i32 5, i32 2, i32 7>
|
||||
%or = or <4 x i32> %shuf1, %shuf2
|
||||
ret <4 x i32> %or
|
||||
}
|
||||
|
||||
define <4 x i32> @combine_bitwise_ops_test6b(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
|
||||
; SSE2-LABEL: combine_bitwise_ops_test6b:
|
||||
; SSE2: # BB#0:
|
||||
; SSE2-NEXT: xorps %xmm1, %xmm0
|
||||
; SSE2-NEXT: xorps %xmm1, %xmm1
|
||||
; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,2],xmm0[1,3]
|
||||
; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm1[0,2,1,3]
|
||||
; SSE2-NEXT: retq
|
||||
;
|
||||
; SSSE3-LABEL: combine_bitwise_ops_test6b:
|
||||
; SSSE3: # BB#0:
|
||||
; SSSE3-NEXT: xorps %xmm1, %xmm0
|
||||
; SSSE3-NEXT: xorps %xmm1, %xmm1
|
||||
; SSSE3-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,2],xmm0[1,3]
|
||||
; SSSE3-NEXT: pshufd {{.*#+}} xmm0 = xmm1[0,2,1,3]
|
||||
; SSSE3-NEXT: retq
|
||||
;
|
||||
; SSE41-LABEL: combine_bitwise_ops_test6b:
|
||||
; SSE41: # BB#0:
|
||||
; SSE41-NEXT: xorps %xmm1, %xmm0
|
||||
; SSE41-NEXT: xorps %xmm1, %xmm1
|
||||
; SSE41-NEXT: blendps {{.*#+}} xmm1 = xmm1[0],xmm0[1],xmm1[2],xmm0[3]
|
||||
; SSE41-NEXT: movaps %xmm1, %xmm0
|
||||
; SSE41-NEXT: retq
|
||||
;
|
||||
; AVX1-LABEL: combine_bitwise_ops_test6b:
|
||||
; AVX1: # BB#0:
|
||||
; AVX1-NEXT: vxorps %xmm1, %xmm0, %xmm0
|
||||
; AVX1-NEXT: vxorps %xmm1, %xmm1, %xmm1
|
||||
; AVX1-NEXT: vblendps {{.*#+}} xmm0 = xmm1[0],xmm0[1],xmm1[2],xmm0[3]
|
||||
; AVX1-NEXT: retq
|
||||
;
|
||||
; AVX2-LABEL: combine_bitwise_ops_test6b:
|
||||
; AVX2: # BB#0:
|
||||
; AVX2-NEXT: vpxor %xmm1, %xmm0, %xmm0
|
||||
; AVX2-NEXT: vpxor %xmm1, %xmm1, %xmm1
|
||||
; AVX2-NEXT: vpblendd {{.*#+}} xmm0 = xmm1[0],xmm0[1],xmm1[2],xmm0[3]
|
||||
; AVX2-NEXT: retq
|
||||
%shuf1 = shufflevector <4 x i32> %c, <4 x i32> %a, <4 x i32><i32 0, i32 5, i32 2, i32 7>
|
||||
%shuf2 = shufflevector <4 x i32> %c, <4 x i32> %b, <4 x i32><i32 0, i32 5, i32 2, i32 7>
|
||||
%xor = xor <4 x i32> %shuf1, %shuf2
|
||||
ret <4 x i32> %xor
|
||||
}
|
||||
|
||||
define <4 x i32> @combine_bitwise_ops_test1c(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
|
||||
; SSE-LABEL: combine_bitwise_ops_test1c:
|
||||
; SSE: # BB#0:
|
||||
; SSE-NEXT: andps %xmm1, %xmm0
|
||||
; SSE-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2],xmm2[1,3]
|
||||
; SSE-NEXT: retq
|
||||
;
|
||||
; AVX-LABEL: combine_bitwise_ops_test1c:
|
||||
; AVX: # BB#0:
|
||||
; AVX-NEXT: vandps %xmm1, %xmm0, %xmm0
|
||||
; AVX-NEXT: vshufps {{.*#+}} xmm0 = xmm0[0,2],xmm2[1,3]
|
||||
; AVX-NEXT: retq
|
||||
%shuf1 = shufflevector <4 x i32> %a, <4 x i32> %c, <4 x i32><i32 0, i32 2, i32 5, i32 7>
|
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%shuf2 = shufflevector <4 x i32> %b, <4 x i32> %c, <4 x i32><i32 0, i32 2, i32 5, i32 7>
|
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%and = and <4 x i32> %shuf1, %shuf2
|
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ret <4 x i32> %and
|
||||
}
|
||||
|
||||
define <4 x i32> @combine_bitwise_ops_test2c(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
|
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; SSE-LABEL: combine_bitwise_ops_test2c:
|
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; SSE: # BB#0:
|
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; SSE-NEXT: orps %xmm1, %xmm0
|
||||
; SSE-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2],xmm2[1,3]
|
||||
; SSE-NEXT: retq
|
||||
;
|
||||
; AVX-LABEL: combine_bitwise_ops_test2c:
|
||||
; AVX: # BB#0:
|
||||
; AVX-NEXT: vorps %xmm1, %xmm0, %xmm0
|
||||
; AVX-NEXT: vshufps {{.*#+}} xmm0 = xmm0[0,2],xmm2[1,3]
|
||||
; AVX-NEXT: retq
|
||||
%shuf1 = shufflevector <4 x i32> %a, <4 x i32> %c, <4 x i32><i32 0, i32 2, i32 5, i32 7>
|
||||
%shuf2 = shufflevector <4 x i32> %b, <4 x i32> %c, <4 x i32><i32 0, i32 2, i32 5, i32 7>
|
||||
%or = or <4 x i32> %shuf1, %shuf2
|
||||
ret <4 x i32> %or
|
||||
}
|
||||
|
||||
define <4 x i32> @combine_bitwise_ops_test3c(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
|
||||
; SSE-LABEL: combine_bitwise_ops_test3c:
|
||||
; SSE: # BB#0:
|
||||
; SSE-NEXT: xorps %xmm1, %xmm0
|
||||
; SSE-NEXT: xorps %xmm1, %xmm1
|
||||
; SSE-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2],xmm1[1,3]
|
||||
; SSE-NEXT: retq
|
||||
;
|
||||
; AVX-LABEL: combine_bitwise_ops_test3c:
|
||||
; AVX: # BB#0:
|
||||
; AVX-NEXT: vxorps %xmm1, %xmm0, %xmm0
|
||||
; AVX-NEXT: vxorps %xmm1, %xmm1, %xmm1
|
||||
; AVX-NEXT: vshufps {{.*#+}} xmm0 = xmm0[0,2],xmm1[1,3]
|
||||
; AVX-NEXT: retq
|
||||
%shuf1 = shufflevector <4 x i32> %a, <4 x i32> %c, <4 x i32><i32 0, i32 2, i32 5, i32 7>
|
||||
%shuf2 = shufflevector <4 x i32> %b, <4 x i32> %c, <4 x i32><i32 0, i32 2, i32 5, i32 7>
|
||||
%xor = xor <4 x i32> %shuf1, %shuf2
|
||||
ret <4 x i32> %xor
|
||||
}
|
||||
|
||||
define <4 x i32> @combine_bitwise_ops_test4c(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
|
||||
; SSE-LABEL: combine_bitwise_ops_test4c:
|
||||
; SSE: # BB#0:
|
||||
; SSE-NEXT: andps %xmm1, %xmm0
|
||||
; SSE-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,2],xmm0[1,3]
|
||||
; SSE-NEXT: movaps %xmm2, %xmm0
|
||||
; SSE-NEXT: retq
|
||||
;
|
||||
; AVX-LABEL: combine_bitwise_ops_test4c:
|
||||
; AVX: # BB#0:
|
||||
; AVX-NEXT: vandps %xmm1, %xmm0, %xmm0
|
||||
; AVX-NEXT: vshufps {{.*#+}} xmm0 = xmm2[0,2],xmm0[1,3]
|
||||
; AVX-NEXT: retq
|
||||
%shuf1 = shufflevector <4 x i32> %c, <4 x i32> %a, <4 x i32><i32 0, i32 2, i32 5, i32 7>
|
||||
%shuf2 = shufflevector <4 x i32> %c, <4 x i32> %b, <4 x i32><i32 0, i32 2, i32 5, i32 7>
|
||||
%and = and <4 x i32> %shuf1, %shuf2
|
||||
ret <4 x i32> %and
|
||||
}
|
||||
|
||||
define <4 x i32> @combine_bitwise_ops_test5c(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
|
||||
; SSE-LABEL: combine_bitwise_ops_test5c:
|
||||
; SSE: # BB#0:
|
||||
; SSE-NEXT: orps %xmm1, %xmm0
|
||||
; SSE-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,2],xmm0[1,3]
|
||||
; SSE-NEXT: movaps %xmm2, %xmm0
|
||||
; SSE-NEXT: retq
|
||||
;
|
||||
; AVX-LABEL: combine_bitwise_ops_test5c:
|
||||
; AVX: # BB#0:
|
||||
; AVX-NEXT: vorps %xmm1, %xmm0, %xmm0
|
||||
; AVX-NEXT: vshufps {{.*#+}} xmm0 = xmm2[0,2],xmm0[1,3]
|
||||
; AVX-NEXT: retq
|
||||
%shuf1 = shufflevector <4 x i32> %c, <4 x i32> %a, <4 x i32><i32 0, i32 2, i32 5, i32 7>
|
||||
%shuf2 = shufflevector <4 x i32> %c, <4 x i32> %b, <4 x i32><i32 0, i32 2, i32 5, i32 7>
|
||||
%or = or <4 x i32> %shuf1, %shuf2
|
||||
ret <4 x i32> %or
|
||||
}
|
||||
|
||||
define <4 x i32> @combine_bitwise_ops_test6c(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
|
||||
; SSE-LABEL: combine_bitwise_ops_test6c:
|
||||
; SSE: # BB#0:
|
||||
; SSE-NEXT: xorps %xmm1, %xmm0
|
||||
; SSE-NEXT: xorps %xmm1, %xmm1
|
||||
; SSE-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,2],xmm0[1,3]
|
||||
; SSE-NEXT: movaps %xmm1, %xmm0
|
||||
; SSE-NEXT: retq
|
||||
;
|
||||
; AVX-LABEL: combine_bitwise_ops_test6c:
|
||||
; AVX: # BB#0:
|
||||
; AVX-NEXT: vxorps %xmm1, %xmm0, %xmm0
|
||||
; AVX-NEXT: vxorps %xmm1, %xmm1, %xmm1
|
||||
; AVX-NEXT: vshufps {{.*#+}} xmm0 = xmm1[0,2],xmm0[1,3]
|
||||
; AVX-NEXT: retq
|
||||
%shuf1 = shufflevector <4 x i32> %c, <4 x i32> %a, <4 x i32><i32 0, i32 2, i32 5, i32 7>
|
||||
%shuf2 = shufflevector <4 x i32> %c, <4 x i32> %b, <4 x i32><i32 0, i32 2, i32 5, i32 7>
|
||||
%xor = xor <4 x i32> %shuf1, %shuf2
|
||||
ret <4 x i32> %xor
|
||||
}
|
||||
|
|
|
|||
Loading…
Reference in New Issue