forked from OSchip/llvm-project
[x86] Allow address-size overrides for SCAS{8,16,32,64} (PR9385)
llvm-svn: 199805
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@ -2361,6 +2361,14 @@ ParseInstruction(ParseInstructionInfo &Info, StringRef Name, SMLoc NameLoc,
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Name == "stosl" || Name == "stosd" || Name == "stosq"))
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Operands.push_back(DefaultMemDIOperand(NameLoc));
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// Transform "scas[bwlq]" into "scas[bwlq] ($DIREG)" for appropriate
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// values of $DIREG according to the mode. It would be nice if this
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// could be achieved with InstAlias in the tables.
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if (Name.startswith("scas") && Operands.size() == 1 &&
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(Name == "scas" || Name == "scasb" || Name == "scasw" ||
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Name == "scasl" || Name == "scasd" || Name == "scasq"))
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Operands.push_back(DefaultMemDIOperand(NameLoc));
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// FIXME: Hack to handle recognize s{hr,ar,hl} $1, <op>. Canonicalize to
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// "shift <op>".
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if ((Name.startswith("shr") || Name.startswith("sar") ||
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@ -1157,11 +1157,14 @@ let Defs = [RCX,RDI], Uses = [RAX,RCX,RDI,EFLAGS] in
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def STOSQ : RI<0xAB, RawFrmDst, (outs dstidx64:$dst), (ins),
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"stosq\t{%rax, $dst|$dst, rax}", [], IIC_STOS>;
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def SCAS8 : I<0xAE, RawFrm, (outs), (ins), "scasb", [], IIC_SCAS>;
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def SCAS16 : I<0xAF, RawFrm, (outs), (ins), "scasw", [], IIC_SCAS>, OpSize;
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def SCAS32 : I<0xAF, RawFrm, (outs), (ins), "scas{l|d}", [], IIC_SCAS>,
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OpSize16;
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def SCAS64 : RI<0xAF, RawFrm, (outs), (ins), "scasq", [], IIC_SCAS>;
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def SCAS8 : I<0xAE, RawFrmDst, (outs), (ins dstidx8:$dst),
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"scasb\t{$dst, %al|al, $dst}", [], IIC_SCAS>;
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def SCAS16 : I<0xAF, RawFrmDst, (outs), (ins dstidx16:$dst),
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"scasw\t{$dst, %ax|ax, $dst}", [], IIC_SCAS>, OpSize;
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def SCAS32 : I<0xAF, RawFrmDst, (outs), (ins dstidx32:$dst),
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"scas{l|d}\t{$dst, %eax|eax, $dst}", [], IIC_SCAS>, OpSize16;
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def SCAS64 : RI<0xAF, RawFrmDst, (outs), (ins dstidx64:$dst),
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"scasq\t{$dst, %rax|rax, $dst}", [], IIC_SCAS>;
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def CMPS8 : I<0xA6, RawFrm, (outs), (ins), "cmpsb", [], IIC_CMPS>;
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def CMPS16 : I<0xA7, RawFrm, (outs), (ins), "cmpsw", [], IIC_CMPS>, OpSize;
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@ -2432,6 +2435,18 @@ def : InstAlias<"stos {%ax, $dst|$dst, ax}", (STOSW dstidx16:$dst), 0>;
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def : InstAlias<"stos {%eax, $dst|$dst, eax}", (STOSL dstidx32:$dst), 0>;
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def : InstAlias<"stos {%rax, $dst|$dst, rax}", (STOSQ dstidx64:$dst), 0>, Requires<[In64BitMode]>;
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// scas aliases. Accept the destination being omitted because it's implicit
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// in the mnemonic, or the mnemonic suffix being omitted because it's implicit
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// in the destination.
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def : InstAlias<"scasb $dst", (SCAS8 dstidx8:$dst), 0>;
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def : InstAlias<"scasw $dst", (SCAS16 dstidx16:$dst), 0>;
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def : InstAlias<"scas{l|d} $dst", (SCAS32 dstidx32:$dst), 0>;
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def : InstAlias<"scasq $dst", (SCAS64 dstidx64:$dst), 0>, Requires<[In64BitMode]>;
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def : InstAlias<"scas {$dst, %al|al, $dst}", (SCAS8 dstidx8:$dst), 0>;
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def : InstAlias<"scas {$dst, %ax|ax, $dst}", (SCAS16 dstidx16:$dst), 0>;
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def : InstAlias<"scas {$dst, %eax|eax, $dst}", (SCAS32 dstidx32:$dst), 0>;
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def : InstAlias<"scas {$dst, %rax|rax, $dst}", (SCAS64 dstidx64:$dst), 0>, Requires<[In64BitMode]>;
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// div and idiv aliases for explicit A register.
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def : InstAlias<"div{b}\t{$src, %al|al, $src}", (DIV8r GR8 :$src)>;
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def : InstAlias<"div{w}\t{$src, %ax|ax, $src}", (DIV16r GR16:$src)>;
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@ -74,3 +74,23 @@ stos %rax, (%edi)
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// 64: stosq %rax, %es:(%edi) # encoding: [0x48,0x67,0xab]
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// ERR32: only available in 64-bit mode
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// ERR16: only available in 64-bit mode
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scas %es:(%edi), %al
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// 64: scasb %es:(%edi), %al # encoding: [0x67,0xae]
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// 32: scasb %es:(%edi), %al # encoding: [0xae]
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// 16: scasb %es:(%edi), %al # encoding: [0x67,0xae]
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scasq %es:(%edi)
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// 64: scasq %es:(%edi), %rax # encoding: [0x48,0x67,0xaf]
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// ERR32: 64-bit
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// ERR16: 64-bit
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scasl %es:(%edi), %al
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// ERR64: invalid operand
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// ERR32: invalid operand
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// ERR16: invalid operand
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scas %es:(%di), %ax
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// ERR64: invalid 16-bit base register
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// 16: scasw %es:(%di), %ax # encoding: [0xaf]
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// 32: scasw %es:(%di), %ax # encoding: [0x66,0x67,0xaf]
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