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[WebAssembly] Refactor atomic operation definitions (NFC) 

Summary:
- Make `ATOMIC_I`, `ATOMIC_NRI`, `AtomicLoad`, `AtomicStore` classes and
  make other operations inherit from them
- Factor the common opcode prefix '0xfe' out from the opcodes into the
  common class
- Reorder instructions in the order of increasing opcodes

Reviewers: tlively

Subscribers: dschuff, sbc100, jgravelle-google, sunfish, jfb, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D58338

llvm-svn: 354421
This commit is contained in:
Heejin Ahn 2019-02-20 01:29:34 +00:00
parent 5fefb02e27
commit 20ea1826f7
1 changed files with 226 additions and 205 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

421
llvm/lib/Target/WebAssembly/WebAssemblyInstrAtomics.td
View File

@ -11,20 +11,156 @@
///
//===----------------------------------------------------------------------===//
multiclass ATOMIC_I<dag oops_r, dag iops_r, dag oops_s, dag iops_s,
list<dag> pattern_r, string asmstr_r = "",
string asmstr_s = "", bits<32> atomic_op = -1> {
defm "" : I<oops_r, iops_r, oops_s, iops_s, pattern_r, asmstr_r, asmstr_s,
!or(0xfe00, !and(0xff, atomic_op))>,
Requires<[HasAtomics]>;
}
multiclass ATOMIC_NRI<dag oops, dag iops, list<dag> pattern, string asmstr = "",
bits<32> atomic_op = -1> {
defm "" : NRI<oops, iops, pattern, asmstr,
!or(0xfe00, !and(0xff, atomic_op))>,
Requires<[HasAtomics]>;
}
//===----------------------------------------------------------------------===//
// Atomic wait / notify
//===----------------------------------------------------------------------===//
let hasSideEffects = 1 in {
defm ATOMIC_NOTIFY :
ATOMIC_I<(outs I32:$dst),
(ins P2Align:$p2align, offset32_op:$off, I32:$addr, I32:$count),
(outs), (ins P2Align:$p2align, offset32_op:$off), [],
"atomic.notify \t$dst, ${off}(${addr})${p2align}, $count",
"atomic.notify \t${off}${p2align}", 0x00>;
let mayLoad = 1 in {
defm ATOMIC_WAIT_I32 :
ATOMIC_I<(outs I32:$dst),
(ins P2Align:$p2align, offset32_op:$off, I32:$addr, I32:$exp,
I64:$timeout),
(outs), (ins P2Align:$p2align, offset32_op:$off), [],
"i32.atomic.wait \t$dst, ${off}(${addr})${p2align}, $exp, $timeout",
"i32.atomic.wait \t${off}${p2align}", 0x01>;
defm ATOMIC_WAIT_I64 :
ATOMIC_I<(outs I32:$dst),
(ins P2Align:$p2align, offset32_op:$off, I32:$addr, I64:$exp,
I64:$timeout),
(outs), (ins P2Align:$p2align, offset32_op:$off), [],
"i64.atomic.wait \t$dst, ${off}(${addr})${p2align}, $exp, $timeout",
"i64.atomic.wait \t${off}${p2align}", 0x02>;
} // mayLoad = 1
} // hasSideEffects = 1
let Predicates = [HasAtomics] in {
// Select notifys with no constant offset.
def NotifyPatNoOffset :
Pat<(i32 (int_wasm_atomic_notify I32:$addr, I32:$count)),
(ATOMIC_NOTIFY 0, 0, I32:$addr, I32:$count)>;
// Select notifys with a constant offset.
// Pattern with address + immediate offset
class NotifyPatImmOff<PatFrag operand> :
Pat<(i32 (int_wasm_atomic_notify (operand I32:$addr, imm:$off), I32:$count)),
(ATOMIC_NOTIFY 0, imm:$off, I32:$addr, I32:$count)>;
def : NotifyPatImmOff<regPlusImm>;
def : NotifyPatImmOff<or_is_add>;
def NotifyPatGlobalAddr :
Pat<(i32 (int_wasm_atomic_notify (regPlusGA I32:$addr,
(WebAssemblywrapper tglobaladdr:$off)),
I32:$count)),
(ATOMIC_NOTIFY 0, tglobaladdr:$off, I32:$addr, I32:$count)>;
def NotifyPatExternalSym :
Pat<(i32 (int_wasm_atomic_notify (add I32:$addr,
(WebAssemblywrapper texternalsym:$off)),
I32:$count)),
(ATOMIC_NOTIFY 0, texternalsym:$off, I32:$addr, I32:$count)>;
// Select notifys with just a constant offset.
def NotifyPatOffsetOnly :
Pat<(i32 (int_wasm_atomic_notify imm:$off, I32:$count)),
(ATOMIC_NOTIFY 0, imm:$off, (CONST_I32 0), I32:$count)>;
def NotifyPatGlobalAddrOffOnly :
Pat<(i32 (int_wasm_atomic_notify (WebAssemblywrapper tglobaladdr:$off),
I32:$count)),
(ATOMIC_NOTIFY 0, tglobaladdr:$off, (CONST_I32 0), I32:$count)>;
def NotifyPatExternSymOffOnly :
Pat<(i32 (int_wasm_atomic_notify (WebAssemblywrapper texternalsym:$off),
I32:$count)),
(ATOMIC_NOTIFY 0, texternalsym:$off, (CONST_I32 0), I32:$count)>;
// Select waits with no constant offset.
class WaitPatNoOffset<ValueType ty, Intrinsic kind, NI inst> :
Pat<(i32 (kind I32:$addr, ty:$exp, I64:$timeout)),
(inst 0, 0, I32:$addr, ty:$exp, I64:$timeout)>;
def : WaitPatNoOffset<i32, int_wasm_atomic_wait_i32, ATOMIC_WAIT_I32>;
def : WaitPatNoOffset<i64, int_wasm_atomic_wait_i64, ATOMIC_WAIT_I64>;
// Select waits with a constant offset.
// Pattern with address + immediate offset
class WaitPatImmOff<ValueType ty, Intrinsic kind, PatFrag operand, NI inst> :
Pat<(i32 (kind (operand I32:$addr, imm:$off), ty:$exp, I64:$timeout)),
(inst 0, imm:$off, I32:$addr, ty:$exp, I64:$timeout)>;
def : WaitPatImmOff<i32, int_wasm_atomic_wait_i32, regPlusImm, ATOMIC_WAIT_I32>;
def : WaitPatImmOff<i32, int_wasm_atomic_wait_i32, or_is_add, ATOMIC_WAIT_I32>;
def : WaitPatImmOff<i64, int_wasm_atomic_wait_i64, regPlusImm, ATOMIC_WAIT_I64>;
def : WaitPatImmOff<i64, int_wasm_atomic_wait_i64, or_is_add, ATOMIC_WAIT_I64>;
class WaitPatGlobalAddr<ValueType ty, Intrinsic kind, NI inst> :
Pat<(i32 (kind (regPlusGA I32:$addr, (WebAssemblywrapper tglobaladdr:$off)),
ty:$exp, I64:$timeout)),
(inst 0, tglobaladdr:$off, I32:$addr, ty:$exp, I64:$timeout)>;
def : WaitPatGlobalAddr<i32, int_wasm_atomic_wait_i32, ATOMIC_WAIT_I32>;
def : WaitPatGlobalAddr<i64, int_wasm_atomic_wait_i64, ATOMIC_WAIT_I64>;
class WaitPatExternalSym<ValueType ty, Intrinsic kind, NI inst> :
Pat<(i32 (kind (add I32:$addr, (WebAssemblywrapper texternalsym:$off)),
ty:$exp, I64:$timeout)),
(inst 0, texternalsym:$off, I32:$addr, ty:$exp, I64:$timeout)>;
def : WaitPatExternalSym<i32, int_wasm_atomic_wait_i32, ATOMIC_WAIT_I32>;
def : WaitPatExternalSym<i64, int_wasm_atomic_wait_i64, ATOMIC_WAIT_I64>;
// Select wait_i32, ATOMIC_WAIT_I32s with just a constant offset.
class WaitPatOffsetOnly<ValueType ty, Intrinsic kind, NI inst> :
Pat<(i32 (kind imm:$off, ty:$exp, I64:$timeout)),
(inst 0, imm:$off, (CONST_I32 0), ty:$exp, I64:$timeout)>;
def : WaitPatOffsetOnly<i32, int_wasm_atomic_wait_i32, ATOMIC_WAIT_I32>;
def : WaitPatOffsetOnly<i64, int_wasm_atomic_wait_i64, ATOMIC_WAIT_I64>;
class WaitPatGlobalAddrOffOnly<ValueType ty, Intrinsic kind, NI inst> :
Pat<(i32 (kind (WebAssemblywrapper tglobaladdr:$off), ty:$exp, I64:$timeout)),
(inst 0, tglobaladdr:$off, (CONST_I32 0), ty:$exp, I64:$timeout)>;
def : WaitPatGlobalAddrOffOnly<i32, int_wasm_atomic_wait_i32, ATOMIC_WAIT_I32>;
def : WaitPatGlobalAddrOffOnly<i64, int_wasm_atomic_wait_i64, ATOMIC_WAIT_I64>;
class WaitPatExternSymOffOnly<ValueType ty, Intrinsic kind, NI inst> :
Pat<(i32 (kind (WebAssemblywrapper texternalsym:$off), ty:$exp,
I64:$timeout)),
(inst 0, texternalsym:$off, (CONST_I32 0), ty:$exp, I64:$timeout)>;
def : WaitPatExternSymOffOnly<i32, int_wasm_atomic_wait_i32, ATOMIC_WAIT_I32>;
def : WaitPatExternSymOffOnly<i64, int_wasm_atomic_wait_i64, ATOMIC_WAIT_I64>;
} // Predicates = [HasAtomics]
//===----------------------------------------------------------------------===//
// Atomic loads
//===----------------------------------------------------------------------===//
multiclass ATOMIC_I<dag oops_r, dag iops_r, dag oops_s, dag iops_s,
list<dag> pattern_r, string asmstr_r = "",
string asmstr_s = "", bits<32> inst = -1> {
defm "" : I<oops_r, iops_r, oops_s, iops_s, pattern_r, asmstr_r, asmstr_s,
inst>,
multiclass AtomicLoad<WebAssemblyRegClass rc, string name, int atomic_op> {
defm "" : WebAssemblyLoad<rc, name, !or(0xfe00, !and(0xff, atomic_op))>,
Requires<[HasAtomics]>;
}
defm ATOMIC_LOAD_I32 : WebAssemblyLoad<I32, "i32.atomic.load", 0xfe10>;
defm ATOMIC_LOAD_I64 : WebAssemblyLoad<I64, "i64.atomic.load", 0xfe11>;
defm ATOMIC_LOAD_I32 : AtomicLoad<I32, "i32.atomic.load", 0x10>;
defm ATOMIC_LOAD_I64 : AtomicLoad<I64, "i64.atomic.load", 0x11>;
// Select loads with no constant offset.
let Predicates = [HasAtomics] in {
@ -59,11 +195,11 @@ def : LoadPatExternSymOffOnly<i64, atomic_load_64, ATOMIC_LOAD_I64>;
// Extending loads. Note that there are only zero-extending atomic loads, no
// sign-extending loads.
defm ATOMIC_LOAD8_U_I32 : WebAssemblyLoad<I32, "i32.atomic.load8_u", 0xfe12>;
defm ATOMIC_LOAD16_U_I32 : WebAssemblyLoad<I32, "i32.atomic.load16_u", 0xfe13>;
defm ATOMIC_LOAD8_U_I64 : WebAssemblyLoad<I64, "i64.atomic.load8_u", 0xfe14>;
defm ATOMIC_LOAD16_U_I64 : WebAssemblyLoad<I64, "i64.atomic.load16_u", 0xfe15>;
defm ATOMIC_LOAD32_U_I64 : WebAssemblyLoad<I64, "i64.atomic.load32_u", 0xfe16>;
defm ATOMIC_LOAD8_U_I32 : AtomicLoad<I32, "i32.atomic.load8_u", 0x12>;
defm ATOMIC_LOAD16_U_I32 : AtomicLoad<I32, "i32.atomic.load16_u", 0x13>;
defm ATOMIC_LOAD8_U_I64 : AtomicLoad<I64, "i64.atomic.load8_u", 0x14>;
defm ATOMIC_LOAD16_U_I64 : AtomicLoad<I64, "i64.atomic.load16_u", 0x15>;
defm ATOMIC_LOAD32_U_I64 : AtomicLoad<I64, "i64.atomic.load32_u", 0x16>;
// Fragments for extending loads. These are different from regular loads because
// the SDNodes are derived from AtomicSDNode rather than LoadSDNode and
@ -195,8 +331,13 @@ def : LoadPatExternSymOffOnly<i64, sext_aload_16_64, ATOMIC_LOAD16_U_I64>;
// Atomic stores
//===----------------------------------------------------------------------===//
defm ATOMIC_STORE_I32 : WebAssemblyStore<I32, "i32.atomic.store", 0xfe17>;
defm ATOMIC_STORE_I64 : WebAssemblyStore<I64, "i64.atomic.store", 0xfe18>;
multiclass AtomicStore<WebAssemblyRegClass rc, string name, int atomic_op> {
defm "" : WebAssemblyStore<rc, name, !or(0xfe00, !and(0xff, atomic_op))>,
Requires<[HasAtomics]>;
}
defm ATOMIC_STORE_I32 : AtomicStore<I32, "i32.atomic.store", 0x17>;
defm ATOMIC_STORE_I64 : AtomicStore<I64, "i64.atomic.store", 0x18>;
// We need an 'atomic' version of store patterns because store and atomic_store
// nodes have different operand orders:
@ -256,11 +397,11 @@ def : AStorePatExternSymOffOnly<i64, atomic_store_64, ATOMIC_STORE_I64>;
} // Predicates = [HasAtomics]
// Truncating stores.
defm ATOMIC_STORE8_I32 : WebAssemblyStore<I32, "i32.atomic.store8", 0xfe19>;
defm ATOMIC_STORE16_I32 : WebAssemblyStore<I32, "i32.atomic.store16", 0xfe1a>;
defm ATOMIC_STORE8_I64 : WebAssemblyStore<I64, "i64.atomic.store8", 0xfe1b>;
defm ATOMIC_STORE16_I64 : WebAssemblyStore<I64, "i64.atomic.store16", 0xfe1c>;
defm ATOMIC_STORE32_I64 : WebAssemblyStore<I64, "i64.atomic.store32", 0xfe1d>;
defm ATOMIC_STORE8_I32 : AtomicStore<I32, "i32.atomic.store8", 0x19>;
defm ATOMIC_STORE16_I32 : AtomicStore<I32, "i32.atomic.store16", 0x1a>;
defm ATOMIC_STORE8_I64 : AtomicStore<I64, "i64.atomic.store8", 0x1b>;
defm ATOMIC_STORE16_I64 : AtomicStore<I64, "i64.atomic.store16", 0x1c>;
defm ATOMIC_STORE32_I64 : AtomicStore<I64, "i64.atomic.store32", 0x1d>;
// Fragments for truncating stores.
@ -332,93 +473,95 @@ def : AStorePatExternSymOffOnly<i64, trunc_astore_32_64, ATOMIC_STORE32_I64>;
// Atomic binary read-modify-writes
//===----------------------------------------------------------------------===//
multiclass WebAssemblyBinRMW<WebAssemblyRegClass rc, string Name, int Opcode> {
defm "" : I<(outs rc:$dst),
multiclass WebAssemblyBinRMW<WebAssemblyRegClass rc, string name,
int atomic_op> {
defm "" :
ATOMIC_I<(outs rc:$dst),
(ins P2Align:$p2align, offset32_op:$off, I32:$addr, rc:$val),
(outs), (ins P2Align:$p2align, offset32_op:$off), [],
!strconcat(Name, "\t$dst, ${off}(${addr})${p2align}, $val"),
!strconcat(Name, "\t${off}${p2align}"), Opcode>;
!strconcat(name, "\t$dst, ${off}(${addr})${p2align}, $val"),
!strconcat(name, "\t${off}${p2align}"), atomic_op>;
}
defm ATOMIC_RMW_ADD_I32 : WebAssemblyBinRMW<I32, "i32.atomic.rmw.add", 0xfe1e>;
defm ATOMIC_RMW_ADD_I64 : WebAssemblyBinRMW<I64, "i64.atomic.rmw.add", 0xfe1f>;
defm ATOMIC_RMW_ADD_I32 : WebAssemblyBinRMW<I32, "i32.atomic.rmw.add", 0x1e>;
defm ATOMIC_RMW_ADD_I64 : WebAssemblyBinRMW<I64, "i64.atomic.rmw.add", 0x1f>;
defm ATOMIC_RMW8_U_ADD_I32 :
WebAssemblyBinRMW<I32, "i32.atomic.rmw8.add_u", 0xfe20>;
WebAssemblyBinRMW<I32, "i32.atomic.rmw8.add_u", 0x20>;
defm ATOMIC_RMW16_U_ADD_I32 :
WebAssemblyBinRMW<I32, "i32.atomic.rmw16.add_u", 0xfe21>;
WebAssemblyBinRMW<I32, "i32.atomic.rmw16.add_u", 0x21>;
defm ATOMIC_RMW8_U_ADD_I64 :
WebAssemblyBinRMW<I64, "i64.atomic.rmw8.add_u", 0xfe22>;
WebAssemblyBinRMW<I64, "i64.atomic.rmw8.add_u", 0x22>;
defm ATOMIC_RMW16_U_ADD_I64 :
WebAssemblyBinRMW<I64, "i64.atomic.rmw16.add_u", 0xfe23>;
WebAssemblyBinRMW<I64, "i64.atomic.rmw16.add_u", 0x23>;
defm ATOMIC_RMW32_U_ADD_I64 :
WebAssemblyBinRMW<I64, "i64.atomic.rmw32.add_u", 0xfe24>;
WebAssemblyBinRMW<I64, "i64.atomic.rmw32.add_u", 0x24>;
defm ATOMIC_RMW_SUB_I32 : WebAssemblyBinRMW<I32, "i32.atomic.rmw.sub", 0xfe25>;
defm ATOMIC_RMW_SUB_I64 : WebAssemblyBinRMW<I64, "i64.atomic.rmw.sub", 0xfe26>;
defm ATOMIC_RMW_SUB_I32 : WebAssemblyBinRMW<I32, "i32.atomic.rmw.sub", 0x25>;
defm ATOMIC_RMW_SUB_I64 : WebAssemblyBinRMW<I64, "i64.atomic.rmw.sub", 0x26>;
defm ATOMIC_RMW8_U_SUB_I32 :
WebAssemblyBinRMW<I32, "i32.atomic.rmw8.sub_u", 0xfe27>;
WebAssemblyBinRMW<I32, "i32.atomic.rmw8.sub_u", 0x27>;
defm ATOMIC_RMW16_U_SUB_I32 :
WebAssemblyBinRMW<I32, "i32.atomic.rmw16.sub_u", 0xfe28>;
WebAssemblyBinRMW<I32, "i32.atomic.rmw16.sub_u", 0x28>;
defm ATOMIC_RMW8_U_SUB_I64 :
WebAssemblyBinRMW<I64, "i64.atomic.rmw8.sub_u", 0xfe29>;
WebAssemblyBinRMW<I64, "i64.atomic.rmw8.sub_u", 0x29>;
defm ATOMIC_RMW16_U_SUB_I64 :
WebAssemblyBinRMW<I64, "i64.atomic.rmw16.sub_u", 0xfe2a>;
WebAssemblyBinRMW<I64, "i64.atomic.rmw16.sub_u", 0x2a>;
defm ATOMIC_RMW32_U_SUB_I64 :
WebAssemblyBinRMW<I64, "i64.atomic.rmw32.sub_u", 0xfe2b>;
WebAssemblyBinRMW<I64, "i64.atomic.rmw32.sub_u", 0x2b>;
defm ATOMIC_RMW_AND_I32 : WebAssemblyBinRMW<I32, "i32.atomic.rmw.and", 0xfe2c>;
defm ATOMIC_RMW_AND_I64 : WebAssemblyBinRMW<I64, "i64.atomic.rmw.and", 0xfe2d>;
defm ATOMIC_RMW_AND_I32 : WebAssemblyBinRMW<I32, "i32.atomic.rmw.and", 0x2c>;
defm ATOMIC_RMW_AND_I64 : WebAssemblyBinRMW<I64, "i64.atomic.rmw.and", 0x2d>;
defm ATOMIC_RMW8_U_AND_I32 :
WebAssemblyBinRMW<I32, "i32.atomic.rmw8.and_u", 0xfe2e>;
WebAssemblyBinRMW<I32, "i32.atomic.rmw8.and_u", 0x2e>;
defm ATOMIC_RMW16_U_AND_I32 :
WebAssemblyBinRMW<I32, "i32.atomic.rmw16.and_u", 0xfe2f>;
WebAssemblyBinRMW<I32, "i32.atomic.rmw16.and_u", 0x2f>;
defm ATOMIC_RMW8_U_AND_I64 :
WebAssemblyBinRMW<I64, "i64.atomic.rmw8.and_u", 0xfe30>;
WebAssemblyBinRMW<I64, "i64.atomic.rmw8.and_u", 0x30>;
defm ATOMIC_RMW16_U_AND_I64 :
WebAssemblyBinRMW<I64, "i64.atomic.rmw16.and_u", 0xfe31>;
WebAssemblyBinRMW<I64, "i64.atomic.rmw16.and_u", 0x31>;
defm ATOMIC_RMW32_U_AND_I64 :
WebAssemblyBinRMW<I64, "i64.atomic.rmw32.and_u", 0xfe32>;
WebAssemblyBinRMW<I64, "i64.atomic.rmw32.and_u", 0x32>;
defm ATOMIC_RMW_OR_I32 : WebAssemblyBinRMW<I32, "i32.atomic.rmw.or", 0xfe33>;
defm ATOMIC_RMW_OR_I64 : WebAssemblyBinRMW<I64, "i64.atomic.rmw.or", 0xfe34>;
defm ATOMIC_RMW_OR_I32 : WebAssemblyBinRMW<I32, "i32.atomic.rmw.or", 0x33>;
defm ATOMIC_RMW_OR_I64 : WebAssemblyBinRMW<I64, "i64.atomic.rmw.or", 0x34>;
defm ATOMIC_RMW8_U_OR_I32 :
WebAssemblyBinRMW<I32, "i32.atomic.rmw8.or_u", 0xfe35>;
WebAssemblyBinRMW<I32, "i32.atomic.rmw8.or_u", 0x35>;
defm ATOMIC_RMW16_U_OR_I32 :
WebAssemblyBinRMW<I32, "i32.atomic.rmw16.or_u", 0xfe36>;
WebAssemblyBinRMW<I32, "i32.atomic.rmw16.or_u", 0x36>;
defm ATOMIC_RMW8_U_OR_I64 :
WebAssemblyBinRMW<I64, "i64.atomic.rmw8.or_u", 0xfe37>;
WebAssemblyBinRMW<I64, "i64.atomic.rmw8.or_u", 0x37>;
defm ATOMIC_RMW16_U_OR_I64 :
WebAssemblyBinRMW<I64, "i64.atomic.rmw16.or_u", 0xfe38>;
WebAssemblyBinRMW<I64, "i64.atomic.rmw16.or_u", 0x38>;
defm ATOMIC_RMW32_U_OR_I64 :
WebAssemblyBinRMW<I64, "i64.atomic.rmw32.or_u", 0xfe39>;
WebAssemblyBinRMW<I64, "i64.atomic.rmw32.or_u", 0x39>;
defm ATOMIC_RMW_XOR_I32 : WebAssemblyBinRMW<I32, "i32.atomic.rmw.xor", 0xfe3a>;
defm ATOMIC_RMW_XOR_I64 : WebAssemblyBinRMW<I64, "i64.atomic.rmw.xor", 0xfe3b>;
defm ATOMIC_RMW_XOR_I32 : WebAssemblyBinRMW<I32, "i32.atomic.rmw.xor", 0x3a>;
defm ATOMIC_RMW_XOR_I64 : WebAssemblyBinRMW<I64, "i64.atomic.rmw.xor", 0x3b>;
defm ATOMIC_RMW8_U_XOR_I32 :
WebAssemblyBinRMW<I32, "i32.atomic.rmw8.xor_u", 0xfe3c>;
WebAssemblyBinRMW<I32, "i32.atomic.rmw8.xor_u", 0x3c>;
defm ATOMIC_RMW16_U_XOR_I32 :
WebAssemblyBinRMW<I32, "i32.atomic.rmw16.xor_u", 0xfe3d>;
WebAssemblyBinRMW<I32, "i32.atomic.rmw16.xor_u", 0x3d>;
defm ATOMIC_RMW8_U_XOR_I64 :
WebAssemblyBinRMW<I64, "i64.atomic.rmw8.xor_u", 0xfe3e>;
WebAssemblyBinRMW<I64, "i64.atomic.rmw8.xor_u", 0x3e>;
defm ATOMIC_RMW16_U_XOR_I64 :
WebAssemblyBinRMW<I64, "i64.atomic.rmw16.xor_u", 0xfe3f>;
WebAssemblyBinRMW<I64, "i64.atomic.rmw16.xor_u", 0x3f>;
defm ATOMIC_RMW32_U_XOR_I64 :
WebAssemblyBinRMW<I64, "i64.atomic.rmw32.xor_u", 0xfe40>;
WebAssemblyBinRMW<I64, "i64.atomic.rmw32.xor_u", 0x40>;
defm ATOMIC_RMW_XCHG_I32 :
WebAssemblyBinRMW<I32, "i32.atomic.rmw.xchg", 0xfe41>;
WebAssemblyBinRMW<I32, "i32.atomic.rmw.xchg", 0x41>;
defm ATOMIC_RMW_XCHG_I64 :
WebAssemblyBinRMW<I64, "i64.atomic.rmw.xchg", 0xfe42>;
WebAssemblyBinRMW<I64, "i64.atomic.rmw.xchg", 0x42>;
defm ATOMIC_RMW8_U_XCHG_I32 :
WebAssemblyBinRMW<I32, "i32.atomic.rmw8.xchg_u", 0xfe43>;
WebAssemblyBinRMW<I32, "i32.atomic.rmw8.xchg_u", 0x43>;
defm ATOMIC_RMW16_U_XCHG_I32 :
WebAssemblyBinRMW<I32, "i32.atomic.rmw16.xchg_u", 0xfe44>;
WebAssemblyBinRMW<I32, "i32.atomic.rmw16.xchg_u", 0x44>;
defm ATOMIC_RMW8_U_XCHG_I64 :
WebAssemblyBinRMW<I64, "i64.atomic.rmw8.xchg_u", 0xfe45>;
WebAssemblyBinRMW<I64, "i64.atomic.rmw8.xchg_u", 0x45>;
defm ATOMIC_RMW16_U_XCHG_I64 :
WebAssemblyBinRMW<I64, "i64.atomic.rmw16.xchg_u", 0xfe46>;
WebAssemblyBinRMW<I64, "i64.atomic.rmw16.xchg_u", 0x46>;
defm ATOMIC_RMW32_U_XCHG_I64 :
WebAssemblyBinRMW<I64, "i64.atomic.rmw32.xchg_u", 0xfe47>;
WebAssemblyBinRMW<I64, "i64.atomic.rmw32.xchg_u", 0x47>;
// Select binary RMWs with no constant offset.
class BinRMWPatNoOffset<ValueType ty, PatFrag kind, NI inst> :
@ -662,29 +805,31 @@ defm : BinRMWTruncExtPattern<
// Consider adding a pass after instruction selection that optimizes this case
// if it is frequent.
multiclass WebAssemblyTerRMW<WebAssemblyRegClass rc, string Name, int Opcode> {
defm "" : I<(outs rc:$dst),
multiclass WebAssemblyTerRMW<WebAssemblyRegClass rc, string name,
int atomic_op> {
defm "" :
ATOMIC_I<(outs rc:$dst),
(ins P2Align:$p2align, offset32_op:$off, I32:$addr, rc:$exp,
rc:$new),
(outs), (ins P2Align:$p2align, offset32_op:$off), [],
!strconcat(Name, "\t$dst, ${off}(${addr})${p2align}, $exp, $new"),
!strconcat(Name, "\t${off}${p2align}"), Opcode>;
!strconcat(name, "\t$dst, ${off}(${addr})${p2align}, $exp, $new"),
!strconcat(name, "\t${off}${p2align}"), atomic_op>;
}
defm ATOMIC_RMW_CMPXCHG_I32 :
WebAssemblyTerRMW<I32, "i32.atomic.rmw.cmpxchg", 0xfe48>;
WebAssemblyTerRMW<I32, "i32.atomic.rmw.cmpxchg", 0x48>;
defm ATOMIC_RMW_CMPXCHG_I64 :
WebAssemblyTerRMW<I64, "i64.atomic.rmw.cmpxchg", 0xfe49>;
WebAssemblyTerRMW<I64, "i64.atomic.rmw.cmpxchg", 0x49>;
defm ATOMIC_RMW8_U_CMPXCHG_I32 :
WebAssemblyTerRMW<I32, "i32.atomic.rmw8.cmpxchg_u", 0xfe4a>;
WebAssemblyTerRMW<I32, "i32.atomic.rmw8.cmpxchg_u", 0x4a>;
defm ATOMIC_RMW16_U_CMPXCHG_I32 :
WebAssemblyTerRMW<I32, "i32.atomic.rmw16.cmpxchg_u", 0xfe4b>;
WebAssemblyTerRMW<I32, "i32.atomic.rmw16.cmpxchg_u", 0x4b>;
defm ATOMIC_RMW8_U_CMPXCHG_I64 :
WebAssemblyTerRMW<I64, "i64.atomic.rmw8.cmpxchg_u", 0xfe4c>;
WebAssemblyTerRMW<I64, "i64.atomic.rmw8.cmpxchg_u", 0x4c>;
defm ATOMIC_RMW16_U_CMPXCHG_I64 :
WebAssemblyTerRMW<I64, "i64.atomic.rmw16.cmpxchg_u", 0xfe4d>;
WebAssemblyTerRMW<I64, "i64.atomic.rmw16.cmpxchg_u", 0x4d>;
defm ATOMIC_RMW32_U_CMPXCHG_I64 :
WebAssemblyTerRMW<I64, "i64.atomic.rmw32.cmpxchg_u", 0xfe4e>;
WebAssemblyTerRMW<I64, "i64.atomic.rmw32.cmpxchg_u", 0x4e>;
// Select ternary RMWs with no constant offset.
class TerRMWPatNoOffset<ValueType ty, PatFrag kind, NI inst> :
@ -890,127 +1035,3 @@ defm : TerRMWTruncExtPattern<
ATOMIC_RMW8_U_CMPXCHG_I32, ATOMIC_RMW16_U_CMPXCHG_I32,
ATOMIC_RMW8_U_CMPXCHG_I64, ATOMIC_RMW16_U_CMPXCHG_I64,
ATOMIC_RMW32_U_CMPXCHG_I64>;
//===----------------------------------------------------------------------===//
// Atomic wait / notify
//===----------------------------------------------------------------------===//
let hasSideEffects = 1 in {
defm ATOMIC_NOTIFY :
I<(outs I32:$dst),
(ins P2Align:$p2align, offset32_op:$off, I32:$addr, I32:$count),
(outs), (ins P2Align:$p2align, offset32_op:$off), [],
"atomic.notify \t$dst, ${off}(${addr})${p2align}, $count",
"atomic.notify \t${off}${p2align}", 0xfe00>;
let mayLoad = 1 in {
defm ATOMIC_WAIT_I32 :
I<(outs I32:$dst),
(ins P2Align:$p2align, offset32_op:$off, I32:$addr, I32:$exp, I64:$timeout),
(outs), (ins P2Align:$p2align, offset32_op:$off), [],
"i32.atomic.wait \t$dst, ${off}(${addr})${p2align}, $exp, $timeout",
"i32.atomic.wait \t${off}${p2align}", 0xfe01>;
defm ATOMIC_WAIT_I64 :
I<(outs I32:$dst),
(ins P2Align:$p2align, offset32_op:$off, I32:$addr, I64:$exp, I64:$timeout),
(outs), (ins P2Align:$p2align, offset32_op:$off), [],
"i64.atomic.wait \t$dst, ${off}(${addr})${p2align}, $exp, $timeout",
"i64.atomic.wait \t${off}${p2align}", 0xfe02>;
} // mayLoad = 1
} // hasSideEffects = 1
let Predicates = [HasAtomics] in {
// Select notifys with no constant offset.
class NotifyPatNoOffset<Intrinsic kind> :
Pat<(i32 (kind I32:$addr, I32:$count)),
(ATOMIC_NOTIFY 0, 0, I32:$addr, I32:$count)>;
def : NotifyPatNoOffset<int_wasm_atomic_notify>;
// Select notifys with a constant offset.
// Pattern with address + immediate offset
class NotifyPatImmOff<Intrinsic kind, PatFrag operand> :
Pat<(i32 (kind (operand I32:$addr, imm:$off), I32:$count)),
(ATOMIC_NOTIFY 0, imm:$off, I32:$addr, I32:$count)>;
def : NotifyPatImmOff<int_wasm_atomic_notify, regPlusImm>;
def : NotifyPatImmOff<int_wasm_atomic_notify, or_is_add>;
class NotifyPatGlobalAddr<Intrinsic kind> :
Pat<(i32 (kind (regPlusGA I32:$addr, (WebAssemblywrapper tglobaladdr:$off)),
I32:$count)),
(ATOMIC_NOTIFY 0, tglobaladdr:$off, I32:$addr, I32:$count)>;
def : NotifyPatGlobalAddr<int_wasm_atomic_notify>;
class NotifyPatExternalSym<Intrinsic kind> :
Pat<(i32 (kind (add I32:$addr, (WebAssemblywrapper texternalsym:$off)),
I32:$count)),
(ATOMIC_NOTIFY 0, texternalsym:$off, I32:$addr, I32:$count)>;
def : NotifyPatExternalSym<int_wasm_atomic_notify>;
// Select notifys with just a constant offset.
class NotifyPatOffsetOnly<Intrinsic kind> :
Pat<(i32 (kind imm:$off, I32:$count)),
(ATOMIC_NOTIFY 0, imm:$off, (CONST_I32 0), I32:$count)>;
def : NotifyPatOffsetOnly<int_wasm_atomic_notify>;
class NotifyPatGlobalAddrOffOnly<Intrinsic kind> :
Pat<(i32 (kind (WebAssemblywrapper tglobaladdr:$off), I32:$count)),
(ATOMIC_NOTIFY 0, tglobaladdr:$off, (CONST_I32 0), I32:$count)>;
def : NotifyPatGlobalAddrOffOnly<int_wasm_atomic_notify>;
class NotifyPatExternSymOffOnly<Intrinsic kind> :
Pat<(i32 (kind (WebAssemblywrapper texternalsym:$off), I32:$count)),
(ATOMIC_NOTIFY 0, texternalsym:$off, (CONST_I32 0), I32:$count)>;
def : NotifyPatExternSymOffOnly<int_wasm_atomic_notify>;
// Select waits with no constant offset.
class WaitPatNoOffset<ValueType ty, Intrinsic kind, NI inst> :
Pat<(i32 (kind I32:$addr, ty:$exp, I64:$timeout)),
(inst 0, 0, I32:$addr, ty:$exp, I64:$timeout)>;
def : WaitPatNoOffset<i32, int_wasm_atomic_wait_i32, ATOMIC_WAIT_I32>;
def : WaitPatNoOffset<i64, int_wasm_atomic_wait_i64, ATOMIC_WAIT_I64>;
// Select waits with a constant offset.
// Pattern with address + immediate offset
class WaitPatImmOff<ValueType ty, Intrinsic kind, PatFrag operand, NI inst> :
Pat<(i32 (kind (operand I32:$addr, imm:$off), ty:$exp, I64:$timeout)),
(inst 0, imm:$off, I32:$addr, ty:$exp, I64:$timeout)>;
def : WaitPatImmOff<i32, int_wasm_atomic_wait_i32, regPlusImm, ATOMIC_WAIT_I32>;
def : WaitPatImmOff<i32, int_wasm_atomic_wait_i32, or_is_add, ATOMIC_WAIT_I32>;
def : WaitPatImmOff<i64, int_wasm_atomic_wait_i64, regPlusImm, ATOMIC_WAIT_I64>;
def : WaitPatImmOff<i64, int_wasm_atomic_wait_i64, or_is_add, ATOMIC_WAIT_I64>;
class WaitPatGlobalAddr<ValueType ty, Intrinsic kind, NI inst> :
Pat<(i32 (kind (regPlusGA I32:$addr, (WebAssemblywrapper tglobaladdr:$off)),
ty:$exp, I64:$timeout)),
(inst 0, tglobaladdr:$off, I32:$addr, ty:$exp, I64:$timeout)>;
def : WaitPatGlobalAddr<i32, int_wasm_atomic_wait_i32, ATOMIC_WAIT_I32>;
def : WaitPatGlobalAddr<i64, int_wasm_atomic_wait_i64, ATOMIC_WAIT_I64>;
class WaitPatExternalSym<ValueType ty, Intrinsic kind, NI inst> :
Pat<(i32 (kind (add I32:$addr, (WebAssemblywrapper texternalsym:$off)),
ty:$exp, I64:$timeout)),
(inst 0, texternalsym:$off, I32:$addr, ty:$exp, I64:$timeout)>;
def : WaitPatExternalSym<i32, int_wasm_atomic_wait_i32, ATOMIC_WAIT_I32>;
def : WaitPatExternalSym<i64, int_wasm_atomic_wait_i64, ATOMIC_WAIT_I64>;
// Select wait_i32, ATOMIC_WAIT_I32s with just a constant offset.
class WaitPatOffsetOnly<ValueType ty, Intrinsic kind, NI inst> :
Pat<(i32 (kind imm:$off, ty:$exp, I64:$timeout)),
(inst 0, imm:$off, (CONST_I32 0), ty:$exp, I64:$timeout)>;
def : WaitPatOffsetOnly<i32, int_wasm_atomic_wait_i32, ATOMIC_WAIT_I32>;
def : WaitPatOffsetOnly<i64, int_wasm_atomic_wait_i64, ATOMIC_WAIT_I64>;
class WaitPatGlobalAddrOffOnly<ValueType ty, Intrinsic kind, NI inst> :
Pat<(i32 (kind (WebAssemblywrapper tglobaladdr:$off), ty:$exp, I64:$timeout)),
(inst 0, tglobaladdr:$off, (CONST_I32 0), ty:$exp, I64:$timeout)>;
def : WaitPatGlobalAddrOffOnly<i32, int_wasm_atomic_wait_i32, ATOMIC_WAIT_I32>;
def : WaitPatGlobalAddrOffOnly<i64, int_wasm_atomic_wait_i64, ATOMIC_WAIT_I64>;
class WaitPatExternSymOffOnly<ValueType ty, Intrinsic kind, NI inst> :
Pat<(i32 (kind (WebAssemblywrapper texternalsym:$off), ty:$exp,
I64:$timeout)),
(inst 0, texternalsym:$off, (CONST_I32 0), ty:$exp, I64:$timeout)>;
def : WaitPatExternSymOffOnly<i32, int_wasm_atomic_wait_i32, ATOMIC_WAIT_I32>;
def : WaitPatExternSymOffOnly<i64, int_wasm_atomic_wait_i64, ATOMIC_WAIT_I64>;
} // Predicates = [HasAtomics]