MIR: Allow parsing of empty machine functions

If you run llc -stop-after=codegenprepare and feed the resulting MIR
to llc -start-after=codegenprepare, you'll have an empty machine
function since we haven't run any isel yet. Of course, this only works
if the MIRParser believes you that this is okay.

This is essentially a revert of r241862 with a fix for the problem it
was papering over.

llvm-svn: 299975

llvm/lib/CodeGen/MIRParser/MIRParser.cpp

@@ -367,9 +367,6 @@ bool MIRParserImpl::initializeMachineFunction(MachineFunction &MF) {
   }
   PFS.SM = &SM;
 
-  if (MF.empty())
-    return error(Twine("machine function '") + Twine(MF.getName()) +
-                 "' requires at least one machine basic block in its body");
   // Initialize the frame information after creating all the MBBs so that the
   // MBB references in the frame information can be resolved.
   if (initializeFrameInfo(PFS, YamlMF))

llvm/lib/CodeGen/MachineVerifier.cpp

@@ -528,7 +528,8 @@ void MachineVerifier::visitMachineFunctionBefore() {
   lastIndex = SlotIndex();
   regsReserved = MRI->getReservedRegs();
 
-  markReachable(&MF->front());
+  if (!MF->empty())
+    markReachable(&MF->front());
 
   // Build a set of the basic blocks in the function.
   FunctionBlocks.clear();
@@ -548,7 +549,8 @@ void MachineVerifier::visitMachineFunctionBefore() {
   // Check that the register use lists are sane.
   MRI->verifyUseLists();
 
-  verifyStackFrame();
+  if (!MF->empty())
+    verifyStackFrame();
 }
 
 // Does iterator point to a and b as the first two elements?

llvm/test/CodeGen/MIR/Generic/llvmIR.mir

@@ -28,10 +28,8 @@
   IfUnequal:
     ret i32 0
   }
-  
+
 ...
 ---
 name: foo
-body: |
-  bb.0:
 ...

llvm/test/CodeGen/MIR/Generic/llvmIRMissing.mir

@@ -4,6 +4,4 @@
 ---
 # CHECK: name: foo
 name: foo
-body: |
-  bb.0:
 ...

llvm/test/CodeGen/MIR/Generic/machine-function-missing-body-error.mir

@@ -1,15 +0,0 @@
-# RUN: not llc -run-pass none -o /dev/null %s 2>&1 | FileCheck %s
-# This test ensures that the MIR parser reports an error when it encounters a
-# machine function with an empty body.
-
---- |
-
-  define i32 @foo() {
-    ret i32 0
-  }
-
-...
----
-# CHECK: machine function 'foo' requires at least one machine basic block in its body
-name:            foo
-...

llvm/test/CodeGen/MIR/Generic/machine-function-missing-body.mir

@@ -0,0 +1,15 @@
+# RUN: llc -run-pass none -o - %s | FileCheck %s
+# This test ensures that the MIR parser accepts files with llvm IR but
+# no machine function body.
+
+--- |
+  ; CHECK: define i32 @foo()
+  define i32 @foo() {
+    ret i32 0
+  }
+
+...
+---
+# CHECK: name: foo
+name:            foo
+...

llvm/test/CodeGen/MIR/Generic/machine-function-missing-function.mir

@@ -12,12 +12,8 @@
 ...
 ---
 name:            foo
-body: |
-  bb.0:
 ...
 ---
 # CHECK: function 'faa' isn't defined in the provided LLVM IR
 name:            faa
-body: |
-  bb.0:
 ...

llvm/test/CodeGen/MIR/Generic/machine-function-missing-name.mir

@@ -16,11 +16,7 @@
 ---
 # CHECK: [[@LINE+1]]:1: missing required key 'name'
 nme:             foo
-body: |
-  bb.0:
 ...
 ---
 name:            bar
-body: |
-  bb.0:
 ...

llvm/test/CodeGen/MIR/Generic/machine-function.mir

@@ -18,7 +18,7 @@
   define i32 @func2() {
     ret i32 0
   }
-  
+
 ...
 ---
 # CHECK: name: foo
@@ -26,8 +26,6 @@
 # CHECK-NEXT: exposesReturnsTwice: false
 # CHECK: ...
 name:            foo
-body: |
-  bb.0:
 ...
 ---
 # CHECK: name: bar
@@ -35,8 +33,6 @@ body: |
 # CHECK-NEXT: exposesReturnsTwice: false
 # CHECK: ...
 name:            bar
-body: |
-  bb.0:
 ...
 ---
 # CHECK: name: func
@@ -45,8 +41,6 @@ body: |
 # CHECK: ...
 name:            func
 alignment:       8
-body: |
-  bb.0:
 ...
 ---
 # CHECK: name: func2
@@ -56,6 +50,4 @@ body: |
 name:            func2
 alignment:       16
 exposesReturnsTwice: true
-body: |
-  bb.0:
 ...

llvm/test/CodeGen/MIR/Generic/register-info.mir

@@ -20,8 +20,6 @@
 # CHECK: tracksRegLiveness: false
 # CHECK: ...
 name:            foo
-body: |
-  bb.0:
 ...
 ---
 # CHECK: name: bar
@@ -29,6 +27,4 @@ body: |
 # CHECK: ...
 name: bar
 tracksRegLiveness: true
-body: |
-  bb.0:
 ...