forked from OSchip/llvm-project
[RISCV] Custom lower SHL_PARTS, SRA_PARTS, SRL_PARTS
When not optimizing for minimum size (-Oz) we custom lower wide shifts (SHL_PARTS, SRA_PARTS, SRL_PARTS) instead of expanding to a libcall. Differential Revision: https://reviews.llvm.org/D59477 llvm-svn: 358498
This commit is contained in:
Luis Marques
parent
4d88b17b3f
commit
20d2424016
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@ -125,9 +125,9 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
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setOperationAction(ISD::SMUL_LOHI, XLenVT, Expand);
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setOperationAction(ISD::UMUL_LOHI, XLenVT, Expand);
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setOperationAction(ISD::SHL_PARTS, XLenVT, Expand);
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setOperationAction(ISD::SRL_PARTS, XLenVT, Expand);
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setOperationAction(ISD::SRA_PARTS, XLenVT, Expand);
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setOperationAction(ISD::SHL_PARTS, XLenVT, Custom);
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setOperationAction(ISD::SRL_PARTS, XLenVT, Custom);
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setOperationAction(ISD::SRA_PARTS, XLenVT, Custom);
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setOperationAction(ISD::ROTL, XLenVT, Expand);
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setOperationAction(ISD::ROTR, XLenVT, Expand);
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@ -360,6 +360,12 @@ SDValue RISCVTargetLowering::LowerOperation(SDValue Op,
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return lowerFRAMEADDR(Op, DAG);
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case ISD::RETURNADDR:
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return lowerRETURNADDR(Op, DAG);
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case ISD::SHL_PARTS:
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return lowerShiftLeftParts(Op, DAG);
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case ISD::SRA_PARTS:
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return lowerShiftRightParts(Op, DAG, true);
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case ISD::SRL_PARTS:
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return lowerShiftRightParts(Op, DAG, false);
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case ISD::BITCAST: {
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assert(Subtarget.is64Bit() && Subtarget.hasStdExtF() &&
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"Unexpected custom legalisation");
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@ -568,6 +574,97 @@ SDValue RISCVTargetLowering::lowerRETURNADDR(SDValue Op,
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return DAG.getCopyFromReg(DAG.getEntryNode(), DL, Reg, XLenVT);
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}
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SDValue RISCVTargetLowering::lowerShiftLeftParts(SDValue Op,
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SelectionDAG &DAG) const {
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SDLoc DL(Op);
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SDValue Lo = Op.getOperand(0);
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SDValue Hi = Op.getOperand(1);
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SDValue Shamt = Op.getOperand(2);
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EVT VT = Lo.getValueType();
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// if Shamt-XLEN < 0: // Shamt < XLEN
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// Lo = Lo << Shamt
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// Hi = (Hi << Shamt) | ((Lo >>u 1) >>u (XLEN-1 - Shamt))
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// else:
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// Lo = 0
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// Hi = Lo << (Shamt-XLEN)
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SDValue Zero = DAG.getConstant(0, DL, VT);
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SDValue One = DAG.getConstant(1, DL, VT);
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SDValue MinusXLen = DAG.getConstant(-(int)Subtarget.getXLen(), DL, VT);
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SDValue XLenMinus1 = DAG.getConstant(Subtarget.getXLen() - 1, DL, VT);
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SDValue ShamtMinusXLen = DAG.getNode(ISD::ADD, DL, VT, Shamt, MinusXLen);
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SDValue XLenMinus1Shamt = DAG.getNode(ISD::SUB, DL, VT, XLenMinus1, Shamt);
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SDValue LoTrue = DAG.getNode(ISD::SHL, DL, VT, Lo, Shamt);
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SDValue ShiftRight1Lo = DAG.getNode(ISD::SRL, DL, VT, Lo, One);
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SDValue ShiftRightLo =
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DAG.getNode(ISD::SRL, DL, VT, ShiftRight1Lo, XLenMinus1Shamt);
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SDValue ShiftLeftHi = DAG.getNode(ISD::SHL, DL, VT, Hi, Shamt);
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SDValue HiTrue = DAG.getNode(ISD::OR, DL, VT, ShiftLeftHi, ShiftRightLo);
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SDValue HiFalse = DAG.getNode(ISD::SHL, DL, VT, Lo, ShamtMinusXLen);
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SDValue CC = DAG.getSetCC(DL, VT, ShamtMinusXLen, Zero, ISD::SETLT);
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Lo = DAG.getNode(ISD::SELECT, DL, VT, CC, LoTrue, Zero);
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Hi = DAG.getNode(ISD::SELECT, DL, VT, CC, HiTrue, HiFalse);
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SDValue Parts[2] = {Lo, Hi};
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return DAG.getMergeValues(Parts, DL);
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}
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SDValue RISCVTargetLowering::lowerShiftRightParts(SDValue Op, SelectionDAG &DAG,
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bool IsSRA) const {
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SDLoc DL(Op);
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SDValue Lo = Op.getOperand(0);
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SDValue Hi = Op.getOperand(1);
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SDValue Shamt = Op.getOperand(2);
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EVT VT = Lo.getValueType();
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// SRA expansion:
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// if Shamt-XLEN < 0: // Shamt < XLEN
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// Lo = (Lo >>u Shamt) | ((Hi << 1) << (XLEN-1 - Shamt))
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// Hi = Hi >>s Shamt
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// else:
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// Lo = Hi >>s (Shamt-XLEN);
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// Hi = Hi >>s (XLEN-1)
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//
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// SRL expansion:
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// if Shamt-XLEN < 0: // Shamt < XLEN
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// Lo = (Lo >>u Shamt) | ((Hi << 1) << (XLEN-1 - Shamt))
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// Hi = Hi >>u Shamt
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// else:
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// Lo = Hi >>u (Shamt-XLEN);
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// Hi = 0;
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unsigned ShiftRightOp = IsSRA ? ISD::SRA : ISD::SRL;
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SDValue Zero = DAG.getConstant(0, DL, VT);
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SDValue One = DAG.getConstant(1, DL, VT);
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SDValue MinusXLen = DAG.getConstant(-(int)Subtarget.getXLen(), DL, VT);
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SDValue XLenMinus1 = DAG.getConstant(Subtarget.getXLen() - 1, DL, VT);
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SDValue ShamtMinusXLen = DAG.getNode(ISD::ADD, DL, VT, Shamt, MinusXLen);
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SDValue XLenMinus1Shamt = DAG.getNode(ISD::SUB, DL, VT, XLenMinus1, Shamt);
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SDValue ShiftRightLo = DAG.getNode(ISD::SRL, DL, VT, Lo, Shamt);
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SDValue ShiftLeftHi1 = DAG.getNode(ISD::SHL, DL, VT, Hi, One);
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SDValue ShiftLeftHi =
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DAG.getNode(ISD::SHL, DL, VT, ShiftLeftHi1, XLenMinus1Shamt);
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SDValue LoTrue = DAG.getNode(ISD::OR, DL, VT, ShiftRightLo, ShiftLeftHi);
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SDValue HiTrue = DAG.getNode(ShiftRightOp, DL, VT, Hi, Shamt);
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SDValue LoFalse = DAG.getNode(ShiftRightOp, DL, VT, Hi, ShamtMinusXLen);
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SDValue HiFalse =
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IsSRA ? DAG.getNode(ISD::SRA, DL, VT, Hi, XLenMinus1) : Zero;
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SDValue CC = DAG.getSetCC(DL, VT, ShamtMinusXLen, Zero, ISD::SETLT);
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Lo = DAG.getNode(ISD::SELECT, DL, VT, CC, LoTrue, LoFalse);
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Hi = DAG.getNode(ISD::SELECT, DL, VT, CC, HiTrue, HiFalse);
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SDValue Parts[2] = {Lo, Hi};
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return DAG.getMergeValues(Parts, DL);
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}
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// Returns the opcode of the target-specific SDNode that implements the 32-bit
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// form of the given Opcode.
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static RISCVISD::NodeType getRISCVWOpcode(unsigned Opcode) {
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@ -114,6 +114,12 @@ public:
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return ISD::SIGN_EXTEND;
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}
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bool shouldExpandShift(SelectionDAG &DAG, SDNode *N) const override {
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if (DAG.getMachineFunction().getFunction().hasMinSize())
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return false;
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return true;
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}
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private:
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void analyzeInputArgs(MachineFunction &MF, CCState &CCInfo,
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const SmallVectorImpl<ISD::InputArg> &Ins,
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@ -152,6 +158,8 @@ private:
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SDValue lowerVASTART(SDValue Op, SelectionDAG &DAG) const;
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SDValue lowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
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SDValue lowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
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SDValue lowerShiftLeftParts(SDValue Op, SelectionDAG &DAG) const;
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SDValue lowerShiftRightParts(SDValue Op, SelectionDAG &DAG, bool IsSRA) const;
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bool isEligibleForTailCallOptimization(
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CCState &CCInfo, CallLoweringInfo &CLI, MachineFunction &MF,
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@ -211,11 +211,20 @@ define i64 @sll(i64 %a, i64 %b) nounwind {
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;
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; RV32I-LABEL: sll:
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; RV32I: # %bb.0:
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; RV32I-NEXT: addi sp, sp, -16
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; RV32I-NEXT: sw ra, 12(sp)
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; RV32I-NEXT: call __ashldi3
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; RV32I-NEXT: lw ra, 12(sp)
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; RV32I-NEXT: addi sp, sp, 16
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; RV32I-NEXT: addi a3, a2, -32
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; RV32I-NEXT: bltz a3, .LBB11_2
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; RV32I-NEXT: # %bb.1:
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; RV32I-NEXT: sll a1, a0, a3
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; RV32I-NEXT: mv a0, zero
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; RV32I-NEXT: ret
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; RV32I-NEXT: .LBB11_2:
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; RV32I-NEXT: addi a3, zero, 31
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; RV32I-NEXT: sub a3, a3, a2
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; RV32I-NEXT: srli a4, a0, 1
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; RV32I-NEXT: srl a3, a4, a3
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; RV32I-NEXT: sll a1, a1, a2
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; RV32I-NEXT: or a1, a1, a3
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; RV32I-NEXT: sll a0, a0, a2
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; RV32I-NEXT: ret
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%1 = shl i64 %a, %b
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ret i64 %1
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@ -288,11 +297,20 @@ define i64 @srl(i64 %a, i64 %b) nounwind {
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;
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; RV32I-LABEL: srl:
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; RV32I: # %bb.0:
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; RV32I-NEXT: addi sp, sp, -16
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; RV32I-NEXT: sw ra, 12(sp)
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; RV32I-NEXT: call __lshrdi3
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; RV32I-NEXT: lw ra, 12(sp)
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; RV32I-NEXT: addi sp, sp, 16
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; RV32I-NEXT: addi a3, a2, -32
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; RV32I-NEXT: bltz a3, .LBB15_2
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; RV32I-NEXT: # %bb.1:
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; RV32I-NEXT: srl a0, a1, a3
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; RV32I-NEXT: mv a1, zero
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; RV32I-NEXT: ret
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; RV32I-NEXT: .LBB15_2:
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; RV32I-NEXT: addi a3, zero, 31
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; RV32I-NEXT: sub a3, a3, a2
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; RV32I-NEXT: slli a4, a1, 1
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; RV32I-NEXT: sll a3, a4, a3
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; RV32I-NEXT: srl a0, a0, a2
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; RV32I-NEXT: or a0, a0, a3
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; RV32I-NEXT: srl a1, a1, a2
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; RV32I-NEXT: ret
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%1 = lshr i64 %a, %b
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ret i64 %1
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@ -306,11 +324,20 @@ define i64 @sra(i64 %a, i64 %b) nounwind {
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;
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; RV32I-LABEL: sra:
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; RV32I: # %bb.0:
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; RV32I-NEXT: addi sp, sp, -16
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; RV32I-NEXT: sw ra, 12(sp)
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; RV32I-NEXT: call __ashrdi3
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; RV32I-NEXT: lw ra, 12(sp)
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; RV32I-NEXT: addi sp, sp, 16
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; RV32I-NEXT: addi a3, a2, -32
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; RV32I-NEXT: bltz a3, .LBB16_2
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; RV32I-NEXT: # %bb.1:
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; RV32I-NEXT: sra a0, a1, a3
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; RV32I-NEXT: srai a1, a1, 31
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; RV32I-NEXT: ret
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; RV32I-NEXT: .LBB16_2:
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; RV32I-NEXT: addi a3, zero, 31
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; RV32I-NEXT: sub a3, a3, a2
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; RV32I-NEXT: slli a4, a1, 1
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; RV32I-NEXT: sll a3, a4, a3
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; RV32I-NEXT: srl a0, a0, a2
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; RV32I-NEXT: or a0, a0, a3
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; RV32I-NEXT: sra a1, a1, a2
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; RV32I-NEXT: ret
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%1 = ashr i64 %a, %b
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ret i64 %1
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@ -1,6 +1,8 @@
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
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; RUN: | FileCheck %s -check-prefix=RV32I
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; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
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; RUN: | FileCheck %s -check-prefix=RV64I
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; Basic shift support is tested as part of ALU.ll. This file ensures that
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; shifts which may not be supported natively are lowered properly.
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@ -8,12 +10,44 @@
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define i64 @lshr64(i64 %a, i64 %b) nounwind {
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; RV32I-LABEL: lshr64:
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; RV32I: # %bb.0:
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; RV32I-NEXT: addi a3, a2, -32
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; RV32I-NEXT: bltz a3, .LBB0_2
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; RV32I-NEXT: # %bb.1:
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; RV32I-NEXT: srl a0, a1, a3
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; RV32I-NEXT: mv a1, zero
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; RV32I-NEXT: ret
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; RV32I-NEXT: .LBB0_2:
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; RV32I-NEXT: addi a3, zero, 31
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; RV32I-NEXT: sub a3, a3, a2
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; RV32I-NEXT: slli a4, a1, 1
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; RV32I-NEXT: sll a3, a4, a3
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; RV32I-NEXT: srl a0, a0, a2
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; RV32I-NEXT: or a0, a0, a3
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; RV32I-NEXT: srl a1, a1, a2
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; RV32I-NEXT: ret
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;
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; RV64I-LABEL: lshr64:
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; RV64I: # %bb.0:
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; RV64I-NEXT: srl a0, a0, a1
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; RV64I-NEXT: ret
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%1 = lshr i64 %a, %b
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ret i64 %1
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}
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define i64 @lshr64_minsize(i64 %a, i64 %b) minsize nounwind {
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; RV32I-LABEL: lshr64_minsize:
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; RV32I: # %bb.0:
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; RV32I-NEXT: addi sp, sp, -16
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; RV32I-NEXT: sw ra, 12(sp)
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; RV32I-NEXT: call __lshrdi3
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; RV32I-NEXT: lw ra, 12(sp)
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; RV32I-NEXT: addi sp, sp, 16
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; RV32I-NEXT: ret
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;
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; RV64I-LABEL: lshr64_minsize:
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; RV64I: # %bb.0:
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; RV64I-NEXT: srl a0, a0, a1
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; RV64I-NEXT: ret
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%1 = lshr i64 %a, %b
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ret i64 %1
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}
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@ -21,12 +55,44 @@ define i64 @lshr64(i64 %a, i64 %b) nounwind {
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define i64 @ashr64(i64 %a, i64 %b) nounwind {
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; RV32I-LABEL: ashr64:
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; RV32I: # %bb.0:
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; RV32I-NEXT: addi a3, a2, -32
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; RV32I-NEXT: bltz a3, .LBB2_2
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; RV32I-NEXT: # %bb.1:
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; RV32I-NEXT: sra a0, a1, a3
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; RV32I-NEXT: srai a1, a1, 31
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; RV32I-NEXT: ret
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; RV32I-NEXT: .LBB2_2:
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; RV32I-NEXT: addi a3, zero, 31
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; RV32I-NEXT: sub a3, a3, a2
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; RV32I-NEXT: slli a4, a1, 1
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; RV32I-NEXT: sll a3, a4, a3
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; RV32I-NEXT: srl a0, a0, a2
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; RV32I-NEXT: or a0, a0, a3
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; RV32I-NEXT: sra a1, a1, a2
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; RV32I-NEXT: ret
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;
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; RV64I-LABEL: ashr64:
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; RV64I: # %bb.0:
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; RV64I-NEXT: sra a0, a0, a1
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; RV64I-NEXT: ret
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%1 = ashr i64 %a, %b
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ret i64 %1
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}
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define i64 @ashr64_minsize(i64 %a, i64 %b) minsize nounwind {
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; RV32I-LABEL: ashr64_minsize:
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; RV32I: # %bb.0:
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; RV32I-NEXT: addi sp, sp, -16
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; RV32I-NEXT: sw ra, 12(sp)
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; RV32I-NEXT: call __ashrdi3
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; RV32I-NEXT: lw ra, 12(sp)
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; RV32I-NEXT: addi sp, sp, 16
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; RV32I-NEXT: ret
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;
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; RV64I-LABEL: ashr64_minsize:
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; RV64I: # %bb.0:
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; RV64I-NEXT: sra a0, a0, a1
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; RV64I-NEXT: ret
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%1 = ashr i64 %a, %b
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ret i64 %1
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}
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@ -34,12 +100,203 @@ define i64 @ashr64(i64 %a, i64 %b) nounwind {
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define i64 @shl64(i64 %a, i64 %b) nounwind {
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; RV32I-LABEL: shl64:
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; RV32I: # %bb.0:
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; RV32I-NEXT: addi a3, a2, -32
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; RV32I-NEXT: bltz a3, .LBB4_2
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; RV32I-NEXT: # %bb.1:
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; RV32I-NEXT: sll a1, a0, a3
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; RV32I-NEXT: mv a0, zero
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; RV32I-NEXT: ret
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; RV32I-NEXT: .LBB4_2:
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; RV32I-NEXT: addi a3, zero, 31
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; RV32I-NEXT: sub a3, a3, a2
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; RV32I-NEXT: srli a4, a0, 1
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; RV32I-NEXT: srl a3, a4, a3
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; RV32I-NEXT: sll a1, a1, a2
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; RV32I-NEXT: or a1, a1, a3
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; RV32I-NEXT: sll a0, a0, a2
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; RV32I-NEXT: ret
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;
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; RV64I-LABEL: shl64:
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; RV64I: # %bb.0:
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; RV64I-NEXT: sll a0, a0, a1
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; RV64I-NEXT: ret
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%1 = shl i64 %a, %b
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ret i64 %1
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}
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define i64 @shl64_minsize(i64 %a, i64 %b) minsize nounwind {
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; RV32I-LABEL: shl64_minsize:
|
||||
; RV32I: # %bb.0:
|
||||
; RV32I-NEXT: addi sp, sp, -16
|
||||
; RV32I-NEXT: sw ra, 12(sp)
|
||||
; RV32I-NEXT: call __ashldi3
|
||||
; RV32I-NEXT: lw ra, 12(sp)
|
||||
; RV32I-NEXT: addi sp, sp, 16
|
||||
; RV32I-NEXT: ret
|
||||
;
|
||||
; RV64I-LABEL: shl64_minsize:
|
||||
; RV64I: # %bb.0:
|
||||
; RV64I-NEXT: sll a0, a0, a1
|
||||
; RV64I-NEXT: ret
|
||||
%1 = shl i64 %a, %b
|
||||
ret i64 %1
|
||||
}
|
||||
|
||||
define i128 @lshr128(i128 %a, i128 %b) nounwind {
|
||||
; RV32I-LABEL: lshr128:
|
||||
; RV32I: # %bb.0:
|
||||
; RV32I-NEXT: addi sp, sp, -48
|
||||
; RV32I-NEXT: sw ra, 44(sp)
|
||||
; RV32I-NEXT: sw s0, 40(sp)
|
||||
; RV32I-NEXT: mv s0, a0
|
||||
; RV32I-NEXT: lw a0, 12(a1)
|
||||
; RV32I-NEXT: sw a0, 20(sp)
|
||||
; RV32I-NEXT: lw a0, 8(a1)
|
||||
; RV32I-NEXT: sw a0, 16(sp)
|
||||
; RV32I-NEXT: lw a0, 4(a1)
|
||||
; RV32I-NEXT: sw a0, 12(sp)
|
||||
; RV32I-NEXT: lw a0, 0(a1)
|
||||
; RV32I-NEXT: sw a0, 8(sp)
|
||||
; RV32I-NEXT: lw a2, 0(a2)
|
||||
; RV32I-NEXT: addi a0, sp, 24
|
||||
; RV32I-NEXT: addi a1, sp, 8
|
||||
; RV32I-NEXT: call __lshrti3
|
||||
; RV32I-NEXT: lw a0, 36(sp)
|
||||
; RV32I-NEXT: sw a0, 12(s0)
|
||||
; RV32I-NEXT: lw a0, 32(sp)
|
||||
; RV32I-NEXT: sw a0, 8(s0)
|
||||
; RV32I-NEXT: lw a0, 28(sp)
|
||||
; RV32I-NEXT: sw a0, 4(s0)
|
||||
; RV32I-NEXT: lw a0, 24(sp)
|
||||
; RV32I-NEXT: sw a0, 0(s0)
|
||||
; RV32I-NEXT: lw s0, 40(sp)
|
||||
; RV32I-NEXT: lw ra, 44(sp)
|
||||
; RV32I-NEXT: addi sp, sp, 48
|
||||
; RV32I-NEXT: ret
|
||||
;
|
||||
; RV64I-LABEL: lshr128:
|
||||
; RV64I: # %bb.0:
|
||||
; RV64I-NEXT: addi a3, a2, -64
|
||||
; RV64I-NEXT: bltz a3, .LBB6_2
|
||||
; RV64I-NEXT: # %bb.1:
|
||||
; RV64I-NEXT: srl a0, a1, a3
|
||||
; RV64I-NEXT: mv a1, zero
|
||||
; RV64I-NEXT: ret
|
||||
; RV64I-NEXT: .LBB6_2:
|
||||
; RV64I-NEXT: addi a3, zero, 63
|
||||
; RV64I-NEXT: sub a3, a3, a2
|
||||
; RV64I-NEXT: slli a4, a1, 1
|
||||
; RV64I-NEXT: sll a3, a4, a3
|
||||
; RV64I-NEXT: srl a0, a0, a2
|
||||
; RV64I-NEXT: or a0, a0, a3
|
||||
; RV64I-NEXT: srl a1, a1, a2
|
||||
; RV64I-NEXT: ret
|
||||
%1 = lshr i128 %a, %b
|
||||
ret i128 %1
|
||||
}
|
||||
|
||||
define i128 @ashr128(i128 %a, i128 %b) nounwind {
|
||||
; RV32I-LABEL: ashr128:
|
||||
; RV32I: # %bb.0:
|
||||
; RV32I-NEXT: addi sp, sp, -48
|
||||
; RV32I-NEXT: sw ra, 44(sp)
|
||||
; RV32I-NEXT: sw s0, 40(sp)
|
||||
; RV32I-NEXT: mv s0, a0
|
||||
; RV32I-NEXT: lw a0, 12(a1)
|
||||
; RV32I-NEXT: sw a0, 20(sp)
|
||||
; RV32I-NEXT: lw a0, 8(a1)
|
||||
; RV32I-NEXT: sw a0, 16(sp)
|
||||
; RV32I-NEXT: lw a0, 4(a1)
|
||||
; RV32I-NEXT: sw a0, 12(sp)
|
||||
; RV32I-NEXT: lw a0, 0(a1)
|
||||
; RV32I-NEXT: sw a0, 8(sp)
|
||||
; RV32I-NEXT: lw a2, 0(a2)
|
||||
; RV32I-NEXT: addi a0, sp, 24
|
||||
; RV32I-NEXT: addi a1, sp, 8
|
||||
; RV32I-NEXT: call __ashrti3
|
||||
; RV32I-NEXT: lw a0, 36(sp)
|
||||
; RV32I-NEXT: sw a0, 12(s0)
|
||||
; RV32I-NEXT: lw a0, 32(sp)
|
||||
; RV32I-NEXT: sw a0, 8(s0)
|
||||
; RV32I-NEXT: lw a0, 28(sp)
|
||||
; RV32I-NEXT: sw a0, 4(s0)
|
||||
; RV32I-NEXT: lw a0, 24(sp)
|
||||
; RV32I-NEXT: sw a0, 0(s0)
|
||||
; RV32I-NEXT: lw s0, 40(sp)
|
||||
; RV32I-NEXT: lw ra, 44(sp)
|
||||
; RV32I-NEXT: addi sp, sp, 48
|
||||
; RV32I-NEXT: ret
|
||||
;
|
||||
; RV64I-LABEL: ashr128:
|
||||
; RV64I: # %bb.0:
|
||||
; RV64I-NEXT: addi a3, a2, -64
|
||||
; RV64I-NEXT: bltz a3, .LBB7_2
|
||||
; RV64I-NEXT: # %bb.1:
|
||||
; RV64I-NEXT: sra a0, a1, a3
|
||||
; RV64I-NEXT: srai a1, a1, 63
|
||||
; RV64I-NEXT: ret
|
||||
; RV64I-NEXT: .LBB7_2:
|
||||
; RV64I-NEXT: addi a3, zero, 63
|
||||
; RV64I-NEXT: sub a3, a3, a2
|
||||
; RV64I-NEXT: slli a4, a1, 1
|
||||
; RV64I-NEXT: sll a3, a4, a3
|
||||
; RV64I-NEXT: srl a0, a0, a2
|
||||
; RV64I-NEXT: or a0, a0, a3
|
||||
; RV64I-NEXT: sra a1, a1, a2
|
||||
; RV64I-NEXT: ret
|
||||
%1 = ashr i128 %a, %b
|
||||
ret i128 %1
|
||||
}
|
||||
|
||||
define i128 @shl128(i128 %a, i128 %b) nounwind {
|
||||
; RV32I-LABEL: shl128:
|
||||
; RV32I: # %bb.0:
|
||||
; RV32I-NEXT: addi sp, sp, -48
|
||||
; RV32I-NEXT: sw ra, 44(sp)
|
||||
; RV32I-NEXT: sw s0, 40(sp)
|
||||
; RV32I-NEXT: mv s0, a0
|
||||
; RV32I-NEXT: lw a0, 12(a1)
|
||||
; RV32I-NEXT: sw a0, 20(sp)
|
||||
; RV32I-NEXT: lw a0, 8(a1)
|
||||
; RV32I-NEXT: sw a0, 16(sp)
|
||||
; RV32I-NEXT: lw a0, 4(a1)
|
||||
; RV32I-NEXT: sw a0, 12(sp)
|
||||
; RV32I-NEXT: lw a0, 0(a1)
|
||||
; RV32I-NEXT: sw a0, 8(sp)
|
||||
; RV32I-NEXT: lw a2, 0(a2)
|
||||
; RV32I-NEXT: addi a0, sp, 24
|
||||
; RV32I-NEXT: addi a1, sp, 8
|
||||
; RV32I-NEXT: call __ashlti3
|
||||
; RV32I-NEXT: lw a0, 36(sp)
|
||||
; RV32I-NEXT: sw a0, 12(s0)
|
||||
; RV32I-NEXT: lw a0, 32(sp)
|
||||
; RV32I-NEXT: sw a0, 8(s0)
|
||||
; RV32I-NEXT: lw a0, 28(sp)
|
||||
; RV32I-NEXT: sw a0, 4(s0)
|
||||
; RV32I-NEXT: lw a0, 24(sp)
|
||||
; RV32I-NEXT: sw a0, 0(s0)
|
||||
; RV32I-NEXT: lw s0, 40(sp)
|
||||
; RV32I-NEXT: lw ra, 44(sp)
|
||||
; RV32I-NEXT: addi sp, sp, 48
|
||||
; RV32I-NEXT: ret
|
||||
;
|
||||
; RV64I-LABEL: shl128:
|
||||
; RV64I: # %bb.0:
|
||||
; RV64I-NEXT: addi a3, a2, -64
|
||||
; RV64I-NEXT: bltz a3, .LBB8_2
|
||||
; RV64I-NEXT: # %bb.1:
|
||||
; RV64I-NEXT: sll a1, a0, a3
|
||||
; RV64I-NEXT: mv a0, zero
|
||||
; RV64I-NEXT: ret
|
||||
; RV64I-NEXT: .LBB8_2:
|
||||
; RV64I-NEXT: addi a3, zero, 63
|
||||
; RV64I-NEXT: sub a3, a3, a2
|
||||
; RV64I-NEXT: srli a4, a0, 1
|
||||
; RV64I-NEXT: srl a3, a4, a3
|
||||
; RV64I-NEXT: sll a1, a1, a2
|
||||
; RV64I-NEXT: or a1, a1, a3
|
||||
; RV64I-NEXT: sll a0, a0, a2
|
||||
; RV64I-NEXT: ret
|
||||
%1 = shl i128 %a, %b
|
||||
ret i128 %1
|
||||
}
|
||||
|
|
|
|||
Loading…
Reference in New Issue