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Expand SREM and UREM for targets that claim not to have them, like PowerPC 

llvm-svn: 21103
This commit is contained in:
Nate Begeman 2005-04-06 00:23:54 +00:00
parent 55e8625c69
commit 20b7d2a36f
1 changed files with 25 additions and 2 deletions
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27
llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
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@ -854,8 +854,6 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) {
case ISD::MUL:
case ISD::UDIV:
case ISD::SDIV:
case ISD::UREM:
case ISD::SREM:
case ISD::AND:
case ISD::OR:
case ISD::XOR:
@ -868,6 +866,31 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) {
Tmp2 != Node->getOperand(1))
Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1,Tmp2);
break;
case ISD::UREM:
case ISD::SREM:
Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS
switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
case TargetLowering::Legal:
if (Tmp1 != Node->getOperand(0) ||
Tmp2 != Node->getOperand(1))
Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1,
Tmp2);
break;
case TargetLowering::Promote:
case TargetLowering::Custom:
assert(0 && "Cannot promote/custom handle this yet!");
case TargetLowering::Expand: {
MVT::ValueType VT = Node->getValueType(0);
unsigned Opc = (Node->getOpcode() == ISD::UREM) ? ISD::UDIV : ISD::SDIV;
Result = DAG.getNode(Opc, VT, Tmp1, Tmp2);
Result = DAG.getNode(ISD::MUL, VT, Result, Tmp2);
Result = DAG.getNode(ISD::SUB, VT, Tmp1, Result);
}
break;
}
break;
// Unary operators
case ISD::FABS: