maxjhandsome
/
llvm-project
forked from OSchip/llvm-project
1
0
Fork 0
Code Issues Pull Requests Packages Releases Wiki Activity

[mips][microMIPSr6] Implement BITSWAP instruction 

Implement BITSWAP instruction using mapping.

Differential Revision: http://reviews.llvm.org/D8857

llvm-svn: 235321
This commit is contained in:
Jozef Kolek 2015-04-20 18:14:59 +00:00
parent fa8aa172ad
commit 207d248eba
5 changed files with 34 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

14
llvm/lib/Target/Mips/MicroMips32r6InstrFormats.td
View File

@ -15,3 +15,17 @@ class MMR6Arch<string opstr> {
string Arch = "micromipsr6";
string BaseOpcode = opstr;
}
class POOL32A_BITSWAP_FM_MMR6<bits<6> funct> : MipsR6Inst {
bits<5> rd;
bits<5> rt;
bits<32> Inst;
let Inst{31-26} = 0b000000;
let Inst{25-21} = rt;
let Inst{20-16} = rd;
let Inst{15-12} = 0b0000;
let Inst{11-6} = funct;
let Inst{5-0} = 0b111100;
}

13
llvm/lib/Target/Mips/MicroMips32r6InstrInfo.td
View File

@ -19,6 +19,7 @@
class BALC_MMR6_ENC : BRANCH_OFF26_FM<0b101101>;
class BC_MMR6_ENC : BRANCH_OFF26_FM<0b100101>;
class BITSWAP_MMR6_ENC : POOL32A_BITSWAP_FM_MMR6<0b101100>;
//===----------------------------------------------------------------------===//
//
@ -40,6 +41,16 @@ class BALC_MMR6_DESC : BC_MMR6_DESC_BASE<"balc", brtarget26> {
}
class BC_MMR6_DESC : BC_MMR6_DESC_BASE<"bc", brtarget26>;
class BITSWAP_MMR6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd>
: MMR6Arch<instr_asm> {
dag OutOperandList = (outs GPROpnd:$rd);
dag InOperandList = (ins GPROpnd:$rt);
string AsmString = !strconcat(instr_asm, "\t$rd, $rt");
list<dag> Pattern = [];
}
class BITSWAP_MMR6_DESC : BITSWAP_MMR6_DESC_BASE<"bitswap", GPR32Opnd>;
//===----------------------------------------------------------------------===//
//
// Instruction Definitions
@ -49,4 +60,6 @@ class BC_MMR6_DESC : BC_MMR6_DESC_BASE<"bc", brtarget26>;
let DecoderNamespace = "MicroMips32r6" in {
def BALC_MMR6 : R6MMR6Rel, BALC_MMR6_ENC, BALC_MMR6_DESC, ISA_MICROMIPS32R6;
def BC_MMR6 : R6MMR6Rel, BC_MMR6_ENC, BC_MMR6_DESC, ISA_MICROMIPS32R6;
def BITSWAP_MMR6 : R6MMR6Rel, BITSWAP_MMR6_ENC, BITSWAP_MMR6_DESC,
ISA_MICROMIPS32R6;
}

5
llvm/lib/Target/Mips/Mips32r6InstrInfo.td
View File

@ -401,7 +401,8 @@ class JR_HB_R6_DESC : JR_HB_DESC_BASE<"jr.hb", GPR32Opnd> {
bit isBarrier=1;
}
class BITSWAP_DESC_BASE<string instr_asm, RegisterOperand GPROpnd> {
class BITSWAP_DESC_BASE<string instr_asm, RegisterOperand GPROpnd>
: MipsR6Arch<instr_asm> {
dag OutOperandList = (outs GPROpnd:$rd);
dag InOperandList = (ins GPROpnd:$rt);
string AsmString = !strconcat(instr_asm, "\t$rd, $rt");
@ -664,7 +665,7 @@ def BGEZALC : BGEZALC_ENC, BGEZALC_DESC, ISA_MIPS32R6;
def BGEZC : BGEZC_ENC, BGEZC_DESC, ISA_MIPS32R6;
def BGTZALC : BGTZALC_ENC, BGTZALC_DESC, ISA_MIPS32R6;
def BGTZC : BGTZC_ENC, BGTZC_DESC, ISA_MIPS32R6;
def BITSWAP : BITSWAP_ENC, BITSWAP_DESC, ISA_MIPS32R6;
def BITSWAP : R6MMR6Rel, BITSWAP_ENC, BITSWAP_DESC, ISA_MIPS32R6;
def BLEZALC : BLEZALC_ENC, BLEZALC_DESC, ISA_MIPS32R6;
def BLEZC : BLEZC_ENC, BLEZC_DESC, ISA_MIPS32R6;
def BLTC : BLTC_ENC, BLTC_DESC, ISA_MIPS32R6;

3
llvm/test/MC/Disassembler/Mips/micromips32r6.txt
View File

@ -5,3 +5,6 @@
# CHECK: bc 14572256
0x94 0x37 0x96 0xb8
# CHECK: bitswap $4, $2
0x00 0x44 0x0b 0x3c

1
llvm/test/MC/Mips/micromips32r6/valid.s
View File

@ -3,3 +3,4 @@
.set noat
balc 14572256 # CHECK: balc 14572256 # encoding: [0xb4,0x37,0x96,0xb8]
bc 14572256 # CHECK: bc 14572256 # encoding: [0x94,0x37,0x96,0xb8]
bitswap $4, $2 # CHECK: bitswap $4, $2 # encoding: [0x00,0x44,0x0b,0x3c]