forked from OSchip/llvm-project
AMDGPU: Don't look for constant in insert/extract_vector_elt regbankselect
The constantness shouldn't change the register bank choice. We also don't need to restrict this to only indexing VGPRs, since it's possible to index SGPRs (but SelectionDAG made using this difficult). Allow directly indexing SGPRs when appropriate. llvm-svn: 356611
This commit is contained in:
Matt Arsenault
parent
f6f4f84378
commit
2065206a9d
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@ -52,24 +52,6 @@ AMDGPURegisterBankInfo::AMDGPURegisterBankInfo(const TargetRegisterInfo &TRI)
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}
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static bool isConstant(const MachineOperand &MO, int64_t &C) {
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const MachineFunction *MF = MO.getParent()->getParent()->getParent();
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const MachineRegisterInfo &MRI = MF->getRegInfo();
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const MachineInstr *Def = MRI.getVRegDef(MO.getReg());
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if (!Def)
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return false;
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if (Def->getOpcode() == AMDGPU::G_CONSTANT) {
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C = Def->getOperand(1).getCImm()->getSExtValue();
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return true;
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}
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if (Def->getOpcode() == AMDGPU::COPY)
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return isConstant(Def->getOperand(1), C);
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return false;
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}
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unsigned AMDGPURegisterBankInfo::copyCost(const RegisterBank &Dst,
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const RegisterBank &Src,
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unsigned Size) const {
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@ -816,42 +798,35 @@ AMDGPURegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
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case AMDGPU::G_EXTRACT_VECTOR_ELT: {
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unsigned IdxOp = 2;
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int64_t Imm;
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// XXX - Do we really need to fully handle these? The constant case should
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// be legalized away before RegBankSelect?
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unsigned OutputBankID = isSALUMapping(MI) && isConstant(MI.getOperand(IdxOp), Imm) ?
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unsigned OutputBankID = isSALUMapping(MI) ?
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AMDGPU::SGPRRegBankID : AMDGPU::VGPRRegBankID;
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unsigned SrcSize = MRI.getType(MI.getOperand(1).getReg()).getSizeInBits();
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unsigned IdxSize = MRI.getType(MI.getOperand(2).getReg()).getSizeInBits();
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unsigned IdxBank = getRegBankID(MI.getOperand(2).getReg(), MRI, *TRI);
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OpdsMapping[0] = AMDGPU::getValueMapping(OutputBankID, MRI.getType(MI.getOperand(0).getReg()).getSizeInBits());
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OpdsMapping[1] = AMDGPU::getValueMapping(OutputBankID, MRI.getType(MI.getOperand(1).getReg()).getSizeInBits());
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OpdsMapping[0] = AMDGPU::getValueMapping(OutputBankID, SrcSize);
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OpdsMapping[1] = AMDGPU::getValueMapping(OutputBankID, SrcSize);
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// The index can be either if the source vector is VGPR.
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OpdsMapping[2] = AMDGPU::getValueMapping(IdxBank, MRI.getType(MI.getOperand(2).getReg()).getSizeInBits());
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OpdsMapping[2] = AMDGPU::getValueMapping(IdxBank, IdxSize);
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break;
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}
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case AMDGPU::G_INSERT_VECTOR_ELT: {
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// XXX - Do we really need to fully handle these? The constant case should
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// be legalized away before RegBankSelect?
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int64_t Imm;
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unsigned IdxOp = MI.getOpcode() == AMDGPU::G_EXTRACT_VECTOR_ELT ? 2 : 3;
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unsigned BankID = isSALUMapping(MI) && isConstant(MI.getOperand(IdxOp), Imm) ?
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unsigned OutputBankID = isSALUMapping(MI) ?
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AMDGPU::SGPRRegBankID : AMDGPU::VGPRRegBankID;
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unsigned VecSize = MRI.getType(MI.getOperand(0).getReg()).getSizeInBits();
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unsigned InsertSize = MRI.getType(MI.getOperand(2).getReg()).getSizeInBits();
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unsigned IdxSize = MRI.getType(MI.getOperand(3).getReg()).getSizeInBits();
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unsigned InsertEltBank = getRegBankID(MI.getOperand(2).getReg(), MRI, *TRI);
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unsigned IdxBank = getRegBankID(MI.getOperand(3).getReg(), MRI, *TRI);
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OpdsMapping[0] = AMDGPU::getValueMapping(OutputBankID, VecSize);
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OpdsMapping[1] = AMDGPU::getValueMapping(OutputBankID, VecSize);
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OpdsMapping[2] = AMDGPU::getValueMapping(InsertEltBank, InsertSize);
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// TODO: Can do SGPR indexing, which would obviate the need for the
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// isConstant check.
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for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
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unsigned Size = getSizeInBits(MI.getOperand(i).getReg(), MRI, *TRI);
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OpdsMapping[i] = AMDGPU::getValueMapping(BankID, Size);
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}
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// The index can be either if the source vector is VGPR.
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OpdsMapping[3] = AMDGPU::getValueMapping(IdxBank, IdxSize);
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break;
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}
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case AMDGPU::G_UNMERGE_VALUES: {
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@ -1,39 +1,76 @@
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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck %s
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# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck %s
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---
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name: extract_vector_elt_0_v2i32_s
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name: extract_vector_elt_v16i32_ss
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legalized: true
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body: |
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bb.0:
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liveins: $sgpr0_sgpr1
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; CHECK-LABEL: name: extract_vector_elt_0_v2i32_s
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; CHECK: [[COPY:%[0-9]+]]:sgpr(<2 x s32>) = COPY $sgpr0_sgpr1
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; CHECK: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0
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; CHECK: [[EVEC:%[0-9]+]]:sgpr(s32) = G_EXTRACT_VECTOR_ELT [[COPY]](<2 x s32>), [[C]](s32)
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liveins: $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15, $sgpr16
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; CHECK-LABEL: name: extract_vector_elt_v16i32_ss
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; CHECK: [[COPY:%[0-9]+]]:sgpr(<16 x s32>) = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15
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; CHECK: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr16
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; CHECK: [[EVEC:%[0-9]+]]:sgpr(s32) = G_EXTRACT_VECTOR_ELT [[COPY]](<16 x s32>), [[COPY1]](s32)
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; CHECK: $vgpr0 = COPY [[EVEC]](s32)
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%0:_(<2 x s32>) = COPY $sgpr0_sgpr1
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%1:_(s32) = G_CONSTANT i32 0
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%0:_(<16 x s32>) = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15
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%1:_(s32) = COPY $sgpr16
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%2:_(s32) = G_EXTRACT_VECTOR_ELT %0, %1
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$vgpr0 = COPY %2
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...
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---
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name: extract_vector_elt_0_v4i32_s
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name: extract_vector_elt_v16i32_sv
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legalized: true
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body: |
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bb.0:
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liveins: $sgpr0_sgpr1_sgpr2_sgpr3
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; CHECK-LABEL: name: extract_vector_elt_0_v4i32_s
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; CHECK: [[COPY:%[0-9]+]]:sgpr(<4 x s32>) = COPY $sgpr0_sgpr1_sgpr2_sgpr3
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; CHECK: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0
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; CHECK: [[EVEC:%[0-9]+]]:sgpr(s32) = G_EXTRACT_VECTOR_ELT [[COPY]](<4 x s32>), [[C]](s32)
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liveins: $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15, $vgpr0
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; CHECK-LABEL: name: extract_vector_elt_v16i32_sv
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; CHECK: [[COPY:%[0-9]+]]:sgpr(<16 x s32>) = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15
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; CHECK: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
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; CHECK: [[COPY2:%[0-9]+]]:vgpr(<16 x s32>) = COPY [[COPY]](<16 x s32>)
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; CHECK: [[EVEC:%[0-9]+]]:vgpr(s32) = G_EXTRACT_VECTOR_ELT [[COPY2]](<16 x s32>), [[COPY1]](s32)
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; CHECK: $vgpr0 = COPY [[EVEC]](s32)
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%0:_(<4 x s32>) = COPY $sgpr0_sgpr1_sgpr2_sgpr3
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%1:_(s32) = G_CONSTANT i32 0
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%0:_(<16 x s32>) = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15
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%1:_(s32) = COPY $vgpr0
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%2:_(s32) = G_EXTRACT_VECTOR_ELT %0, %1
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$vgpr0 = COPY %2
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...
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---
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name: extract_vector_elt_v16i32_vs
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legalized: true
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body: |
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bb.0:
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liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, $sgpr0
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; CHECK-LABEL: name: extract_vector_elt_v16i32_vs
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; CHECK: [[COPY:%[0-9]+]]:vgpr(<16 x s32>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
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; CHECK: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
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; CHECK: [[EVEC:%[0-9]+]]:vgpr(s32) = G_EXTRACT_VECTOR_ELT [[COPY]](<16 x s32>), [[COPY1]](s32)
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; CHECK: $vgpr0 = COPY [[EVEC]](s32)
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%0:_(<16 x s32>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
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%1:_(s32) = COPY $sgpr0
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%2:_(s32) = G_EXTRACT_VECTOR_ELT %0, %1
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$vgpr0 = COPY %2
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...
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---
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name: extract_vector_elt_v16i32_vv
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legalized: true
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body: |
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bb.0:
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liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, $vgpr16
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; CHECK-LABEL: name: extract_vector_elt_v16i32_vv
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; CHECK: [[COPY:%[0-9]+]]:vgpr(<16 x s32>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
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; CHECK: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr16
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; CHECK: [[EVEC:%[0-9]+]]:vgpr(s32) = G_EXTRACT_VECTOR_ELT [[COPY]](<16 x s32>), [[COPY1]](s32)
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; CHECK: $vgpr0 = COPY [[EVEC]](s32)
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%0:_(<16 x s32>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
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%1:_(s32) = COPY $vgpr16
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%2:_(s32) = G_EXTRACT_VECTOR_ELT %0, %1
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$vgpr0 = COPY %2
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...
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@ -1,111 +1,111 @@
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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck %s
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# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck %s
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---
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name: insert_vector_elt_v4i32_s_s_k
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name: insert_vector_elt_v4i32_s_s_s
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legalized: true
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body: |
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bb.0:
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liveins: $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr5
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; CHECK-LABEL: name: insert_vector_elt_v4i32_s_s_k
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liveins: $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr4, $sgpr5
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; CHECK-LABEL: name: insert_vector_elt_v4i32_s_s_s
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; CHECK: [[COPY:%[0-9]+]]:sgpr(<4 x s32>) = COPY $sgpr0_sgpr1_sgpr2_sgpr3
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; CHECK: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr5
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; CHECK: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0
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; CHECK: [[IVEC:%[0-9]+]]:sgpr(<4 x s32>) = G_INSERT_VECTOR_ELT [[COPY]], [[COPY1]](s32), [[C]](s32)
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; CHECK: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr4
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; CHECK: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr5
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; CHECK: [[IVEC:%[0-9]+]]:sgpr(<4 x s32>) = G_INSERT_VECTOR_ELT [[COPY]], [[COPY1]](s32), [[COPY2]](s32)
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; CHECK: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[IVEC]](<4 x s32>)
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%0:_(<4 x s32>) = COPY $sgpr0_sgpr1_sgpr2_sgpr3
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%1:_(s32) = COPY $sgpr5
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%2:_(s32) = G_CONSTANT i32 0
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%1:_(s32) = COPY $sgpr4
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%2:_(s32) = COPY $sgpr5
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%3:_(<4 x s32>) = G_INSERT_VECTOR_ELT %0, %1, %2
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$sgpr0_sgpr1_sgpr2_sgpr3 = COPY %3
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...
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---
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name: insert_vector_elt_v4i32_v_s_k
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name: insert_vector_elt_v4i32_v_s_s
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legalized: true
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body: |
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bb.0:
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liveins: $vgpr0_vgpr1_vgpr2_vgpr3, $sgpr5
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; CHECK-LABEL: name: insert_vector_elt_v4i32_v_s_k
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liveins: $vgpr0_vgpr1_vgpr2_vgpr3, $sgpr0, $sgpr1
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; CHECK-LABEL: name: insert_vector_elt_v4i32_v_s_s
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; CHECK: [[COPY:%[0-9]+]]:vgpr(<4 x s32>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
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; CHECK: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr5
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; CHECK: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0
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; CHECK: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32)
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; CHECK: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)
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; CHECK: [[IVEC:%[0-9]+]]:vgpr(<4 x s32>) = G_INSERT_VECTOR_ELT [[COPY]], [[COPY2]](s32), [[COPY3]](s32)
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; CHECK: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
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; CHECK: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
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; CHECK: [[IVEC:%[0-9]+]]:vgpr(<4 x s32>) = G_INSERT_VECTOR_ELT [[COPY]], [[COPY1]](s32), [[COPY2]](s32)
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; CHECK: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[IVEC]](<4 x s32>)
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%0:_(<4 x s32>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
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%1:_(s32) = COPY $sgpr5
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%2:_(s32) = G_CONSTANT i32 0
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%1:_(s32) = COPY $sgpr0
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%2:_(s32) = COPY $sgpr1
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%3:_(<4 x s32>) = G_INSERT_VECTOR_ELT %0, %1, %2
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$sgpr0_sgpr1_sgpr2_sgpr3 = COPY %3
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...
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---
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name: insert_vector_elt_v4i32_s_v_k
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name: insert_vector_elt_v4i32_s_v_s
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legalized: true
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body: |
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bb.0:
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liveins: $sgpr0_sgpr1_sgpr2_sgpr3, $vgpr5
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; CHECK-LABEL: name: insert_vector_elt_v4i32_s_v_k
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; CHECK: [[COPY:%[0-9]+]]:sgpr(<4 x s32>) = COPY $sgpr0_sgpr1_sgpr2_sgpr3
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; CHECK: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr2
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; CHECK: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0
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; CHECK: [[COPY2:%[0-9]+]]:vgpr(<4 x s32>) = COPY [[COPY]](<4 x s32>)
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; CHECK: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)
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; CHECK: [[IVEC:%[0-9]+]]:vgpr(<4 x s32>) = G_INSERT_VECTOR_ELT [[COPY2]], [[COPY1]](s32), [[COPY3]](s32)
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; CHECK: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[IVEC]](<4 x s32>)
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%0:_(<4 x s32>) = COPY $sgpr0_sgpr1_sgpr2_sgpr3
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%1:_(s32) = COPY $vgpr2
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%2:_(s32) = G_CONSTANT i32 0
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%3:_(<4 x s32>) = G_INSERT_VECTOR_ELT %0, %1, %2
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$sgpr0_sgpr1_sgpr2_sgpr3 = COPY %3
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...
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liveins: $sgpr0_sgpr1_sgpr2_sgpr3, $vgpr0, $sgpr4
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---
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name: insert_vector_elt_var_v4i32_s_s_s
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legalized: true
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body: |
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bb.0:
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liveins: $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr5, $sgpr6
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; CHECK-LABEL: name: insert_vector_elt_var_v4i32_s_s_s
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; CHECK-LABEL: name: insert_vector_elt_v4i32_s_v_s
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; CHECK: [[COPY:%[0-9]+]]:sgpr(<4 x s32>) = COPY $sgpr0_sgpr1_sgpr2_sgpr3
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; CHECK: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr5
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; CHECK: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr6
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; CHECK: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
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; CHECK: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr4
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; CHECK: [[COPY3:%[0-9]+]]:vgpr(<4 x s32>) = COPY [[COPY]](<4 x s32>)
|
||||
; CHECK: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32)
|
||||
; CHECK: [[COPY5:%[0-9]+]]:vgpr(s32) = COPY [[COPY2]](s32)
|
||||
; CHECK: [[IVEC:%[0-9]+]]:vgpr(<4 x s32>) = G_INSERT_VECTOR_ELT [[COPY3]], [[COPY4]](s32), [[COPY5]](s32)
|
||||
; CHECK: [[IVEC:%[0-9]+]]:vgpr(<4 x s32>) = G_INSERT_VECTOR_ELT [[COPY3]], [[COPY1]](s32), [[COPY2]](s32)
|
||||
; CHECK: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[IVEC]](<4 x s32>)
|
||||
%0:_(<4 x s32>) = COPY $sgpr0_sgpr1_sgpr2_sgpr3
|
||||
%1:_(s32) = COPY $sgpr5
|
||||
%2:_(s32) = COPY $sgpr6
|
||||
%1:_(s32) = COPY $vgpr0
|
||||
%2:_(s32) = COPY $sgpr4
|
||||
%3:_(<4 x s32>) = G_INSERT_VECTOR_ELT %0, %1, %2
|
||||
$sgpr0_sgpr1_sgpr2_sgpr3 = COPY %3
|
||||
...
|
||||
|
||||
---
|
||||
name: insert_vector_elt_var_v4i32_s_s_v
|
||||
name: insert_vector_elt_v4i32_s_s_v
|
||||
legalized: true
|
||||
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr5, $vgpr6
|
||||
; CHECK-LABEL: name: insert_vector_elt_var_v4i32_s_s_v
|
||||
liveins: $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr4, $vgpr0
|
||||
|
||||
; CHECK-LABEL: name: insert_vector_elt_v4i32_s_s_v
|
||||
; CHECK: [[COPY:%[0-9]+]]:sgpr(<4 x s32>) = COPY $sgpr0_sgpr1_sgpr2_sgpr3
|
||||
; CHECK: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr5
|
||||
; CHECK: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY $vgpr6
|
||||
; CHECK: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr4
|
||||
; CHECK: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
|
||||
; CHECK: [[COPY3:%[0-9]+]]:vgpr(<4 x s32>) = COPY [[COPY]](<4 x s32>)
|
||||
; CHECK: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32)
|
||||
; CHECK: [[IVEC:%[0-9]+]]:vgpr(<4 x s32>) = G_INSERT_VECTOR_ELT [[COPY3]], [[COPY4]](s32), [[COPY2]](s32)
|
||||
; CHECK: [[IVEC:%[0-9]+]]:vgpr(<4 x s32>) = G_INSERT_VECTOR_ELT [[COPY3]], [[COPY1]](s32), [[COPY2]](s32)
|
||||
; CHECK: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[IVEC]](<4 x s32>)
|
||||
%0:_(<4 x s32>) = COPY $sgpr0_sgpr1_sgpr2_sgpr3
|
||||
%1:_(s32) = COPY $sgpr5
|
||||
%2:_(s32) = COPY $vgpr6
|
||||
%1:_(s32) = COPY $sgpr4
|
||||
%2:_(s32) = COPY $vgpr0
|
||||
%3:_(<4 x s32>) = G_INSERT_VECTOR_ELT %0, %1, %2
|
||||
$sgpr0_sgpr1_sgpr2_sgpr3 = COPY %3
|
||||
...
|
||||
|
||||
---
|
||||
name: insert_vector_elt_v4i32_s_v_v
|
||||
legalized: true
|
||||
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: $sgpr0_sgpr1_sgpr2_sgpr3, $vgpr0, $vgpr1
|
||||
|
||||
; CHECK-LABEL: name: insert_vector_elt_v4i32_s_v_v
|
||||
; CHECK: [[COPY:%[0-9]+]]:sgpr(<4 x s32>) = COPY $sgpr0_sgpr1_sgpr2_sgpr3
|
||||
; CHECK: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
|
||||
; CHECK: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY $vgpr1
|
||||
; CHECK: [[COPY3:%[0-9]+]]:vgpr(<4 x s32>) = COPY [[COPY]](<4 x s32>)
|
||||
; CHECK: [[IVEC:%[0-9]+]]:vgpr(<4 x s32>) = G_INSERT_VECTOR_ELT [[COPY3]], [[COPY1]](s32), [[COPY2]](s32)
|
||||
; CHECK: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[IVEC]](<4 x s32>)
|
||||
%0:_(<4 x s32>) = COPY $sgpr0_sgpr1_sgpr2_sgpr3
|
||||
%1:_(s32) = COPY $vgpr0
|
||||
%2:_(s32) = COPY $vgpr1
|
||||
%3:_(<4 x s32>) = G_INSERT_VECTOR_ELT %0, %1, %2
|
||||
$sgpr0_sgpr1_sgpr2_sgpr3 = COPY %3
|
||||
...
|
||||
|
|
@ -116,17 +116,38 @@ legalized: true
|
|||
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: $vgpr0_vgpr1_vgpr2_vgpr3, $sgpr5, $vgpr6
|
||||
liveins: $vgpr0_vgpr1_vgpr2_vgpr3, $sgpr4, $vgpr0
|
||||
|
||||
; CHECK-LABEL: name: insert_vector_elt_var_v4i32_v_s_v
|
||||
; CHECK: [[COPY:%[0-9]+]]:vgpr(<4 x s32>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
|
||||
; CHECK: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr5
|
||||
; CHECK: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY $vgpr6
|
||||
; CHECK: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32)
|
||||
; CHECK: [[IVEC:%[0-9]+]]:vgpr(<4 x s32>) = G_INSERT_VECTOR_ELT [[COPY]], [[COPY3]](s32), [[COPY2]](s32)
|
||||
; CHECK: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr4
|
||||
; CHECK: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
|
||||
; CHECK: [[IVEC:%[0-9]+]]:vgpr(<4 x s32>) = G_INSERT_VECTOR_ELT [[COPY]], [[COPY1]](s32), [[COPY2]](s32)
|
||||
; CHECK: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[IVEC]](<4 x s32>)
|
||||
%0:_(<4 x s32>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
|
||||
%1:_(s32) = COPY $sgpr5
|
||||
%2:_(s32) = COPY $vgpr6
|
||||
%1:_(s32) = COPY $sgpr4
|
||||
%2:_(s32) = COPY $vgpr0
|
||||
%3:_(<4 x s32>) = G_INSERT_VECTOR_ELT %0, %1, %2
|
||||
$sgpr0_sgpr1_sgpr2_sgpr3 = COPY %3
|
||||
...
|
||||
|
||||
---
|
||||
name: insert_vector_elt_var_v4i32_v_v_s
|
||||
legalized: true
|
||||
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: $vgpr0_vgpr1_vgpr2_vgpr3, $vgpr4, $sgpr0
|
||||
|
||||
; CHECK-LABEL: name: insert_vector_elt_var_v4i32_v_v_s
|
||||
; CHECK: [[COPY:%[0-9]+]]:vgpr(<4 x s32>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
|
||||
; CHECK: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
|
||||
; CHECK: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
|
||||
; CHECK: [[IVEC:%[0-9]+]]:vgpr(<4 x s32>) = G_INSERT_VECTOR_ELT [[COPY]], [[COPY1]](s32), [[COPY2]](s32)
|
||||
; CHECK: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[IVEC]](<4 x s32>)
|
||||
%0:_(<4 x s32>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
|
||||
%1:_(s32) = COPY $vgpr0
|
||||
%2:_(s32) = COPY $sgpr0
|
||||
%3:_(<4 x s32>) = G_INSERT_VECTOR_ELT %0, %1, %2
|
||||
$sgpr0_sgpr1_sgpr2_sgpr3 = COPY %3
|
||||
...
|
||||
|
|
@ -137,16 +158,17 @@ legalized: true
|
|||
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: $vgpr0_vgpr1_vgpr2_vgpr3, $vgpr5, $vgpr6
|
||||
liveins: $vgpr0_vgpr1_vgpr2_vgpr3, $vgpr4, $vgpr5
|
||||
|
||||
; CHECK-LABEL: name: insert_vector_elt_var_v4i32_v_v_v
|
||||
; CHECK: [[COPY:%[0-9]+]]:vgpr(<4 x s32>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
|
||||
; CHECK: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr5
|
||||
; CHECK: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY $vgpr6
|
||||
; CHECK: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr4
|
||||
; CHECK: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY $vgpr5
|
||||
; CHECK: [[IVEC:%[0-9]+]]:vgpr(<4 x s32>) = G_INSERT_VECTOR_ELT [[COPY]], [[COPY1]](s32), [[COPY2]](s32)
|
||||
; CHECK: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[IVEC]](<4 x s32>)
|
||||
%0:_(<4 x s32>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
|
||||
%1:_(s32) = COPY $vgpr5
|
||||
%2:_(s32) = COPY $vgpr6
|
||||
%1:_(s32) = COPY $vgpr4
|
||||
%2:_(s32) = COPY $vgpr5
|
||||
%3:_(<4 x s32>) = G_INSERT_VECTOR_ELT %0, %1, %2
|
||||
$vgpr0_vgpr1_vgpr2_vgpr3 = COPY %3
|
||||
...
|
||||
|
|
|
|||
Loading…
Reference in New Issue