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Change MachineInstr ctor's to take a TargetInstrDescriptor reference instead 

of opcode and number of operands.

llvm-svn: 31947
This commit is contained in:
Evan Cheng 2006-11-27 23:37:22 +00:00
parent 5230e9175a
commit 20350c4025
36 changed files with 400 additions and 356 deletions
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16
llvm/include/llvm/CodeGen/MachineInstr.h
View File

@ -27,7 +27,6 @@ namespace llvm {
class Value;
class Function;
class MachineBasicBlock;
class TargetInstrInfo;
class TargetInstrDescriptor;
class TargetMachine;
class GlobalValue;
@ -296,7 +295,7 @@ public:
///
class MachineInstr {
short Opcode; // the opcode
short NumImplicitOps; // Number of implicit operands (which
unsigned short NumImplicitOps; // Number of implicit operands (which
// are determined at construction time).
std::vector<MachineOperand> Operands; // the operands
@ -314,19 +313,20 @@ class MachineInstr {
friend struct ilist_traits<MachineInstr>;
public:
/// MachineInstr ctor - This constructor reserves space for numOperand
/// operands.
MachineInstr(short Opcode, unsigned numOperands);
/// MachineInstr ctor - This constructor creates a dummy MachineInstr with
/// opcode 0 and no operands.
MachineInstr();
/// MachineInstr ctor - This constructor create a MachineInstr and add the
/// implicit operands. It reserves space for numOperand operands.
MachineInstr(const TargetInstrInfo &TII, short Opcode, unsigned numOperands);
/// implicit operands. It reserves space for number of operands specified by
/// TargetInstrDescriptor.
MachineInstr(const TargetInstrDescriptor &TID);
/// MachineInstr ctor - Work exactly the same as the ctor above, except that
/// the MachineInstr is created and added to the end of the specified basic
/// block.
///
MachineInstr(MachineBasicBlock *MBB, short Opcode, unsigned numOps);
MachineInstr(MachineBasicBlock *MBB, const TargetInstrDescriptor &TID);
~MachineInstr();

50
llvm/include/llvm/CodeGen/MachineInstrBuilder.h
View File

@ -19,10 +19,11 @@
#include "llvm/CodeGen/MachineBasicBlock.h"
#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/Target/TargetMachine.h"
namespace llvm {
class TargetInstrDescriptor;
class MachineInstrBuilder {
MachineInstr *MI;
public:
@ -83,36 +84,29 @@ public:
};
/// BuildMI - Builder interface. Specify how to create the initial instruction
/// itself. NumOperands is the number of operands to the machine instruction to
/// allow for memory efficient representation of machine instructions.
/// itself.
///
inline MachineInstrBuilder BuildMI(const TargetInstrInfo &TII, int Opcode,
unsigned NumOperands) {
return MachineInstrBuilder(new MachineInstr(TII, Opcode, NumOperands));
inline MachineInstrBuilder BuildMI(const TargetInstrDescriptor &TID) {
return MachineInstrBuilder(new MachineInstr(TID));
}
/// BuildMI - This version of the builder sets up the first operand as a
/// destination virtual register. NumOperands is the number of additional add*
/// calls that are expected, not including the destination register.
/// destination virtual register.
///
inline MachineInstrBuilder BuildMI(const TargetInstrInfo &TII, int Opcode,
unsigned NumOperands, unsigned DestReg) {
return MachineInstrBuilder(new MachineInstr(TII, Opcode, NumOperands+1))
.addReg(DestReg, true);
inline MachineInstrBuilder BuildMI(const TargetInstrDescriptor &TID,
unsigned DestReg) {
return MachineInstrBuilder(new MachineInstr(TID)).addReg(DestReg, true);
}
/// BuildMI - This version of the builder inserts the newly-built
/// instruction before the given position in the given MachineBasicBlock, and
/// sets up the first operand as a destination virtual register.
/// NumOperands is the number of additional add* calls that are expected,
/// not including the destination register.
///
inline MachineInstrBuilder BuildMI(MachineBasicBlock &BB,
MachineBasicBlock::iterator I,
int Opcode, unsigned NumOperands,
const TargetInstrDescriptor &TID,
unsigned DestReg) {
MachineInstr *MI = new MachineInstr(*BB.getParent()->getTarget().
getInstrInfo(), Opcode, NumOperands+1);
MachineInstr *MI = new MachineInstr(TID);
BB.insert(I, MI);
return MachineInstrBuilder(MI).addReg(DestReg, true);
}
@ -123,9 +117,8 @@ inline MachineInstrBuilder BuildMI(MachineBasicBlock &BB,
///
inline MachineInstrBuilder BuildMI(MachineBasicBlock &BB,
MachineBasicBlock::iterator I,
int Opcode, unsigned NumOperands) {
MachineInstr *MI = new MachineInstr(*BB.getParent()->getTarget().
getInstrInfo(), Opcode, NumOperands);
const TargetInstrDescriptor &TID) {
MachineInstr *MI = new MachineInstr(TID);
BB.insert(I, MI);
return MachineInstrBuilder(MI);
}
@ -134,20 +127,19 @@ inline MachineInstrBuilder BuildMI(MachineBasicBlock &BB,
/// instruction at the end of the given MachineBasicBlock, and does NOT take a
/// destination register.
///
inline MachineInstrBuilder BuildMI(MachineBasicBlock *BB, int Opcode,
unsigned NumOperands) {
return BuildMI(*BB, BB->end(), Opcode, NumOperands);
inline MachineInstrBuilder BuildMI(MachineBasicBlock *BB,
const TargetInstrDescriptor &TID) {
return BuildMI(*BB, BB->end(), TID);
}
/// BuildMI - This version of the builder inserts the newly-built
/// instruction at the end of the given MachineBasicBlock, and sets up the first
/// operand as a destination virtual register. NumOperands is the number of
/// additional add* calls that are expected, not including the destination
/// register.
/// operand as a destination virtual register.
///
inline MachineInstrBuilder BuildMI(MachineBasicBlock *BB, int Opcode,
unsigned NumOperands, unsigned DestReg) {
return BuildMI(*BB, BB->end(), Opcode, NumOperands, DestReg);
inline MachineInstrBuilder BuildMI(MachineBasicBlock *BB,
const TargetInstrDescriptor &TID,
unsigned DestReg) {
return BuildMI(*BB, BB->end(), TID, DestReg);
}
} // End llvm namespace

2
llvm/lib/CodeGen/MachineBasicBlock.cpp
View File

@ -52,7 +52,7 @@ void ilist_traits<MachineBasicBlock>::removeNodeFromList(MachineBasicBlock* N) {
MachineInstr* ilist_traits<MachineInstr>::createSentinel() {
MachineInstr* dummy = new MachineInstr(0, 0);
MachineInstr* dummy = new MachineInstr();
LeakDetector::removeGarbageObject(dummy);
return dummy;
}

34
llvm/lib/CodeGen/MachineInstr.cpp
View File

@ -32,14 +32,10 @@ namespace llvm {
extern const TargetInstrDescriptor *TargetInstrDescriptors;
}
/// MachineInstr ctor - This constructor only does a _reserve_ of the operands,
/// not a resize for them. It is expected that if you use this that you call
/// add* methods below to fill up the operands, instead of the Set methods.
/// Eventually, the "resizing" ctors will be phased out.
///
MachineInstr::MachineInstr(short opcode, unsigned numOperands)
: Opcode(opcode), NumImplicitOps(0), parent(0) {
Operands.reserve(numOperands);
/// MachineInstr ctor - This constructor creates a dummy MachineInstr with
/// opcode 0 and no operands.
MachineInstr::MachineInstr()
: Opcode(0), NumImplicitOps(0), parent(0) {
// Make sure that we get added to a machine basicblock
LeakDetector::addGarbageObject(this);
}
@ -72,18 +68,18 @@ void MachineInstr::addImplicitDefUseOperands(const TargetInstrDescriptor &TID) {
}
/// MachineInstr ctor - This constructor create a MachineInstr and add the
/// implicit operands. It reserves space for numOperand operands.
MachineInstr::MachineInstr(const TargetInstrInfo &TII, short opcode,
unsigned numOperands)
: Opcode(opcode), NumImplicitOps(0), parent(0) {
const TargetInstrDescriptor &TID = TII.get(opcode);
/// implicit operands. It reserves space for number of operands specified by
/// TargetInstrDescriptor or the numOperands if it is not zero. (for
/// instructions with variable number of operands).
MachineInstr::MachineInstr(const TargetInstrDescriptor &TID)
: Opcode(TID.Opcode), NumImplicitOps(0), parent(0) {
if (TID.ImplicitDefs)
for (const unsigned *ImpDefs = TID.ImplicitDefs; *ImpDefs; ++ImpDefs)
NumImplicitOps++;
if (TID.ImplicitUses)
for (const unsigned *ImpUses = TID.ImplicitUses; *ImpUses; ++ImpUses)
NumImplicitOps++;
Operands.reserve(NumImplicitOps + numOperands);
Operands.reserve(NumImplicitOps + TID.numOperands);
addImplicitDefUseOperands(TID);
// Make sure that we get added to a machine basicblock
LeakDetector::addGarbageObject(this);
@ -92,19 +88,17 @@ MachineInstr::MachineInstr(const TargetInstrInfo &TII, short opcode,
/// MachineInstr ctor - Work exactly the same as the ctor above, except that the
/// MachineInstr is created and added to the end of the specified basic block.
///
MachineInstr::MachineInstr(MachineBasicBlock *MBB, short opcode,
unsigned numOperands)
: Opcode(opcode), NumImplicitOps(0), parent(0) {
MachineInstr::MachineInstr(MachineBasicBlock *MBB,
const TargetInstrDescriptor &TID)
: Opcode(TID.Opcode), NumImplicitOps(0), parent(0) {
assert(MBB && "Cannot use inserting ctor with null basic block!");
const TargetInstrDescriptor &TID = MBB->getParent()->getTarget().
getInstrInfo()->get(opcode);
if (TID.ImplicitDefs)
for (const unsigned *ImpDefs = TID.ImplicitDefs; *ImpDefs; ++ImpDefs)
NumImplicitOps++;
if (TID.ImplicitUses)
for (const unsigned *ImpUses = TID.ImplicitUses; *ImpUses; ++ImpUses)
NumImplicitOps++;
Operands.reserve(NumImplicitOps + numOperands);
Operands.reserve(NumImplicitOps + TID.numOperands);
addImplicitDefUseOperands(TID);
// Make sure that we get added to a machine basicblock
LeakDetector::addGarbageObject(this);

4
llvm/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp
View File

@ -395,7 +395,7 @@ void ScheduleDAG::EmitNode(SDNode *Node,
#endif
// Create the new machine instruction.
MachineInstr *MI = new MachineInstr(*TII, Opc, NumMIOperands);
MachineInstr *MI = new MachineInstr(II);
// Add result register values for things that are defined by this
// instruction.
@ -518,7 +518,7 @@ void ScheduleDAG::EmitNode(SDNode *Node,
// Create the inline asm machine instruction.
MachineInstr *MI =
new MachineInstr(BB, TargetInstrInfo::INLINEASM, (NumOps-2)/2+1);
new MachineInstr(BB, TII->get(TargetInstrInfo::INLINEASM));
// Add the asm string as an external symbol operand.
const char *AsmStr =

3
llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
View File

@ -294,8 +294,9 @@ FunctionLoweringInfo::FunctionLoweringInfo(TargetLowering &tli,
}
unsigned PHIReg = ValueMap[PN];
assert(PHIReg && "PHI node does not have an assigned virtual register!");
const TargetInstrInfo *TII = TLI.getTargetMachine().getInstrInfo();
for (unsigned i = 0; i != NumElements; ++i)
BuildMI(MBB, TargetInstrInfo::PHI, PN->getNumOperands(), PHIReg+i);
BuildMI(MBB, TII->get(TargetInstrInfo::PHI), PHIReg+i);
}
}
}

5
llvm/lib/Target/ARM/ARMInstrInfo.cpp
View File

@ -19,7 +19,8 @@
using namespace llvm;
ARMInstrInfo::ARMInstrInfo()
: TargetInstrInfo(ARMInsts, sizeof(ARMInsts)/sizeof(ARMInsts[0])) {
: TargetInstrInfo(ARMInsts, sizeof(ARMInsts)/sizeof(ARMInsts[0])),
RI(*this) {
}
const TargetRegisterClass *ARMInstrInfo::getPointerRegClass() const {
@ -54,5 +55,5 @@ void ARMInstrInfo::InsertBranch(MachineBasicBlock &MBB,MachineBasicBlock *TBB,
const std::vector<MachineOperand> &Cond)const{
// Can only insert uncond branches so far.
assert(Cond.empty() && !FBB && TBB && "Can only handle uncond branches!");
BuildMI(&MBB, ARM::b, 1).addMBB(TBB);
BuildMI(&MBB, get(ARM::b)).addMBB(TBB);
}

6
llvm/lib/Target/ARM/ARMMul.cpp
View File

@ -16,6 +16,8 @@
#include "ARM.h"
#include "llvm/CodeGen/MachineInstrBuilder.h"
#include "llvm/CodeGen/MachineFunctionPass.h"
#include "llvm/Target/TargetMachine.h"
#include "llvm/Target/TargetInstrInfo.h"
#include "llvm/Support/Compiler.h"
using namespace llvm;
@ -60,8 +62,8 @@ bool FixMul::runOnMachineFunction(MachineFunction &MF) {
RsOp.setReg(Rm);
} else {
unsigned scratch = Op == ARM::MUL ? ARM::R12 : ARM::R0;
BuildMI(MBB, I, ARM::MOV, 3, scratch).addReg(Rm).addImm(0)
.addImm(ARMShift::LSL);
BuildMI(MBB, I, MF.getTarget().getInstrInfo()->get(ARM::MOV),
scratch).addReg(Rm).addImm(0).addImm(ARMShift::LSL);
RmOp.setReg(scratch);
}
}

34
llvm/lib/Target/ARM/ARMRegisterInfo.cpp
View File

@ -22,6 +22,7 @@
#include "llvm/Target/TargetFrameInfo.h"
#include "llvm/Target/TargetMachine.h"
#include "llvm/Target/TargetOptions.h"
#include "llvm/Target/TargetInstrInfo.h"
#include "llvm/ADT/STLExtras.h"
#include <iostream>
using namespace llvm;
@ -35,8 +36,9 @@ static bool hasFP(const MachineFunction &MF) {
return NoFramePointerElim || MFI->hasVarSizedObjects();
}
ARMRegisterInfo::ARMRegisterInfo()
: ARMGenRegisterInfo(ARM::ADJCALLSTACKDOWN, ARM::ADJCALLSTACKUP) {
ARMRegisterInfo::ARMRegisterInfo(const TargetInstrInfo &tii)
: ARMGenRegisterInfo(ARM::ADJCALLSTACKDOWN, ARM::ADJCALLSTACKUP),
TII(tii) {
}
void ARMRegisterInfo::
@ -44,7 +46,7 @@ storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
unsigned SrcReg, int FI,
const TargetRegisterClass *RC) const {
assert (RC == ARM::IntRegsRegisterClass);
BuildMI(MBB, I, ARM::STR, 3).addReg(SrcReg).addFrameIndex(FI).addImm(0);
BuildMI(MBB, I, TII.get(ARM::STR)).addReg(SrcReg).addFrameIndex(FI).addImm(0);
}
void ARMRegisterInfo::
@ -52,7 +54,7 @@ loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
unsigned DestReg, int FI,
const TargetRegisterClass *RC) const {
assert (RC == ARM::IntRegsRegisterClass);
BuildMI(MBB, I, ARM::LDR, 2, DestReg).addFrameIndex(FI).addImm(0);
BuildMI(MBB, I, TII.get(ARM::LDR), DestReg).addFrameIndex(FI).addImm(0);
}
void ARMRegisterInfo::copyRegToReg(MachineBasicBlock &MBB,
@ -64,12 +66,12 @@ void ARMRegisterInfo::copyRegToReg(MachineBasicBlock &MBB,
RC == ARM::DFPRegsRegisterClass);
if (RC == ARM::IntRegsRegisterClass)
BuildMI(MBB, I, ARM::MOV, 3, DestReg).addReg(SrcReg).addImm(0)
BuildMI(MBB, I, TII.get(ARM::MOV), DestReg).addReg(SrcReg).addImm(0)
.addImm(ARMShift::LSL);
else if (RC == ARM::FPRegsRegisterClass)
BuildMI(MBB, I, ARM::FCPYS, 1, DestReg).addReg(SrcReg);
BuildMI(MBB, I, TII.get(ARM::FCPYS), DestReg).addReg(SrcReg);
else
BuildMI(MBB, I, ARM::FCPYD, 1, DestReg).addReg(SrcReg);
BuildMI(MBB, I, TII.get(ARM::FCPYD), DestReg).addReg(SrcReg);
}
MachineInstr *ARMRegisterInfo::foldMemoryOperand(MachineInstr* MI,
@ -109,12 +111,12 @@ eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
if (Old->getOpcode() == ARM::ADJCALLSTACKDOWN) {
// sub sp, sp, amount
BuildMI(MBB, I, ARM::SUB, 2, ARM::R13).addReg(ARM::R13).addImm(Amount)
BuildMI(MBB, I, TII.get(ARM::SUB), ARM::R13).addReg(ARM::R13).addImm(Amount)
.addImm(0).addImm(ARMShift::LSL);
} else {
// add sp, sp, amount
assert(Old->getOpcode() == ARM::ADJCALLSTACKUP);
BuildMI(MBB, I, ARM::ADD, 2, ARM::R13).addReg(ARM::R13).addImm(Amount)
BuildMI(MBB, I, TII.get(ARM::ADD), ARM::R13).addReg(ARM::R13).addImm(Amount)
.addImm(0).addImm(ARMShift::LSL);
}
}
@ -155,7 +157,7 @@ ARMRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II) const {
// Insert a set of r12 with the full address
// r12 = r13 + offset
MachineBasicBlock *MBB2 = MI.getParent();
BuildMI(*MBB2, II, ARM::ADD, 4, ARM::R12).addReg(BaseRegister)
BuildMI(*MBB2, II, TII.get(ARM::ADD), ARM::R12).addReg(BaseRegister)
.addImm(Offset).addImm(0).addImm(ARMShift::LSL);
// Replace the FrameIndex with r12
@ -191,13 +193,13 @@ void ARMRegisterInfo::emitPrologue(MachineFunction &MF) const {
MFI->setStackSize(NumBytes);
//sub sp, sp, #NumBytes
BuildMI(MBB, MBBI, ARM::SUB, 4, ARM::R13).addReg(ARM::R13).addImm(NumBytes)
BuildMI(MBB, MBBI, TII.get(ARM::SUB), ARM::R13).addReg(ARM::R13).addImm(NumBytes)
.addImm(0).addImm(ARMShift::LSL);
if (HasFP) {
BuildMI(MBB, MBBI, ARM::STR, 3)
BuildMI(MBB, MBBI, TII.get(ARM::STR))
.addReg(ARM::R11).addReg(ARM::R13).addImm(0);
BuildMI(MBB, MBBI, ARM::MOV, 3, ARM::R11).addReg(ARM::R13).addImm(0).
BuildMI(MBB, MBBI, TII.get(ARM::MOV), ARM::R11).addReg(ARM::R13).addImm(0).
addImm(ARMShift::LSL);
}
}
@ -212,13 +214,13 @@ void ARMRegisterInfo::emitEpilogue(MachineFunction &MF,
int NumBytes = (int) MFI->getStackSize();
if (hasFP(MF)) {
BuildMI(MBB, MBBI, ARM::MOV, 3, ARM::R13).addReg(ARM::R11).addImm(0).
BuildMI(MBB, MBBI, TII.get(ARM::MOV), ARM::R13).addReg(ARM::R11).addImm(0).
addImm(ARMShift::LSL);
BuildMI(MBB, MBBI, ARM::LDR, 2, ARM::R11).addReg(ARM::R13).addImm(0);
BuildMI(MBB, MBBI, TII.get(ARM::LDR), ARM::R11).addReg(ARM::R13).addImm(0);
}
//add sp, sp, #NumBytes
BuildMI(MBB, MBBI, ARM::ADD, 4, ARM::R13).addReg(ARM::R13).addImm(NumBytes)
BuildMI(MBB, MBBI, TII.get(ARM::ADD), ARM::R13).addReg(ARM::R13).addImm(NumBytes)
.addImm(0).addImm(ARMShift::LSL);
}

4
llvm/lib/Target/ARM/ARMRegisterInfo.h
View File

@ -21,10 +21,12 @@
namespace llvm {
class Type;
class TargetInstrInfo;
struct ARMRegisterInfo : public ARMGenRegisterInfo {
const TargetInstrInfo &TII;
ARMRegisterInfo();
ARMRegisterInfo(const TargetInstrInfo &tii);
/// Code Generation virtual methods...
void storeRegToStackSlot(MachineBasicBlock &MBB,

14
llvm/lib/Target/Alpha/AlphaInstrInfo.cpp
View File

@ -110,25 +110,25 @@ void AlphaInstrInfo::InsertBranch(MachineBasicBlock &MBB,MachineBasicBlock *TBB,
// One-way branch.
if (FBB == 0) {
if (Cond.empty()) // Unconditional branch
BuildMI(&MBB, Alpha::BR, 1).addMBB(TBB);
BuildMI(&MBB, get(Alpha::BR)).addMBB(TBB);
else // Conditional branch
if (isAlphaIntCondCode(Cond[0].getImm()))
BuildMI(&MBB, Alpha::COND_BRANCH_I, 3)
BuildMI(&MBB, get(Alpha::COND_BRANCH_I))
.addImm(Cond[0].getImm()).addReg(Cond[1].getReg()).addMBB(TBB);
else
BuildMI(&MBB, Alpha::COND_BRANCH_F, 3)
BuildMI(&MBB, get(Alpha::COND_BRANCH_F))
.addImm(Cond[0].getImm()).addReg(Cond[1].getReg()).addMBB(TBB);
return;
}
// Two-way Conditional Branch.
if (isAlphaIntCondCode(Cond[0].getImm()))
BuildMI(&MBB, Alpha::COND_BRANCH_I, 3)
BuildMI(&MBB, get(Alpha::COND_BRANCH_I))
.addImm(Cond[0].getImm()).addReg(Cond[1].getReg()).addMBB(TBB);
else
BuildMI(&MBB, Alpha::COND_BRANCH_F, 3)
BuildMI(&MBB, get(Alpha::COND_BRANCH_F))
.addImm(Cond[0].getImm()).addReg(Cond[1].getReg()).addMBB(TBB);
BuildMI(&MBB, Alpha::BR, 1).addMBB(FBB);
BuildMI(&MBB, get(Alpha::BR)).addMBB(FBB);
}
static unsigned AlphaRevCondCode(unsigned Opcode) {
@ -230,7 +230,7 @@ void AlphaInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
void AlphaInstrInfo::insertNoop(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MI) const {
BuildMI(MBB, MI, Alpha::BISr, 2, Alpha::R31).addReg(Alpha::R31)
BuildMI(MBB, MI, get(Alpha::BISr), Alpha::R31).addReg(Alpha::R31)
.addReg(Alpha::R31);
}

17
llvm/lib/Target/Alpha/AlphaLLRP.cpp
View File

@ -15,6 +15,8 @@
#include "Alpha.h"
#include "llvm/CodeGen/MachineFunctionPass.h"
#include "llvm/CodeGen/MachineInstrBuilder.h"
#include "llvm/Target/TargetMachine.h"
#include "llvm/Target/TargetInstrInfo.h"
#include "llvm/ADT/SetOperations.h"
#include "llvm/ADT/Statistic.h"
#include "llvm/Support/CommandLine.h"
@ -42,6 +44,7 @@ namespace {
}
bool runOnMachineFunction(MachineFunction &F) {
const TargetInstrInfo *TII = F.getTarget().getInstrInfo();
bool Changed = false;
MachineInstr* prev[3] = {0,0,0};
unsigned count = 0;
@ -70,7 +73,7 @@ namespace {
prev[0] = prev[1];
prev[1] = prev[2];
prev[2] = 0;
BuildMI(MBB, MI, Alpha::BISr, 2, Alpha::R31).addReg(Alpha::R31)
BuildMI(MBB, MI, TII->get(Alpha::BISr), Alpha::R31).addReg(Alpha::R31)
.addReg(Alpha::R31);
Changed = true; nopintro += 1;
count += 1;
@ -81,9 +84,9 @@ namespace {
MI->getOperand(1).getImmedValue()) {
prev[0] = prev[2];
prev[1] = prev[2] = 0;
BuildMI(MBB, MI, Alpha::BISr, 2, Alpha::R31).addReg(Alpha::R31)
BuildMI(MBB, MI, TII->get(Alpha::BISr), Alpha::R31).addReg(Alpha::R31)
.addReg(Alpha::R31);
BuildMI(MBB, MI, Alpha::BISr, 2, Alpha::R31).addReg(Alpha::R31)
BuildMI(MBB, MI, TII->get(Alpha::BISr), Alpha::R31).addReg(Alpha::R31)
.addReg(Alpha::R31);
Changed = true; nopintro += 2;
count += 2;
@ -93,11 +96,11 @@ namespace {
&& prev[2]->getOperand(1).getImmedValue() ==
MI->getOperand(1).getImmedValue()) {
prev[0] = prev[1] = prev[2] = 0;
BuildMI(MBB, MI, Alpha::BISr, 2, Alpha::R31).addReg(Alpha::R31)
BuildMI(MBB, MI, TII->get(Alpha::BISr), Alpha::R31).addReg(Alpha::R31)
.addReg(Alpha::R31);
BuildMI(MBB, MI, Alpha::BISr, 2, Alpha::R31).addReg(Alpha::R31)
BuildMI(MBB, MI, TII->get(Alpha::BISr), Alpha::R31).addReg(Alpha::R31)
.addReg(Alpha::R31);
BuildMI(MBB, MI, Alpha::BISr, 2, Alpha::R31).addReg(Alpha::R31)
BuildMI(MBB, MI, TII->get(Alpha::BISr), Alpha::R31).addReg(Alpha::R31)
.addReg(Alpha::R31);
Changed = true; nopintro += 3;
count += 3;
@ -130,7 +133,7 @@ namespace {
if (ub || AlignAll) {
//we can align stuff for free at this point
while (count % 4) {
BuildMI(MBB, MBB.end(), Alpha::BISr, 2, Alpha::R31)
BuildMI(MBB, MBB.end(), TII->get(Alpha::BISr), Alpha::R31)
.addReg(Alpha::R31).addReg(Alpha::R31);
++count;
++nopalign;

55
llvm/lib/Target/Alpha/AlphaRegisterInfo.cpp
View File

@ -25,6 +25,7 @@
#include "llvm/Target/TargetFrameInfo.h"
#include "llvm/Target/TargetMachine.h"
#include "llvm/Target/TargetOptions.h"
#include "llvm/Target/TargetInstrInfo.h"
#include "llvm/Support/CommandLine.h"
#include "llvm/Support/Debug.h"
#include "llvm/ADT/STLExtras.h"
@ -66,13 +67,13 @@ AlphaRegisterInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
//<< FrameIdx << "\n";
//BuildMI(MBB, MI, Alpha::WTF, 0).addReg(SrcReg);
if (RC == Alpha::F4RCRegisterClass)
BuildMI(MBB, MI, Alpha::STS, 3)
BuildMI(MBB, MI, TII.get(Alpha::STS))
.addReg(SrcReg).addFrameIndex(FrameIdx).addReg(Alpha::F31);
else if (RC == Alpha::F8RCRegisterClass)
BuildMI(MBB, MI, Alpha::STT, 3)
BuildMI(MBB, MI, TII.get(Alpha::STT))
.addReg(SrcReg).addFrameIndex(FrameIdx).addReg(Alpha::F31);
else if (RC == Alpha::GPRCRegisterClass)
BuildMI(MBB, MI, Alpha::STQ, 3)
BuildMI(MBB, MI, TII.get(Alpha::STQ))
.addReg(SrcReg).addFrameIndex(FrameIdx).addReg(Alpha::F31);
else
abort();
@ -86,13 +87,13 @@ AlphaRegisterInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
//std::cerr << "Trying to load " << getPrettyName(DestReg) << " to "
//<< FrameIdx << "\n";
if (RC == Alpha::F4RCRegisterClass)
BuildMI(MBB, MI, Alpha::LDS, 2, DestReg)
BuildMI(MBB, MI, TII.get(Alpha::LDS), DestReg)
.addFrameIndex(FrameIdx).addReg(Alpha::F31);
else if (RC == Alpha::F8RCRegisterClass)
BuildMI(MBB, MI, Alpha::LDT, 2, DestReg)
BuildMI(MBB, MI, TII.get(Alpha::LDT), DestReg)
.addFrameIndex(FrameIdx).addReg(Alpha::F31);
else if (RC == Alpha::GPRCRegisterClass)
BuildMI(MBB, MI, Alpha::LDQ, 2, DestReg)
BuildMI(MBB, MI, TII.get(Alpha::LDQ), DestReg)
.addFrameIndex(FrameIdx).addReg(Alpha::F31);
else
abort();
@ -116,13 +117,13 @@ MachineInstr *AlphaRegisterInfo::foldMemoryOperand(MachineInstr *MI,
unsigned InReg = MI->getOperand(1).getReg();
Opc = (Opc == Alpha::BISr) ? Alpha::STQ :
((Opc == Alpha::CPYSS) ? Alpha::STS : Alpha::STT);
NewMI = BuildMI(TII, Opc, 3).addReg(InReg).addFrameIndex(FrameIndex)
NewMI = BuildMI(TII.get(Opc)).addReg(InReg).addFrameIndex(FrameIndex)
.addReg(Alpha::F31);
} else { // load -> move
unsigned OutReg = MI->getOperand(0).getReg();
Opc = (Opc == Alpha::BISr) ? Alpha::LDQ :
((Opc == Alpha::CPYSS) ? Alpha::LDS : Alpha::LDT);
NewMI = BuildMI(TII, Opc, 2, OutReg).addFrameIndex(FrameIndex)
NewMI = BuildMI(TII.get(Opc), OutReg).addFrameIndex(FrameIndex)
.addReg(Alpha::F31);
}
}
@ -140,11 +141,11 @@ void AlphaRegisterInfo::copyRegToReg(MachineBasicBlock &MBB,
const TargetRegisterClass *RC) const {
// std::cerr << "copyRegToReg " << DestReg << " <- " << SrcReg << "\n";
if (RC == Alpha::GPRCRegisterClass) {
BuildMI(MBB, MI, Alpha::BISr, 2, DestReg).addReg(SrcReg).addReg(SrcReg);
BuildMI(MBB, MI, TII.get(Alpha::BISr), DestReg).addReg(SrcReg).addReg(SrcReg);
} else if (RC == Alpha::F4RCRegisterClass) {
BuildMI(MBB, MI, Alpha::CPYSS, 2, DestReg).addReg(SrcReg).addReg(SrcReg);
BuildMI(MBB, MI, TII.get(Alpha::CPYSS), DestReg).addReg(SrcReg).addReg(SrcReg);
} else if (RC == Alpha::F8RCRegisterClass) {
BuildMI(MBB, MI, Alpha::CPYST, 2, DestReg).addReg(SrcReg).addReg(SrcReg);
BuildMI(MBB, MI, TII.get(Alpha::CPYST), DestReg).addReg(SrcReg).addReg(SrcReg);
} else {
std::cerr << "Attempt to copy register that is not GPR or FPR";
abort();
@ -209,11 +210,11 @@ eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
MachineInstr *New;
if (Old->getOpcode() == Alpha::ADJUSTSTACKDOWN) {
New=BuildMI(TII, Alpha::LDA, 2, Alpha::R30)
New=BuildMI(TII.get(Alpha::LDA), Alpha::R30)
.addImm(-Amount).addReg(Alpha::R30);
} else {
assert(Old->getOpcode() == Alpha::ADJUSTSTACKUP);
New=BuildMI(TII, Alpha::LDA, 2, Alpha::R30)
New=BuildMI(TII.get(Alpha::LDA), Alpha::R30)
.addImm(Amount).addReg(Alpha::R30);
}
@ -270,7 +271,7 @@ AlphaRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II) const {
MI.getOperand(i + 1).ChangeToRegister(Alpha::R28, false);
MI.getOperand(i).ChangeToImmediate(getLower16(Offset));
//insert the new
MachineInstr* nMI=BuildMI(TII, Alpha::LDAH, 2, Alpha::R28)
MachineInstr* nMI=BuildMI(TII.get(Alpha::LDAH), Alpha::R28)
.addImm(getUpper16(Offset)).addReg(FP ? Alpha::R15 : Alpha::R30);
MBB.insert(II, nMI);
} else {
@ -288,15 +289,15 @@ void AlphaRegisterInfo::emitPrologue(MachineFunction &MF) const {
static int curgpdist = 0;
//handle GOP offset
BuildMI(MBB, MBBI, Alpha::LDAHg, 3, Alpha::R29)
BuildMI(MBB, MBBI, TII.get(Alpha::LDAHg), Alpha::R29)
.addGlobalAddress(const_cast<Function*>(MF.getFunction()))
.addReg(Alpha::R27).addImm(++curgpdist);
BuildMI(MBB, MBBI, Alpha::LDAg, 3, Alpha::R29)
BuildMI(MBB, MBBI, TII.get(Alpha::LDAg), Alpha::R29)
.addGlobalAddress(const_cast<Function*>(MF.getFunction()))
.addReg(Alpha::R29).addImm(curgpdist);
//evil const_cast until MO stuff setup to handle const
BuildMI(MBB, MBBI, Alpha::ALTENT, 1)
BuildMI(MBB, MBBI, TII.get(Alpha::ALTENT))
.addGlobalAddress(const_cast<Function*>(MF.getFunction()));
// Get the number of bytes to allocate from the FrameInfo
@ -327,12 +328,12 @@ void AlphaRegisterInfo::emitPrologue(MachineFunction &MF) const {
// adjust stack pointer: r30 -= numbytes
NumBytes = -NumBytes;
if (NumBytes >= IMM_LOW) {
BuildMI(MBB, MBBI, Alpha::LDA, 2, Alpha::R30).addImm(NumBytes)
BuildMI(MBB, MBBI, TII.get(Alpha::LDA), Alpha::R30).addImm(NumBytes)
.addReg(Alpha::R30);
} else if (getUpper16(NumBytes) >= IMM_LOW) {
BuildMI(MBB, MBBI, Alpha::LDAH, 2, Alpha::R30).addImm(getUpper16(NumBytes))
BuildMI(MBB, MBBI, TII.get(Alpha::LDAH), Alpha::R30).addImm(getUpper16(NumBytes))
.addReg(Alpha::R30);
BuildMI(MBB, MBBI, Alpha::LDA, 2, Alpha::R30).addImm(getLower16(NumBytes))
BuildMI(MBB, MBBI, TII.get(Alpha::LDA), Alpha::R30).addImm(getLower16(NumBytes))
.addReg(Alpha::R30);
} else {
std::cerr << "Too big a stack frame at " << NumBytes << "\n";
@ -342,10 +343,10 @@ void AlphaRegisterInfo::emitPrologue(MachineFunction &MF) const {
//now if we need to, save the old FP and set the new
if (FP)
{
BuildMI(MBB, MBBI, Alpha::STQ, 3)
BuildMI(MBB, MBBI, TII.get(Alpha::STQ))
.addReg(Alpha::R15).addImm(0).addReg(Alpha::R30);
//this must be the last instr in the prolog
BuildMI(MBB, MBBI, Alpha::BISr, 2, Alpha::R15)
BuildMI(MBB, MBBI, TII.get(Alpha::BISr), Alpha::R15)
.addReg(Alpha::R30).addReg(Alpha::R30);
}
@ -368,21 +369,21 @@ void AlphaRegisterInfo::emitEpilogue(MachineFunction &MF,
if (FP)
{
//copy the FP into the SP (discards allocas)
BuildMI(MBB, MBBI, Alpha::BISr, 2, Alpha::R30).addReg(Alpha::R15)
BuildMI(MBB, MBBI, TII.get(Alpha::BISr), Alpha::R30).addReg(Alpha::R15)
.addReg(Alpha::R15);
//restore the FP
BuildMI(MBB, MBBI, Alpha::LDQ, 2, Alpha::R15).addImm(0).addReg(Alpha::R15);
BuildMI(MBB, MBBI, TII.get(Alpha::LDQ), Alpha::R15).addImm(0).addReg(Alpha::R15);
}
if (NumBytes != 0)
{
if (NumBytes <= IMM_HIGH) {
BuildMI(MBB, MBBI, Alpha::LDA, 2, Alpha::R30).addImm(NumBytes)
BuildMI(MBB, MBBI, TII.get(Alpha::LDA), Alpha::R30).addImm(NumBytes)
.addReg(Alpha::R30);
} else if (getUpper16(NumBytes) <= IMM_HIGH) {
BuildMI(MBB, MBBI, Alpha::LDAH, 2, Alpha::R30)
BuildMI(MBB, MBBI, TII.get(Alpha::LDAH), Alpha::R30)
.addImm(getUpper16(NumBytes)).addReg(Alpha::R30);
BuildMI(MBB, MBBI, Alpha::LDA, 2, Alpha::R30)
BuildMI(MBB, MBBI, TII.get(Alpha::LDA), Alpha::R30)
.addImm(getLower16(NumBytes)).addReg(Alpha::R30);
} else {
std::cerr << "Too big a stack frame at " << NumBytes << "\n";

1
llvm/lib/Target/Alpha/AlphaRegisterInfo.h
View File

@ -19,6 +19,7 @@
namespace llvm {
class TargetInstrInfo;
class Type;
struct AlphaRegisterInfo : public AlphaGenRegisterInfo {

5
llvm/lib/Target/IA64/IA64Bundling.cpp
View File

@ -21,6 +21,8 @@
//===----------------------------------------------------------------------===//
#include "IA64.h"
#include "IA64InstrInfo.h"
#include "IA64TargetMachine.h"
#include "llvm/CodeGen/MachineFunctionPass.h"
#include "llvm/CodeGen/MachineInstrBuilder.h"
#include "llvm/ADT/SetOperations.h"
@ -99,7 +101,8 @@ bool IA64BundlingPass::runOnMachineBasicBlock(MachineBasicBlock &MBB) {
if(! (CurrentReads.empty() && CurrentWrites.empty()) ) {
// there is a conflict, insert a stop and reset PendingRegWrites
CurrentInsn = BuildMI(MBB, CurrentInsn, IA64::STOP, 0);
CurrentInsn = BuildMI(MBB, CurrentInsn,
TM.getInstrInfo()->get(IA64::STOP), 0);
PendingRegWrites=OrigWrites; // carry over current writes to next insn
Changed=true; StopBitsAdded++; // update stats
} else { // otherwise, track additional pending writes

9
llvm/lib/Target/IA64/IA64ISelLowering.cpp
View File

@ -139,6 +139,7 @@ IA64TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) {
//
MachineFunction &MF = DAG.getMachineFunction();
MachineFrameInfo *MFI = MF.getFrameInfo();
const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
GP = MF.getSSARegMap()->createVirtualRegister(getRegClassFor(MVT::i64));
SP = MF.getSSARegMap()->createVirtualRegister(getRegClassFor(MVT::i64));
@ -225,7 +226,7 @@ IA64TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) {
// Create a vreg to hold the output of (what will become)
// the "alloc" instruction
VirtGPR = MF.getSSARegMap()->createVirtualRegister(getRegClassFor(MVT::i64));
BuildMI(&BB, IA64::PSEUDO_ALLOC, 0, VirtGPR);
BuildMI(&BB, TII->get(IA64::PSEUDO_ALLOC), VirtGPR);
// we create a PSEUDO_ALLOC (pseudo)instruction for now
/*
BuildMI(&BB, IA64::IDEF, 0, IA64::r1);
@ -255,14 +256,14 @@ IA64TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) {
// here we actually do the moving of args, and store them to the stack
// too if this is a varargs function:
for (int i = 0; i < count && i < 8; ++i) {
BuildMI(&BB, argOpc[i], 1, argVreg[i]).addReg(argPreg[i]);
BuildMI(&BB, TII->get(argOpc[i]), argVreg[i]).addReg(argPreg[i]);
if(F.isVarArg()) {
// if this is a varargs function, we copy the input registers to the stack
int FI = MFI->CreateFixedObject(8, tempOffset);
tempOffset+=8; //XXX: is it safe to use r22 like this?
BuildMI(&BB, IA64::MOV, 1, IA64::r22).addFrameIndex(FI);
BuildMI(&BB, TII->get(IA64::MOV), IA64::r22).addFrameIndex(FI);
// FIXME: we should use st8.spill here, one day
BuildMI(&BB, IA64::ST8, 1, IA64::r22).addReg(argPreg[i]);
BuildMI(&BB, TII->get(IA64::ST8), IA64::r22).addReg(argPreg[i]);
}
}

5
llvm/lib/Target/IA64/IA64InstrInfo.cpp
View File

@ -19,7 +19,8 @@
using namespace llvm;
IA64InstrInfo::IA64InstrInfo()
: TargetInstrInfo(IA64Insts, sizeof(IA64Insts)/sizeof(IA64Insts[0])) {
: TargetInstrInfo(IA64Insts, sizeof(IA64Insts)/sizeof(IA64Insts[0])),
RI(*this) {
}
@ -51,5 +52,5 @@ void IA64InstrInfo::InsertBranch(MachineBasicBlock &MBB,MachineBasicBlock *TBB,
const std::vector<MachineOperand> &Cond)const {
// Can only insert uncond branches so far.
assert(Cond.empty() && !FBB && TBB && "Can only handle uncond branches!");
BuildMI(&MBB, IA64::BRL_NOTCALL, 1).addMBB(TBB);
BuildMI(&MBB, get(IA64::BRL_NOTCALL)).addMBB(TBB);
}

64
llvm/lib/Target/IA64/IA64RegisterInfo.cpp
View File

@ -26,14 +26,16 @@
#include "llvm/Target/TargetFrameInfo.h"
#include "llvm/Target/TargetMachine.h"
#include "llvm/Target/TargetOptions.h"
#include "llvm/Target/TargetInstrInfo.h"
#include "llvm/Support/CommandLine.h"
#include "llvm/ADT/STLExtras.h"
#include <iostream>
using namespace llvm;
IA64RegisterInfo::IA64RegisterInfo()
: IA64GenRegisterInfo(IA64::ADJUSTCALLSTACKDOWN, IA64::ADJUSTCALLSTACKUP) {}
IA64RegisterInfo::IA64RegisterInfo(const TargetInstrInfo &tii)
: IA64GenRegisterInfo(IA64::ADJUSTCALLSTACKDOWN, IA64::ADJUSTCALLSTACKUP),
TII(tii) {}
void IA64RegisterInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MI,
@ -41,19 +43,19 @@ void IA64RegisterInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
const TargetRegisterClass *RC) const{
if (RC == IA64::FPRegisterClass) {
BuildMI(MBB, MI, IA64::STF_SPILL, 2).addFrameIndex(FrameIdx).addReg(SrcReg);
BuildMI(MBB, MI, TII.get(IA64::STF_SPILL)).addFrameIndex(FrameIdx).addReg(SrcReg);
} else if (RC == IA64::GRRegisterClass) {
BuildMI(MBB, MI, IA64::ST8, 2).addFrameIndex(FrameIdx).addReg(SrcReg);
BuildMI(MBB, MI, TII.get(IA64::ST8)).addFrameIndex(FrameIdx).addReg(SrcReg);
}
else if (RC == IA64::PRRegisterClass) {
/* we use IA64::r2 as a temporary register for doing this hackery. */
// first we load 0:
BuildMI(MBB, MI, IA64::MOV, 1, IA64::r2).addReg(IA64::r0);
BuildMI(MBB, MI, TII.get(IA64::MOV), IA64::r2).addReg(IA64::r0);
// then conditionally add 1:
BuildMI(MBB, MI, IA64::CADDIMM22, 3, IA64::r2).addReg(IA64::r2)
BuildMI(MBB, MI, TII.get(IA64::CADDIMM22), IA64::r2).addReg(IA64::r2)
.addImm(1).addReg(SrcReg);
// and then store it to the stack
BuildMI(MBB, MI, IA64::ST8, 2).addFrameIndex(FrameIdx).addReg(IA64::r2);
BuildMI(MBB, MI, TII.get(IA64::ST8)).addFrameIndex(FrameIdx).addReg(IA64::r2);
} else assert(0 &&
"sorry, I don't know how to store this sort of reg in the stack\n");
}
@ -64,16 +66,16 @@ void IA64RegisterInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
const TargetRegisterClass *RC)const{
if (RC == IA64::FPRegisterClass) {
BuildMI(MBB, MI, IA64::LDF_FILL, 1, DestReg).addFrameIndex(FrameIdx);
BuildMI(MBB, MI, TII.get(IA64::LDF_FILL), DestReg).addFrameIndex(FrameIdx);
} else if (RC == IA64::GRRegisterClass) {
BuildMI(MBB, MI, IA64::LD8, 1, DestReg).addFrameIndex(FrameIdx);
BuildMI(MBB, MI, TII.get(IA64::LD8), DestReg).addFrameIndex(FrameIdx);
} else if (RC == IA64::PRRegisterClass) {
// first we load a byte from the stack into r2, our 'predicate hackery'
// scratch reg
BuildMI(MBB, MI, IA64::LD8, 1, IA64::r2).addFrameIndex(FrameIdx);
BuildMI(MBB, MI, TII.get(IA64::LD8), IA64::r2).addFrameIndex(FrameIdx);
// then we compare it to zero. If it _is_ zero, compare-not-equal to
// r0 gives us 0, which is what we want, so that's nice.
BuildMI(MBB, MI, IA64::CMPNE, 2, DestReg).addReg(IA64::r2).addReg(IA64::r0);
BuildMI(MBB, MI, TII.get(IA64::CMPNE), DestReg).addReg(IA64::r2).addReg(IA64::r0);
} else assert(0 &&
"sorry, I don't know how to load this sort of reg from the stack\n");
}
@ -85,10 +87,10 @@ void IA64RegisterInfo::copyRegToReg(MachineBasicBlock &MBB,
if(RC == IA64::PRRegisterClass ) // if a bool, we use pseudocode
// (SrcReg) DestReg = cmp.eq.unc(r0, r0)
BuildMI(MBB, MI, IA64::PCMPEQUNC, 3, DestReg)
BuildMI(MBB, MI, TII.get(IA64::PCMPEQUNC), DestReg)
.addReg(IA64::r0).addReg(IA64::r0).addReg(SrcReg);
else // otherwise, MOV works (for both gen. regs and FP regs)
BuildMI(MBB, MI, IA64::MOV, 1, DestReg).addReg(SrcReg);
BuildMI(MBB, MI, TII.get(IA64::MOV), DestReg).addReg(SrcReg);
}
const unsigned* IA64RegisterInfo::getCalleeSaveRegs() const {
@ -121,7 +123,6 @@ static bool hasFP(const MachineFunction &MF) {
void IA64RegisterInfo::
eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
MachineBasicBlock::iterator I) const {
const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo();
if (hasFP(MF)) {
// If we have a frame pointer, turn the adjcallstackup instruction into a
// 'sub SP, <amt>' and the adjcallstackdown instruction into 'add SP,
@ -137,11 +138,11 @@ eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
MachineInstr *New;
if (Old->getOpcode() == IA64::ADJUSTCALLSTACKDOWN) {
New=BuildMI(TII, IA64::ADDIMM22, 2, IA64::r12).addReg(IA64::r12)
New=BuildMI(TII.get(IA64::ADDIMM22), IA64::r12).addReg(IA64::r12)
.addImm(-Amount);
} else {
assert(Old->getOpcode() == IA64::ADJUSTCALLSTACKUP);
New=BuildMI(TII, IA64::ADDIMM22, 2, IA64::r12).addReg(IA64::r12)
New=BuildMI(TII.get(IA64::ADDIMM22), IA64::r12).addReg(IA64::r12)
.addImm(Amount);
}
@ -158,7 +159,6 @@ void IA64RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II)const{
MachineInstr &MI = *II;
MachineBasicBlock &MBB = *MI.getParent();
MachineFunction &MF = *MBB.getParent();
const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo();
bool FP = hasFP(MF);
@ -187,16 +187,16 @@ void IA64RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II)const{
// Fix up the old:
MI.getOperand(i).ChangeToRegister(IA64::r22, false);
//insert the new
MachineInstr* nMI=BuildMI(TII, IA64::ADDIMM22, 2, IA64::r22)
MachineInstr* nMI=BuildMI(TII.get(IA64::ADDIMM22), IA64::r22)
.addReg(BaseRegister).addImm(Offset);
MBB.insert(II, nMI);
} else { // it's big
//fix up the old:
MI.getOperand(i).ChangeToRegister(IA64::r22, false);
MachineInstr* nMI;
nMI=BuildMI(TII, IA64::MOVLIMM64, 1, IA64::r22).addImm(Offset);
nMI=BuildMI(TII.get(IA64::MOVLIMM64), IA64::r22).addImm(Offset);
MBB.insert(II, nMI);
nMI=BuildMI(TII, IA64::ADD, 2, IA64::r22).addReg(BaseRegister)
nMI=BuildMI(TII.get(IA64::ADD), IA64::r22).addReg(BaseRegister)
.addReg(IA64::r22);
MBB.insert(II, nMI);
}
@ -207,7 +207,6 @@ void IA64RegisterInfo::emitPrologue(MachineFunction &MF) const {
MachineBasicBlock &MBB = MF.front(); // Prolog goes in entry BB
MachineBasicBlock::iterator MBBI = MBB.begin();
MachineFrameInfo *MFI = MF.getFrameInfo();
const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo();
MachineInstr *MI;
bool FP = hasFP(MF);
@ -252,7 +251,7 @@ void IA64RegisterInfo::emitPrologue(MachineFunction &MF) const {
}
}
MI=BuildMI(TII, IA64::ALLOC,5).addReg(dstRegOfPseudoAlloc).addImm(0). \
MI=BuildMI(TII.get(IA64::ALLOC)).addReg(dstRegOfPseudoAlloc).addImm(0). \
addImm(numStackedGPRsUsed).addImm(numOutRegsUsed).addImm(0);
MBB.insert(MBBI, MI);
@ -284,23 +283,23 @@ void IA64RegisterInfo::emitPrologue(MachineFunction &MF) const {
// adjust stack pointer: r12 -= numbytes
if (NumBytes <= 8191) {
MI=BuildMI(TII, IA64::ADDIMM22,2,IA64::r12).addReg(IA64::r12).
MI=BuildMI(TII.get(IA64::ADDIMM22),IA64::r12).addReg(IA64::r12).
addImm(-NumBytes);
MBB.insert(MBBI, MI);
} else { // we use r22 as a scratch register here
MI=BuildMI(TII, IA64::MOVLIMM64, 1, IA64::r22).addImm(-NumBytes);
MI=BuildMI(TII.get(IA64::MOVLIMM64), IA64::r22).addImm(-NumBytes);
// FIXME: MOVLSI32 expects a _u_32imm
MBB.insert(MBBI, MI); // first load the decrement into r22
MI=BuildMI(TII,IA64::ADD, 2, IA64::r12).addReg(IA64::r12).addReg(IA64::r22);
MI=BuildMI(TII.get(IA64::ADD), IA64::r12).addReg(IA64::r12).addReg(IA64::r22);
MBB.insert(MBBI, MI); // then add (subtract) it to r12 (stack ptr)
}
// now if we need to, save the old FP and set the new
if (FP) {
MI = BuildMI(TII, IA64::ST8, 2).addReg(IA64::r12).addReg(IA64::r5);
MI = BuildMI(TII.get(IA64::ST8)).addReg(IA64::r12).addReg(IA64::r5);
MBB.insert(MBBI, MI);
// this must be the last instr in the prolog ? (XXX: why??)
MI = BuildMI(TII, IA64::MOV, 1, IA64::r5).addReg(IA64::r12);
MI = BuildMI(TII.get(IA64::MOV), IA64::r5).addReg(IA64::r12);
MBB.insert(MBBI, MI);
}
@ -309,7 +308,6 @@ void IA64RegisterInfo::emitPrologue(MachineFunction &MF) const {
void IA64RegisterInfo::emitEpilogue(MachineFunction &MF,
MachineBasicBlock &MBB) const {
const MachineFrameInfo *MFI = MF.getFrameInfo();
const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo();
MachineBasicBlock::iterator MBBI = prior(MBB.end());
MachineInstr *MI;
assert(MBBI->getOpcode() == IA64::RET &&
@ -324,23 +322,23 @@ void IA64RegisterInfo::emitEpilogue(MachineFunction &MF,
if (FP)
{
//copy the FP into the SP (discards allocas)
MI=BuildMI(TII, IA64::MOV, 1, IA64::r12).addReg(IA64::r5);
MI=BuildMI(TII.get(IA64::MOV), IA64::r12).addReg(IA64::r5);
MBB.insert(MBBI, MI);
//restore the FP
MI=BuildMI(TII, IA64::LD8, 1, IA64::r5).addReg(IA64::r5);
MI=BuildMI(TII.get(IA64::LD8), IA64::r5).addReg(IA64::r5);
MBB.insert(MBBI, MI);
}
if (NumBytes != 0)
{
if (NumBytes <= 8191) {
MI=BuildMI(TII, IA64::ADDIMM22,2,IA64::r12).addReg(IA64::r12).
MI=BuildMI(TII.get(IA64::ADDIMM22),IA64::r12).addReg(IA64::r12).
addImm(NumBytes);
MBB.insert(MBBI, MI);
} else {
MI=BuildMI(TII, IA64::MOVLIMM64, 1, IA64::r22).addImm(NumBytes);
MI=BuildMI(TII.get(IA64::MOVLIMM64), IA64::r22).addImm(NumBytes);
MBB.insert(MBBI, MI);
MI=BuildMI(TII, IA64::ADD, 2, IA64::r12).addReg(IA64::r12).
MI=BuildMI(TII.get(IA64::ADD), IA64::r12).addReg(IA64::r12).
addReg(IA64::r22);
MBB.insert(MBBI, MI);
}

6
llvm/lib/Target/IA64/IA64RegisterInfo.h
View File

@ -21,8 +21,12 @@ namespace llvm { class llvm::Type; }
namespace llvm {
class TargetInstrInfo;
struct IA64RegisterInfo : public IA64GenRegisterInfo {
IA64RegisterInfo();
const TargetInstrInfo &TII;
IA64RegisterInfo(const TargetInstrInfo &tii);
/// Code Generation virtual methods...
void storeRegToStackSlot(MachineBasicBlock &MBB,

5
llvm/lib/Target/PowerPC/PPCBranchSelector.cpp
View File

@ -73,6 +73,7 @@ static unsigned getNumBytesForInstruction(MachineInstr *MI) {
bool PPCBSel::runOnMachineFunction(MachineFunction &Fn) {
const TargetInstrInfo *TII = Fn.getTarget().getInstrInfo();
// Give the blocks of the function a dense, in-order, numbering.
Fn.RenumberBlocks();
BlockSizes.resize(Fn.getNumBlockIDs());
@ -165,11 +166,11 @@ bool PPCBSel::runOnMachineFunction(MachineFunction &Fn) {
MachineInstr *OldBranch = I;
// Jump over the uncond branch inst (i.e. $PC+8) on opposite condition.
BuildMI(MBB, I, PPC::BCC, 3)
BuildMI(MBB, I, TII->get(PPC::BCC))
.addImm(PPC::InvertPredicate(Pred)).addReg(CRReg).addImm(2);
// Uncond branch to the real destination.
I = BuildMI(MBB, I, PPC::B, 1).addMBB(Dest);
I = BuildMI(MBB, I, TII->get(PPC::B)).addMBB(Dest);
// Remove the old branch from the function.
OldBranch->eraseFromParent();

19
llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
View File

@ -250,18 +250,18 @@ void PPCDAGToDAGISel::InsertVRSaveCode(Function &F) {
unsigned InVRSAVE = RegMap->createVirtualRegister(&PPC::GPRCRegClass);
unsigned UpdatedVRSAVE = RegMap->createVirtualRegister(&PPC::GPRCRegClass);
const TargetInstrInfo &TII = *TM.getInstrInfo();
MachineBasicBlock &EntryBB = *Fn.begin();
// Emit the following code into the entry block:
// InVRSAVE = MFVRSAVE
// UpdatedVRSAVE = UPDATE_VRSAVE InVRSAVE
// MTVRSAVE UpdatedVRSAVE
MachineBasicBlock::iterator IP = EntryBB.begin(); // Insert Point
BuildMI(EntryBB, IP, PPC::MFVRSAVE, 0, InVRSAVE);
BuildMI(EntryBB, IP, PPC::UPDATE_VRSAVE, 1, UpdatedVRSAVE).addReg(InVRSAVE);
BuildMI(EntryBB, IP, PPC::MTVRSAVE, 1).addReg(UpdatedVRSAVE);
BuildMI(EntryBB, IP, TII.get(PPC::MFVRSAVE), InVRSAVE);
BuildMI(EntryBB, IP, TII.get(PPC::UPDATE_VRSAVE), UpdatedVRSAVE).addReg(InVRSAVE);
BuildMI(EntryBB, IP, TII.get(PPC::MTVRSAVE)).addReg(UpdatedVRSAVE);
// Find all return blocks, outputting a restore in each epilog.
const TargetInstrInfo &TII = *TM.getInstrInfo();
for (MachineFunction::iterator BB = Fn.begin(), E = Fn.end(); BB != E; ++BB) {
if (!BB->empty() && TII.isReturn(BB->back().getOpcode())) {
IP = BB->end(); --IP;
@ -273,7 +273,7 @@ void PPCDAGToDAGISel::InsertVRSaveCode(Function &F) {
IP = I2;
// Emit: MTVRSAVE InVRSave
BuildMI(*BB, IP, PPC::MTVRSAVE, 1).addReg(InVRSAVE);
BuildMI(*BB, IP, TII.get(PPC::MTVRSAVE)).addReg(InVRSAVE);
}
}
}
@ -284,6 +284,7 @@ void PPCDAGToDAGISel::InsertVRSaveCode(Function &F) {
///
SDNode *PPCDAGToDAGISel::getGlobalBaseReg() {
if (!GlobalBaseReg) {
const TargetInstrInfo &TII = *TM.getInstrInfo();
// Insert the set of GlobalBaseReg into the first MBB of the function
MachineBasicBlock &FirstMBB = BB->getParent()->front();
MachineBasicBlock::iterator MBBI = FirstMBB.begin();
@ -291,12 +292,12 @@ SDNode *PPCDAGToDAGISel::getGlobalBaseReg() {
if (PPCLowering.getPointerTy() == MVT::i32) {
GlobalBaseReg = RegMap->createVirtualRegister(PPC::GPRCRegisterClass);
BuildMI(FirstMBB, MBBI, PPC::MovePCtoLR, 0, PPC::LR);
BuildMI(FirstMBB, MBBI, PPC::MFLR, 1, GlobalBaseReg);
BuildMI(FirstMBB, MBBI, TII.get(PPC::MovePCtoLR), PPC::LR);
BuildMI(FirstMBB, MBBI, TII.get(PPC::MFLR), GlobalBaseReg);
} else {
GlobalBaseReg = RegMap->createVirtualRegister(PPC::G8RCRegisterClass);
BuildMI(FirstMBB, MBBI, PPC::MovePCtoLR8, 0, PPC::LR8);
BuildMI(FirstMBB, MBBI, PPC::MFLR8, 1, GlobalBaseReg);
BuildMI(FirstMBB, MBBI, TII.get(PPC::MovePCtoLR8), PPC::LR8);
BuildMI(FirstMBB, MBBI, TII.get(PPC::MFLR8), GlobalBaseReg);
}
}
return CurDAG->getRegister(GlobalBaseReg, PPCLowering.getPointerTy()).Val;

5
llvm/lib/Target/PowerPC/PPCISelLowering.cpp
View File

@ -2593,6 +2593,7 @@ SDOperand PPCTargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) {
MachineBasicBlock *
PPCTargetLowering::InsertAtEndOfBasicBlock(MachineInstr *MI,
MachineBasicBlock *BB) {
const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
assert((MI->getOpcode() == PPC::SELECT_CC_I4 ||
MI->getOpcode() == PPC::SELECT_CC_I8 ||
MI->getOpcode() == PPC::SELECT_CC_F4 ||
@ -2618,7 +2619,7 @@ PPCTargetLowering::InsertAtEndOfBasicBlock(MachineInstr *MI,
MachineBasicBlock *copy0MBB = new MachineBasicBlock(LLVM_BB);
MachineBasicBlock *sinkMBB = new MachineBasicBlock(LLVM_BB);
unsigned SelectPred = MI->getOperand(4).getImm();
BuildMI(BB, PPC::BCC, 3)
BuildMI(BB, TII->get(PPC::BCC))
.addImm(SelectPred).addReg(MI->getOperand(1).getReg()).addMBB(sinkMBB);
MachineFunction *F = BB->getParent();
F->getBasicBlockList().insert(It, copy0MBB);
@ -2647,7 +2648,7 @@ PPCTargetLowering::InsertAtEndOfBasicBlock(MachineInstr *MI,
// %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
// ...
BB = sinkMBB;
BuildMI(BB, PPC::PHI, 4, MI->getOperand(0).getReg())
BuildMI(BB, TII->get(PPC::PHI), MI->getOperand(0).getReg())
.addReg(MI->getOperand(3).getReg()).addMBB(copy0MBB)
.addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);

10
llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
View File

@ -171,7 +171,7 @@ MachineInstr *PPCInstrInfo::commuteInstruction(MachineInstr *MI) const {
void PPCInstrInfo::insertNoop(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MI) const {
BuildMI(MBB, MI, PPC::NOP, 0);
BuildMI(MBB, MI, get(PPC::NOP));
}
@ -257,17 +257,17 @@ void PPCInstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
// One-way branch.
if (FBB == 0) {
if (Cond.empty()) // Unconditional branch
BuildMI(&MBB, PPC::B, 1).addMBB(TBB);
BuildMI(&MBB, get(PPC::B)).addMBB(TBB);
else // Conditional branch
BuildMI(&MBB, PPC::BCC, 3)
BuildMI(&MBB, get(PPC::BCC))
.addImm(Cond[0].getImm()).addReg(Cond[1].getReg()).addMBB(TBB);
return;
}
// Two-way Conditional Branch.
BuildMI(&MBB, PPC::BCC, 3)
BuildMI(&MBB, get(PPC::BCC))
.addImm(Cond[0].getImm()).addReg(Cond[1].getReg()).addMBB(TBB);
BuildMI(&MBB, PPC::B, 1).addMBB(FBB);
BuildMI(&MBB, get(PPC::B)).addMBB(FBB);
}
bool PPCInstrInfo::BlockHasNoFallThrough(MachineBasicBlock &MBB) const {

179
llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
View File

@ -103,54 +103,60 @@ PPCRegisterInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
const TargetRegisterClass *RC) const {
if (RC == PPC::GPRCRegisterClass) {
if (SrcReg != PPC::LR) {
addFrameReference(BuildMI(MBB, MI, PPC::STW, 3).addReg(SrcReg),FrameIdx);
addFrameReference(BuildMI(MBB, MI, TII.get(PPC::STW)).addReg(SrcReg),
FrameIdx);
} else {
// FIXME: this spills LR immediately to memory in one step. To do this,
// we use R11, which we know cannot be used in the prolog/epilog. This is
// a hack.
BuildMI(MBB, MI, PPC::MFLR, 1, PPC::R11);
addFrameReference(BuildMI(MBB, MI, PPC::STW, 3).addReg(PPC::R11),
BuildMI(MBB, MI, TII.get(PPC::MFLR), PPC::R11);
addFrameReference(BuildMI(MBB, MI, TII.get(PPC::STW)).addReg(PPC::R11),
FrameIdx);
}
} else if (RC == PPC::G8RCRegisterClass) {
if (SrcReg != PPC::LR8) {
addFrameReference(BuildMI(MBB, MI, PPC::STD, 3).addReg(SrcReg), FrameIdx);
addFrameReference(BuildMI(MBB, MI, TII.get(PPC::STD)).addReg(SrcReg),
FrameIdx);
} else {
// FIXME: this spills LR immediately to memory in one step. To do this,
// we use R11, which we know cannot be used in the prolog/epilog. This is
// a hack.
BuildMI(MBB, MI, PPC::MFLR8, 1, PPC::X11);
addFrameReference(BuildMI(MBB, MI, PPC::STD, 3).addReg(PPC::X11),
BuildMI(MBB, MI, TII.get(PPC::MFLR8), PPC::X11);
addFrameReference(BuildMI(MBB, MI, TII.get(PPC::STD)).addReg(PPC::X11),
FrameIdx);
}
} else if (RC == PPC::F8RCRegisterClass) {
addFrameReference(BuildMI(MBB, MI, PPC::STFD, 3).addReg(SrcReg),FrameIdx);
addFrameReference(BuildMI(MBB, MI, TII.get(PPC::STFD)).addReg(SrcReg),
FrameIdx);
} else if (RC == PPC::F4RCRegisterClass) {
addFrameReference(BuildMI(MBB, MI, PPC::STFS, 3).addReg(SrcReg),FrameIdx);
addFrameReference(BuildMI(MBB, MI, TII.get(PPC::STFS)).addReg(SrcReg),
FrameIdx);
} else if (RC == PPC::CRRCRegisterClass) {
// FIXME: We use R0 here, because it isn't available for RA.
// We need to store the CR in the low 4-bits of the saved value. First,
// issue a MFCR to save all of the CRBits.
BuildMI(MBB, MI, PPC::MFCR, 0, PPC::R0);
BuildMI(MBB, MI, TII.get(PPC::MFCR), PPC::R0);
// If the saved register wasn't CR0, shift the bits left so that they are in
// CR0's slot.
if (SrcReg != PPC::CR0) {
unsigned ShiftBits = PPCRegisterInfo::getRegisterNumbering(SrcReg)*4;
// rlwinm r0, r0, ShiftBits, 0, 31.
BuildMI(MBB, MI, PPC::RLWINM, 4, PPC::R0)
BuildMI(MBB, MI, TII.get(PPC::RLWINM), PPC::R0)
.addReg(PPC::R0).addImm(ShiftBits).addImm(0).addImm(31);
}
addFrameReference(BuildMI(MBB, MI, PPC::STW, 3).addReg(PPC::R0), FrameIdx);
addFrameReference(BuildMI(MBB, MI, TII.get(PPC::STW)).addReg(PPC::R0),
FrameIdx);
} else if (RC == PPC::VRRCRegisterClass) {
// We don't have indexed addressing for vector loads. Emit:
// R11 = ADDI FI#
// Dest = LVX R0, R11
//
// FIXME: We use R0 here, because it isn't available for RA.
addFrameReference(BuildMI(MBB, MI, PPC::ADDI, 1, PPC::R0), FrameIdx, 0, 0);
BuildMI(MBB, MI, PPC::STVX, 3)
addFrameReference(BuildMI(MBB, MI, TII.get(PPC::ADDI), PPC::R0),
FrameIdx, 0, 0);
BuildMI(MBB, MI, TII.get(PPC::STVX))
.addReg(SrcReg).addReg(PPC::R0).addReg(PPC::R0);
} else {
assert(0 && "Unknown regclass!");
@ -165,44 +171,45 @@ PPCRegisterInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
const TargetRegisterClass *RC) const {
if (RC == PPC::GPRCRegisterClass) {
if (DestReg != PPC::LR) {
addFrameReference(BuildMI(MBB, MI, PPC::LWZ, 2, DestReg), FrameIdx);
addFrameReference(BuildMI(MBB, MI, TII.get(PPC::LWZ), DestReg), FrameIdx);
} else {
addFrameReference(BuildMI(MBB, MI, PPC::LWZ, 2, PPC::R11), FrameIdx);
BuildMI(MBB, MI, PPC::MTLR, 1).addReg(PPC::R11);
addFrameReference(BuildMI(MBB, MI, TII.get(PPC::LWZ), PPC::R11),FrameIdx);
BuildMI(MBB, MI, TII.get(PPC::MTLR)).addReg(PPC::R11);
}
} else if (RC == PPC::G8RCRegisterClass) {
if (DestReg != PPC::LR8) {
addFrameReference(BuildMI(MBB, MI, PPC::LD, 2, DestReg), FrameIdx);
addFrameReference(BuildMI(MBB, MI, TII.get(PPC::LD), DestReg), FrameIdx);
} else {
addFrameReference(BuildMI(MBB, MI, PPC::LD, 2, PPC::R11), FrameIdx);
BuildMI(MBB, MI, PPC::MTLR8, 1).addReg(PPC::R11);
addFrameReference(BuildMI(MBB, MI, TII.get(PPC::LD), PPC::R11), FrameIdx);
BuildMI(MBB, MI, TII.get(PPC::MTLR8)).addReg(PPC::R11);
}
} else if (RC == PPC::F8RCRegisterClass) {
addFrameReference(BuildMI(MBB, MI, PPC::LFD, 2, DestReg), FrameIdx);
addFrameReference(BuildMI(MBB, MI, TII.get(PPC::LFD), DestReg), FrameIdx);
} else if (RC == PPC::F4RCRegisterClass) {
addFrameReference(BuildMI(MBB, MI, PPC::LFS, 2, DestReg), FrameIdx);
addFrameReference(BuildMI(MBB, MI, TII.get(PPC::LFS), DestReg), FrameIdx);
} else if (RC == PPC::CRRCRegisterClass) {
// FIXME: We use R0 here, because it isn't available for RA.
addFrameReference(BuildMI(MBB, MI, PPC::LWZ, 2, PPC::R0), FrameIdx);
addFrameReference(BuildMI(MBB, MI, TII.get(PPC::LWZ), PPC::R0), FrameIdx);
// If the reloaded register isn't CR0, shift the bits right so that they are
// in the right CR's slot.
if (DestReg != PPC::CR0) {
unsigned ShiftBits = PPCRegisterInfo::getRegisterNumbering(DestReg)*4;
// rlwinm r11, r11, 32-ShiftBits, 0, 31.
BuildMI(MBB, MI, PPC::RLWINM, 4, PPC::R0)
BuildMI(MBB, MI, TII.get(PPC::RLWINM), PPC::R0)
.addReg(PPC::R0).addImm(32-ShiftBits).addImm(0).addImm(31);
}
BuildMI(MBB, MI, PPC::MTCRF, 1, DestReg).addReg(PPC::R0);
BuildMI(MBB, MI, TII.get(PPC::MTCRF), DestReg).addReg(PPC::R0);
} else if (RC == PPC::VRRCRegisterClass) {
// We don't have indexed addressing for vector loads. Emit:
// R11 = ADDI FI#
// Dest = LVX R0, R11
//
// FIXME: We use R0 here, because it isn't available for RA.
addFrameReference(BuildMI(MBB, MI, PPC::ADDI, 1, PPC::R0), FrameIdx, 0, 0);
BuildMI(MBB, MI, PPC::LVX, 2, DestReg).addReg(PPC::R0).addReg(PPC::R0);
addFrameReference(BuildMI(MBB, MI, TII.get(PPC::ADDI), PPC::R0),
FrameIdx, 0, 0);
BuildMI(MBB, MI, TII.get(PPC::LVX),DestReg).addReg(PPC::R0).addReg(PPC::R0);
} else {
assert(0 && "Unknown regclass!");
abort();
@ -214,17 +221,17 @@ void PPCRegisterInfo::copyRegToReg(MachineBasicBlock &MBB,
unsigned DestReg, unsigned SrcReg,
const TargetRegisterClass *RC) const {
if (RC == PPC::GPRCRegisterClass) {
BuildMI(MBB, MI, PPC::OR, 2, DestReg).addReg(SrcReg).addReg(SrcReg);
BuildMI(MBB, MI, TII.get(PPC::OR), DestReg).addReg(SrcReg).addReg(SrcReg);
} else if (RC == PPC::G8RCRegisterClass) {
BuildMI(MBB, MI, PPC::OR8, 2, DestReg).addReg(SrcReg).addReg(SrcReg);
BuildMI(MBB, MI, TII.get(PPC::OR8), DestReg).addReg(SrcReg).addReg(SrcReg);
} else if (RC == PPC::F4RCRegisterClass) {
BuildMI(MBB, MI, PPC::FMRS, 1, DestReg).addReg(SrcReg);
BuildMI(MBB, MI, TII.get(PPC::FMRS), DestReg).addReg(SrcReg);
} else if (RC == PPC::F8RCRegisterClass) {
BuildMI(MBB, MI, PPC::FMRD, 1, DestReg).addReg(SrcReg);
BuildMI(MBB, MI, TII.get(PPC::FMRD), DestReg).addReg(SrcReg);
} else if (RC == PPC::CRRCRegisterClass) {
BuildMI(MBB, MI, PPC::MCRF, 1, DestReg).addReg(SrcReg);
BuildMI(MBB, MI, TII.get(PPC::MCRF), DestReg).addReg(SrcReg);
} else if (RC == PPC::VRRCRegisterClass) {
BuildMI(MBB, MI, PPC::VOR, 2, DestReg).addReg(SrcReg).addReg(SrcReg);
BuildMI(MBB, MI, TII.get(PPC::VOR), DestReg).addReg(SrcReg).addReg(SrcReg);
} else {
std::cerr << "Attempt to copy register that is not GPR or FPR";
abort();
@ -345,39 +352,40 @@ MachineInstr *PPCRegisterInfo::foldMemoryOperand(MachineInstr *MI,
MI->getOperand(1).getReg() == MI->getOperand(2).getReg())) {
if (OpNum == 0) { // move -> store
unsigned InReg = MI->getOperand(1).getReg();
NewMI = addFrameReference(BuildMI(TII, PPC::STW,
3).addReg(InReg), FrameIndex);
NewMI = addFrameReference(BuildMI(TII.get(PPC::STW)).addReg(InReg),
FrameIndex);
} else { // move -> load
unsigned OutReg = MI->getOperand(0).getReg();
NewMI = addFrameReference(BuildMI(TII, PPC::LWZ, 2, OutReg), FrameIndex);
NewMI = addFrameReference(BuildMI(TII.get(PPC::LWZ), OutReg),
FrameIndex);
}
} else if ((Opc == PPC::OR8 &&
MI->getOperand(1).getReg() == MI->getOperand(2).getReg())) {
if (OpNum == 0) { // move -> store
unsigned InReg = MI->getOperand(1).getReg();
NewMI = addFrameReference(BuildMI(TII, PPC::STD,
3).addReg(InReg), FrameIndex);
NewMI = addFrameReference(BuildMI(TII.get(PPC::STD)).addReg(InReg),
FrameIndex);
} else { // move -> load
unsigned OutReg = MI->getOperand(0).getReg();
NewMI = addFrameReference(BuildMI(TII, PPC::LD, 2, OutReg), FrameIndex);
NewMI = addFrameReference(BuildMI(TII.get(PPC::LD), OutReg), FrameIndex);
}
} else if (Opc == PPC::FMRD) {
if (OpNum == 0) { // move -> store
unsigned InReg = MI->getOperand(1).getReg();
NewMI = addFrameReference(BuildMI(TII, PPC::STFD,
3).addReg(InReg), FrameIndex);
NewMI = addFrameReference(BuildMI(TII.get(PPC::STFD)).addReg(InReg),
FrameIndex);
} else { // move -> load
unsigned OutReg = MI->getOperand(0).getReg();
NewMI = addFrameReference(BuildMI(TII, PPC::LFD, 2, OutReg), FrameIndex);
NewMI = addFrameReference(BuildMI(TII.get(PPC::LFD), OutReg), FrameIndex);
}
} else if (Opc == PPC::FMRS) {
if (OpNum == 0) { // move -> store
unsigned InReg = MI->getOperand(1).getReg();
NewMI = addFrameReference(BuildMI(TII, PPC::STFS,
3).addReg(InReg), FrameIndex);
NewMI = addFrameReference(BuildMI(TII.get(PPC::STFS)).addReg(InReg),
FrameIndex);
} else { // move -> load
unsigned OutReg = MI->getOperand(0).getReg();
NewMI = addFrameReference(BuildMI(TII, PPC::LFS, 2, OutReg), FrameIndex);
NewMI = addFrameReference(BuildMI(TII.get(PPC::LFS), OutReg), FrameIndex);
}
}
@ -455,15 +463,15 @@ void PPCRegisterInfo::lowerDynamicAlloc(MachineBasicBlock::iterator II) const {
// Constructing the constant and adding would take 3 instructions.
// Fortunately, a frame greater than 32K is rare.
if (MaxAlign < TargetAlign && isInt16(FrameSize)) {
BuildMI(MBB, II, PPC::ADDI, 2, PPC::R0)
BuildMI(MBB, II, TII.get(PPC::ADDI), PPC::R0)
.addReg(PPC::R31)
.addImm(FrameSize);
} else if (LP64) {
BuildMI(MBB, II, PPC::LD, 2, PPC::X0)
BuildMI(MBB, II, TII.get(PPC::LD), PPC::X0)
.addImm(0)
.addReg(PPC::X1);
} else {
BuildMI(MBB, II, PPC::LWZ, 2, PPC::R0)
BuildMI(MBB, II, TII.get(PPC::LWZ), PPC::R0)
.addImm(0)
.addReg(PPC::R1);
}
@ -471,19 +479,19 @@ void PPCRegisterInfo::lowerDynamicAlloc(MachineBasicBlock::iterator II) const {
// Grow the stack and update the stack pointer link, then
// determine the address of new allocated space.
if (LP64) {
BuildMI(MBB, II, PPC::STDUX, 3)
BuildMI(MBB, II, TII.get(PPC::STDUX))
.addReg(PPC::X0)
.addReg(PPC::X1)
.addReg(MI.getOperand(1).getReg());
BuildMI(MBB, II, PPC::ADDI8, 2, MI.getOperand(0).getReg())
BuildMI(MBB, II, TII.get(PPC::ADDI8), MI.getOperand(0).getReg())
.addReg(PPC::X1)
.addImm(maxCallFrameSize);
} else {
BuildMI(MBB, II, PPC::STWUX, 3)
BuildMI(MBB, II, TII.get(PPC::STWUX))
.addReg(PPC::R0)
.addReg(PPC::R1)
.addReg(MI.getOperand(1).getReg());
BuildMI(MBB, II, PPC::ADDI, 2, MI.getOperand(0).getReg())
BuildMI(MBB, II, TII.get(PPC::ADDI), MI.getOperand(0).getReg())
.addReg(PPC::R1)
.addImm(maxCallFrameSize);
}
@ -559,8 +567,8 @@ PPCRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II) const {
if (!isInt16(Offset)) {
// Insert a set of r0 with the full offset value before the ld, st, or add
BuildMI(MBB, II, PPC::LIS, 1, PPC::R0).addImm(Offset >> 16);
BuildMI(MBB, II, PPC::ORI, 2, PPC::R0).addReg(PPC::R0).addImm(Offset);
BuildMI(MBB, II, TII.get(PPC::LIS), PPC::R0).addImm(Offset >> 16);
BuildMI(MBB, II, TII.get(PPC::ORI), PPC::R0).addReg(PPC::R0).addImm(Offset);
// convert into indexed form of the instruction
// sth 0:rA, 1:imm 2:(rB) ==> sthx 0:rA, 2:rB, 1:r0
@ -640,7 +648,8 @@ static void RemoveVRSaveCode(MachineInstr *MI) {
// HandleVRSaveUpdate - MI is the UPDATE_VRSAVE instruction introduced by the
// instruction selector. Based on the vector registers that have been used,
// transform this into the appropriate ORI instruction.
static void HandleVRSaveUpdate(MachineInstr *MI, const bool *UsedRegs) {
static void HandleVRSaveUpdate(MachineInstr *MI, const bool *UsedRegs,
const TargetInstrInfo &TII) {
unsigned UsedRegMask = 0;
for (unsigned i = 0; i != 32; ++i)
if (UsedRegs[VRRegNo[i]])
@ -670,15 +679,15 @@ static void HandleVRSaveUpdate(MachineInstr *MI, const bool *UsedRegs) {
RemoveVRSaveCode(MI);
return;
} else if ((UsedRegMask & 0xFFFF) == UsedRegMask) {
BuildMI(*MI->getParent(), MI, PPC::ORI, 2, DstReg)
BuildMI(*MI->getParent(), MI, TII.get(PPC::ORI), DstReg)
.addReg(SrcReg).addImm(UsedRegMask);
} else if ((UsedRegMask & 0xFFFF0000) == UsedRegMask) {
BuildMI(*MI->getParent(), MI, PPC::ORIS, 2, DstReg)
BuildMI(*MI->getParent(), MI, TII.get(PPC::ORIS), DstReg)
.addReg(SrcReg).addImm(UsedRegMask >> 16);
} else {
BuildMI(*MI->getParent(), MI, PPC::ORIS, 2, DstReg)
BuildMI(*MI->getParent(), MI, TII.get(PPC::ORIS), DstReg)
.addReg(SrcReg).addImm(UsedRegMask >> 16);
BuildMI(*MI->getParent(), MI, PPC::ORI, 2, DstReg)
BuildMI(*MI->getParent(), MI, TII.get(PPC::ORI), DstReg)
.addReg(DstReg).addImm(UsedRegMask & 0xFFFF);
}
@ -750,7 +759,7 @@ void PPCRegisterInfo::emitPrologue(MachineFunction &MF) const {
// process it.
for (unsigned i = 0; MBBI != MBB.end(); ++i, ++MBBI) {
if (MBBI->getOpcode() == PPC::UPDATE_VRSAVE) {
HandleVRSaveUpdate(MBBI, MF.getUsedPhysregs());
HandleVRSaveUpdate(MBBI, MF.getUsedPhysregs(), TII);
break;
}
}
@ -775,10 +784,10 @@ void PPCRegisterInfo::emitPrologue(MachineFunction &MF) const {
int Offset = PPCFrameInfo::getFramePointerSaveOffset(Subtarget.isPPC64());
if (!Subtarget.isPPC64()) {
BuildMI(MBB, MBBI, PPC::STW, 3)
BuildMI(MBB, MBBI, TII.get(PPC::STW))
.addReg(PPC::R31).addImm(Offset).addReg(PPC::R1);
} else {
BuildMI(MBB, MBBI, PPC::STD, 3)
BuildMI(MBB, MBBI, TII.get(PPC::STD))
.addReg(PPC::X31).addImm(Offset/4).addReg(PPC::X1);
}
}
@ -794,40 +803,40 @@ void PPCRegisterInfo::emitPrologue(MachineFunction &MF) const {
if (MaxAlign > TargetAlign) {
assert(isPowerOf2_32(MaxAlign)&&isInt16(MaxAlign)&&"Invalid alignment!");
assert(isInt16(NegFrameSize) && "Unhandled stack size and alignment!");
BuildMI(MBB, MBBI, PPC::RLWINM, 4, PPC::R0)
BuildMI(MBB, MBBI, TII.get(PPC::RLWINM), PPC::R0)
.addReg(PPC::R1).addImm(0).addImm(32-Log2_32(MaxAlign)).addImm(31);
BuildMI(MBB, MBBI, PPC::SUBFIC,2,PPC::R0).addReg(PPC::R0)
BuildMI(MBB, MBBI, TII.get(PPC::SUBFIC) ,PPC::R0).addReg(PPC::R0)
.addImm(NegFrameSize);
BuildMI(MBB, MBBI, PPC::STWUX, 3)
BuildMI(MBB, MBBI, TII.get(PPC::STWUX))
.addReg(PPC::R1).addReg(PPC::R1).addReg(PPC::R0);
} else if (isInt16(NegFrameSize)) {
BuildMI(MBB, MBBI, PPC::STWU, 3,
BuildMI(MBB, MBBI, TII.get(PPC::STWU),
PPC::R1).addReg(PPC::R1).addImm(NegFrameSize).addReg(PPC::R1);
} else {
BuildMI(MBB, MBBI, PPC::LIS, 1, PPC::R0).addImm(NegFrameSize >> 16);
BuildMI(MBB, MBBI, PPC::ORI, 2, PPC::R0).addReg(PPC::R0)
BuildMI(MBB, MBBI, TII.get(PPC::LIS), PPC::R0).addImm(NegFrameSize >> 16);
BuildMI(MBB, MBBI, TII.get(PPC::ORI), PPC::R0).addReg(PPC::R0)
.addImm(NegFrameSize & 0xFFFF);
BuildMI(MBB, MBBI, PPC::STWUX, 3).addReg(PPC::R1).addReg(PPC::R1)
BuildMI(MBB, MBBI, TII.get(PPC::STWUX)).addReg(PPC::R1).addReg(PPC::R1)
.addReg(PPC::R0);
}
} else { // PPC64.
if (MaxAlign > TargetAlign) {
assert(isPowerOf2_32(MaxAlign)&&isInt16(MaxAlign)&&"Invalid alignment!");
assert(isInt16(NegFrameSize) && "Unhandled stack size and alignment!");
BuildMI(MBB, MBBI, PPC::RLDICL, 3, PPC::X0)
BuildMI(MBB, MBBI, TII.get(PPC::RLDICL), PPC::X0)
.addReg(PPC::X1).addImm(0).addImm(64-Log2_32(MaxAlign));
BuildMI(MBB, MBBI, PPC::SUBFIC8, 2, PPC::X0).addReg(PPC::X0)
BuildMI(MBB, MBBI, TII.get(PPC::SUBFIC8), PPC::X0).addReg(PPC::X0)
.addImm(NegFrameSize);
BuildMI(MBB, MBBI, PPC::STDUX, 3)
BuildMI(MBB, MBBI, TII.get(PPC::STDUX))
.addReg(PPC::X1).addReg(PPC::X1).addReg(PPC::X0);
} else if (isInt16(NegFrameSize)) {
BuildMI(MBB, MBBI, PPC::STDU, 3, PPC::X1)
BuildMI(MBB, MBBI, TII.get(PPC::STDU), PPC::X1)
.addReg(PPC::X1).addImm(NegFrameSize/4).addReg(PPC::X1);
} else {
BuildMI(MBB, MBBI, PPC::LIS8, 1, PPC::X0).addImm(NegFrameSize >> 16);
BuildMI(MBB, MBBI, PPC::ORI8, 2, PPC::X0).addReg(PPC::X0)
BuildMI(MBB, MBBI, TII.get(PPC::LIS8), PPC::X0).addImm(NegFrameSize >>16);
BuildMI(MBB, MBBI, TII.get(PPC::ORI8), PPC::X0).addReg(PPC::X0)
.addImm(NegFrameSize & 0xFFFF);
BuildMI(MBB, MBBI, PPC::STDUX, 3).addReg(PPC::X1).addReg(PPC::X1)
BuildMI(MBB, MBBI, TII.get(PPC::STDUX)).addReg(PPC::X1).addReg(PPC::X1)
.addReg(PPC::X0);
}
}
@ -837,7 +846,7 @@ void PPCRegisterInfo::emitPrologue(MachineFunction &MF) const {
unsigned LabelID = DebugInfo->NextLabelID();
// Mark effective beginning of when frame pointer becomes valid.
BuildMI(MBB, MBBI, PPC::DWARF_LABEL, 1).addImm(LabelID);
BuildMI(MBB, MBBI, TII.get(PPC::DWARF_LABEL)).addImm(LabelID);
// Show update of SP.
MachineLocation SPDst(MachineLocation::VirtualFP);
@ -857,9 +866,11 @@ void PPCRegisterInfo::emitPrologue(MachineFunction &MF) const {
// If there is a frame pointer, copy R1 into R31
if (HasFP) {
if (!Subtarget.isPPC64()) {
BuildMI(MBB, MBBI, PPC::OR, 2, PPC::R31).addReg(PPC::R1).addReg(PPC::R1);
BuildMI(MBB, MBBI, TII.get(PPC::OR), PPC::R31).addReg(PPC::R1)
.addReg(PPC::R1);
} else {
BuildMI(MBB, MBBI, PPC::OR8, 2, PPC::X31).addReg(PPC::X1).addReg(PPC::X1);
BuildMI(MBB, MBBI, TII.get(PPC::OR8), PPC::X31).addReg(PPC::X1)
.addReg(PPC::X1);
}
}
}
@ -884,18 +895,18 @@ void PPCRegisterInfo::emitEpilogue(MachineFunction &MF,
if (!Subtarget.isPPC64()) {
if (isInt16(FrameSize) && TargetAlign >= MaxAlign &&
!MFI->hasVarSizedObjects()) {
BuildMI(MBB, MBBI, PPC::ADDI, 2, PPC::R1)
BuildMI(MBB, MBBI, TII.get(PPC::ADDI), PPC::R1)
.addReg(PPC::R1).addImm(FrameSize);
} else {
BuildMI(MBB, MBBI, PPC::LWZ, 2, PPC::R1).addImm(0).addReg(PPC::R1);
BuildMI(MBB, MBBI, TII.get(PPC::LWZ),PPC::R1).addImm(0).addReg(PPC::R1);
}
} else {
if (isInt16(FrameSize) && TargetAlign >= MaxAlign &&
!MFI->hasVarSizedObjects()) {
BuildMI(MBB, MBBI, PPC::ADDI8, 2, PPC::X1)
BuildMI(MBB, MBBI, TII.get(PPC::ADDI8), PPC::X1)
.addReg(PPC::X1).addImm(FrameSize);
} else {
BuildMI(MBB, MBBI, PPC::LD, 2, PPC::X1).addImm(0).addReg(PPC::X1);
BuildMI(MBB, MBBI, TII.get(PPC::LD), PPC::X1).addImm(0).addReg(PPC::X1);
}
}
@ -905,10 +916,10 @@ void PPCRegisterInfo::emitEpilogue(MachineFunction &MF,
int Offset = PPCFrameInfo::getFramePointerSaveOffset(Subtarget.isPPC64());
if (!Subtarget.isPPC64()) {
BuildMI(MBB, MBBI, PPC::LWZ, 2, PPC::R31)
BuildMI(MBB, MBBI, TII.get(PPC::LWZ), PPC::R31)
.addImm(Offset).addReg(PPC::R1);
} else {
BuildMI(MBB, MBBI, PPC::LD, 2, PPC::X31)
BuildMI(MBB, MBBI, TII.get(PPC::LD), PPC::X31)
.addImm(Offset/4).addReg(PPC::X1);
}
}

1
llvm/lib/Target/PowerPC/PPCRegisterInfo.h
View File

@ -20,6 +20,7 @@
namespace llvm {
class PPCSubtarget;
class TargetInstrInfo;
class Type;
class PPCRegisterInfo : public PPCGenRegisterInfo {

2
llvm/lib/Target/Sparc/DelaySlotFiller.cpp
View File

@ -64,7 +64,7 @@ bool Filler::runOnMachineBasicBlock(MachineBasicBlock &MBB) {
if (TII->hasDelaySlot(I->getOpcode())) {
MachineBasicBlock::iterator J = I;
++J;
BuildMI(MBB, J, SP::NOP, 0);
BuildMI(MBB, J, TII->get(SP::NOP));
++FilledSlots;
Changed = true;
}

4
llvm/lib/Target/Sparc/FPMover.cpp
View File

@ -16,6 +16,7 @@
#include "llvm/CodeGen/MachineFunctionPass.h"
#include "llvm/CodeGen/MachineInstrBuilder.h"
#include "llvm/Target/TargetMachine.h"
#include "llvm/Target/TargetInstrInfo.h"
#include "llvm/ADT/Statistic.h"
#include "llvm/Support/Debug.h"
#include <iostream>
@ -109,7 +110,8 @@ bool FPMover::runOnMachineBasicBlock(MachineBasicBlock &MBB) {
DEBUG(std::cerr << "FPMover: the modified instr is: " << *MI);
// Insert copy for the other half of the double.
if (DestDReg != SrcDReg) {
MI = BuildMI(MBB, I, SP::FMOVS, 1, OddDestReg).addReg(OddSrcReg);
MI = BuildMI(MBB, I, TM.getInstrInfo()->get(SP::FMOVS), OddDestReg)
.addReg(OddSrcReg);
DEBUG(std::cerr << "FPMover: the inserted instr is: " << *MI);
}
++NumFpDs;

5
llvm/lib/Target/Sparc/SparcISelDAGToDAG.cpp
View File

@ -873,6 +873,7 @@ LowerOperation(SDOperand Op, SelectionDAG &DAG) {
MachineBasicBlock *
SparcTargetLowering::InsertAtEndOfBasicBlock(MachineInstr *MI,
MachineBasicBlock *BB) {
const TargetInstrInfo &TII = *getTargetMachine().getInstrInfo();
unsigned BROpcode;
unsigned CC;
// Figure out the conditional branch opcode to use for this select_cc.
@ -908,7 +909,7 @@ SparcTargetLowering::InsertAtEndOfBasicBlock(MachineInstr *MI,
MachineBasicBlock *thisMBB = BB;
MachineBasicBlock *copy0MBB = new MachineBasicBlock(LLVM_BB);
MachineBasicBlock *sinkMBB = new MachineBasicBlock(LLVM_BB);
BuildMI(BB, BROpcode, 2).addMBB(sinkMBB).addImm(CC);
BuildMI(BB, TII.get(BROpcode)).addMBB(sinkMBB).addImm(CC);
MachineFunction *F = BB->getParent();
F->getBasicBlockList().insert(It, copy0MBB);
F->getBasicBlockList().insert(It, sinkMBB);
@ -936,7 +937,7 @@ SparcTargetLowering::InsertAtEndOfBasicBlock(MachineInstr *MI,
// %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
// ...
BB = sinkMBB;
BuildMI(BB, SP::PHI, 4, MI->getOperand(0).getReg())
BuildMI(BB, TII.get(SP::PHI), MI->getOperand(0).getReg())
.addReg(MI->getOperand(2).getReg()).addMBB(copy0MBB)
.addReg(MI->getOperand(1).getReg()).addMBB(thisMBB);

2
llvm/lib/Target/Sparc/SparcInstrInfo.cpp
View File

@ -102,5 +102,5 @@ void SparcInstrInfo::InsertBranch(MachineBasicBlock &MBB,MachineBasicBlock *TBB,
const std::vector<MachineOperand> &Cond)const{
// Can only insert uncond branches so far.
assert(Cond.empty() && !FBB && TBB && "Can only handle uncond branches!");
BuildMI(&MBB, SP::BA, 1).addMBB(TBB);
BuildMI(&MBB, get(SP::BA)).addMBB(TBB);
}

53
llvm/lib/Target/Sparc/SparcRegisterInfo.cpp
View File

@ -18,6 +18,7 @@
#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/CodeGen/MachineFrameInfo.h"
#include "llvm/CodeGen/MachineLocation.h"
#include "llvm/Target/TargetInstrInfo.h"
#include "llvm/Type.h"
#include "llvm/ADT/STLExtras.h"
#include <iostream>
@ -35,11 +36,14 @@ storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
const TargetRegisterClass *RC) const {
// On the order of operands here: think "[FrameIdx + 0] = SrcReg".
if (RC == SP::IntRegsRegisterClass)
BuildMI(MBB, I, SP::STri, 3).addFrameIndex(FI).addImm(0).addReg(SrcReg);
BuildMI(MBB, I, TII.get(SP::STri)).addFrameIndex(FI).addImm(0)
.addReg(SrcReg);
else if (RC == SP::FPRegsRegisterClass)
BuildMI(MBB, I, SP::STFri, 3).addFrameIndex(FI).addImm(0).addReg(SrcReg);
BuildMI(MBB, I, TII.get(SP::STFri)).addFrameIndex(FI).addImm(0)
.addReg(SrcReg);
else if (RC == SP::DFPRegsRegisterClass)
BuildMI(MBB, I, SP::STDFri, 3).addFrameIndex(FI).addImm(0).addReg(SrcReg);
BuildMI(MBB, I, TII.get(SP::STDFri)).addFrameIndex(FI).addImm(0)
.addReg(SrcReg);
else
assert(0 && "Can't store this register to stack slot");
}
@ -49,11 +53,11 @@ loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
unsigned DestReg, int FI,
const TargetRegisterClass *RC) const {
if (RC == SP::IntRegsRegisterClass)
BuildMI(MBB, I, SP::LDri, 2, DestReg).addFrameIndex(FI).addImm(0);
BuildMI(MBB, I, TII.get(SP::LDri), DestReg).addFrameIndex(FI).addImm(0);
else if (RC == SP::FPRegsRegisterClass)
BuildMI(MBB, I, SP::LDFri, 2, DestReg).addFrameIndex(FI).addImm (0);
BuildMI(MBB, I, TII.get(SP::LDFri), DestReg).addFrameIndex(FI).addImm(0);
else if (RC == SP::DFPRegsRegisterClass)
BuildMI(MBB, I, SP::LDDFri, 2, DestReg).addFrameIndex(FI).addImm(0);
BuildMI(MBB, I, TII.get(SP::LDDFri), DestReg).addFrameIndex(FI).addImm(0);
else
assert(0 && "Can't load this register from stack slot");
}
@ -63,12 +67,12 @@ void SparcRegisterInfo::copyRegToReg(MachineBasicBlock &MBB,
unsigned DestReg, unsigned SrcReg,
const TargetRegisterClass *RC) const {
if (RC == SP::IntRegsRegisterClass)
BuildMI(MBB, I, SP::ORrr, 2, DestReg).addReg(SP::G0).addReg(SrcReg);
BuildMI(MBB, I, TII.get(SP::ORrr), DestReg).addReg(SP::G0).addReg(SrcReg);
else if (RC == SP::FPRegsRegisterClass)
BuildMI(MBB, I, SP::FMOVS, 1, DestReg).addReg(SrcReg);
BuildMI(MBB, I, TII.get(SP::FMOVS), DestReg).addReg(SrcReg);
else if (RC == SP::DFPRegsRegisterClass)
BuildMI(MBB, I, Subtarget.isV9() ? SP::FMOVD : SP::FpMOVD,
1, DestReg).addReg(SrcReg);
BuildMI(MBB, I, TII.get(Subtarget.isV9() ? SP::FMOVD : SP::FpMOVD),DestReg)
.addReg(SrcReg);
else
assert (0 && "Can't copy this register");
}
@ -83,10 +87,10 @@ MachineInstr *SparcRegisterInfo::foldMemoryOperand(MachineInstr* MI,
if (MI->getOperand(1).isRegister() && MI->getOperand(1).getReg() == SP::G0&&
MI->getOperand(0).isRegister() && MI->getOperand(2).isRegister()) {
if (OpNum == 0) // COPY -> STORE
NewMI = BuildMI(TII, SP::STri, 3).addFrameIndex(FI).addImm(0)
NewMI = BuildMI(TII.get(SP::STri)).addFrameIndex(FI).addImm(0)
.addReg(MI->getOperand(2).getReg());
else // COPY -> LOAD
NewMI = BuildMI(TII, SP::LDri, 2, MI->getOperand(0).getReg())
NewMI = BuildMI(TII.get(SP::LDri), MI->getOperand(0).getReg())
.addFrameIndex(FI).addImm(0);
}
break;
@ -95,10 +99,10 @@ MachineInstr *SparcRegisterInfo::foldMemoryOperand(MachineInstr* MI,
// FALLTHROUGH
case SP::FMOVD:
if (OpNum == 0) // COPY -> STORE
NewMI = BuildMI(TII, isFloat ? SP::STFri : SP::STDFri, 3)
NewMI = BuildMI(TII.get(isFloat ? SP::STFri : SP::STDFri))
.addFrameIndex(FI).addImm(0).addReg(MI->getOperand(1).getReg());
else // COPY -> LOAD
NewMI = BuildMI(TII, isFloat ? SP::LDFri : SP::LDDFri, 2,
NewMI = BuildMI(TII.get(isFloat ? SP::LDFri : SP::LDDFri),
MI->getOperand(0).getReg()).addFrameIndex(FI).addImm(0);
break;
}
@ -128,7 +132,7 @@ eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
if (MI.getOpcode() == SP::ADJCALLSTACKDOWN)
Size = -Size;
if (Size)
BuildMI(MBB, I, SP::ADDri, 2, SP::O6).addReg(SP::O6).addImm(Size);
BuildMI(MBB, I, TII.get(SP::ADDri), SP::O6).addReg(SP::O6).addImm(Size);
MBB.erase(I);
}
@ -158,10 +162,10 @@ SparcRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II) const {
// Otherwise, emit a G1 = SETHI %hi(offset). FIXME: it would be better to
// scavenge a register here instead of reserving G1 all of the time.
unsigned OffHi = (unsigned)Offset >> 10U;
BuildMI(*MI.getParent(), II, SP::SETHIi, 1, SP::G1).addImm(OffHi);
BuildMI(*MI.getParent(), II, TII.get(SP::SETHIi), SP::G1).addImm(OffHi);
// Emit G1 = G1 + I6
BuildMI(*MI.getParent(), II, SP::ADDrr, 2,
SP::G1).addReg(SP::G1).addReg(SP::I6);
BuildMI(*MI.getParent(), II, TII.get(SP::ADDrr), SP::G1).addReg(SP::G1)
.addReg(SP::I6);
// Insert: G1+%lo(offset) into the user.
MI.getOperand(i).ChangeToRegister(SP::G1, false);
MI.getOperand(i+1).ChangeToImmediate(Offset & ((1 << 10)-1));
@ -192,19 +196,19 @@ void SparcRegisterInfo::emitPrologue(MachineFunction &MF) const {
NumBytes = -NumBytes;
if (NumBytes >= -4096) {
BuildMI(MBB, MBB.begin(), SP::SAVEri, 2,
BuildMI(MBB, MBB.begin(), TII.get(SP::SAVEri),
SP::O6).addImm(NumBytes).addReg(SP::O6);
} else {
MachineBasicBlock::iterator InsertPt = MBB.begin();
// Emit this the hard way. This clobbers G1 which we always know is
// available here.
unsigned OffHi = (unsigned)NumBytes >> 10U;
BuildMI(MBB, InsertPt, SP::SETHIi, 1, SP::G1).addImm(OffHi);
BuildMI(MBB, InsertPt, TII.get(SP::SETHIi), SP::G1).addImm(OffHi);
// Emit G1 = G1 + I6
BuildMI(MBB, InsertPt, SP::ORri, 2, SP::G1)
BuildMI(MBB, InsertPt, TII.get(SP::ORri), SP::G1)
.addReg(SP::G1).addImm(NumBytes & ((1 << 10)-1));
BuildMI(MBB, InsertPt, SP::SAVErr, 2,
SP::O6).addReg(SP::O6).addReg(SP::G1);
BuildMI(MBB, InsertPt, TII.get(SP::SAVErr), SP::O6)
.addReg(SP::O6).addReg(SP::G1);
}
}
@ -213,7 +217,8 @@ void SparcRegisterInfo::emitEpilogue(MachineFunction &MF,
MachineBasicBlock::iterator MBBI = prior(MBB.end());
assert(MBBI->getOpcode() == SP::RETL &&
"Can only put epilog before 'retl' instruction!");
BuildMI(MBB, MBBI, SP::RESTORErr, 2, SP::G0).addReg(SP::G0).addReg(SP::G0);
BuildMI(MBB, MBBI, TII.get(SP::RESTORErr), SP::G0).addReg(SP::G0)
.addReg(SP::G0);
}
unsigned SparcRegisterInfo::getRARegister() const {

1
llvm/lib/Target/Sparc/SparcRegisterInfo.h
View File

@ -20,6 +20,7 @@
namespace llvm {
class SparcSubtarget;
class TargetInstrInfo;
class Type;
struct SparcRegisterInfo : public SparcGenRegisterInfo {

19
llvm/lib/Target/X86/X86FloatingPoint.cpp
View File

@ -107,6 +107,9 @@ namespace {
bool isAtTop(unsigned RegNo) const { return getSlot(RegNo) == StackTop-1; }
void moveToTop(unsigned RegNo, MachineBasicBlock::iterator &I) {
if (!isAtTop(RegNo)) {
MachineFunction *MF = I->getParent()->getParent();
const TargetInstrInfo &TII = *MF->getTarget().getInstrInfo();
unsigned STReg = getSTReg(RegNo);
unsigned RegOnTop = getStackEntry(0);
@ -118,16 +121,18 @@ namespace {
std::swap(Stack[RegMap[RegOnTop]], Stack[StackTop-1]);
// Emit an fxch to update the runtime processors version of the state
BuildMI(*MBB, I, X86::FXCH, 1).addReg(STReg);
BuildMI(*MBB, I, TII.get(X86::FXCH)).addReg(STReg);
NumFXCH++;
}
}
void duplicateToTop(unsigned RegNo, unsigned AsReg, MachineInstr *I) {
MachineFunction *MF = I->getParent()->getParent();
const TargetInstrInfo &TII = *MF->getTarget().getInstrInfo();
unsigned STReg = getSTReg(RegNo);
pushReg(AsReg); // New register on top of stack
BuildMI(*MBB, I, X86::FLDrr, 1).addReg(STReg);
BuildMI(*MBB, I, TII.get(X86::FLDrr)).addReg(STReg);
}
// popStackAfter - Pop the current value off of the top of the FP stack
@ -435,7 +440,9 @@ void FPS::popStackAfter(MachineBasicBlock::iterator &I) {
I->RemoveOperand(0);
} else { // Insert an explicit pop
I = BuildMI(*MBB, ++I, X86::FSTPrr, 1).addReg(X86::ST0);
MachineFunction *MF = I->getParent()->getParent();
const TargetInstrInfo &TII = *MF->getTarget().getInstrInfo();
I = BuildMI(*MBB, ++I, TII.get(X86::FSTPrr)).addReg(X86::ST0);
}
}
@ -459,7 +466,9 @@ void FPS::freeStackSlotAfter(MachineBasicBlock::iterator &I, unsigned FPRegNo) {
RegMap[TopReg] = OldSlot;
RegMap[FPRegNo] = ~0;
Stack[--StackTop] = ~0;
I = BuildMI(*MBB, ++I, X86::FSTPrr, 1).addReg(STReg);
MachineFunction *MF = I->getParent()->getParent();
const TargetInstrInfo &TII = *MF->getTarget().getInstrInfo();
I = BuildMI(*MBB, ++I, TII.get(X86::FSTPrr)).addReg(STReg);
}
@ -697,7 +706,7 @@ void FPS::handleTwoArgFP(MachineBasicBlock::iterator &I) {
// Replace the old instruction with a new instruction
MBB->remove(I++);
I = BuildMI(*MBB, I, Opcode, 1).addReg(getSTReg(NotTOS));
I = BuildMI(*MBB, I, TII.get(Opcode)).addReg(getSTReg(NotTOS));
// If both operands are killed, pop one off of the stack in addition to
// overwriting the other one.

19
llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
View File

@ -525,7 +525,8 @@ void X86DAGToDAGISel::InstructionSelectBasicBlock(SelectionDAG &DAG) {
// Finally, if we found any FP code, emit the FP_REG_KILL instruction.
if (ContainsFPCode) {
BuildMI(*BB, BB->getFirstTerminator(), X86::FP_REG_KILL, 0);
BuildMI(*BB, BB->getFirstTerminator(),
TM.getInstrInfo()->get(X86::FP_REG_KILL));
++NumFPKill;
}
}
@ -535,19 +536,20 @@ void X86DAGToDAGISel::InstructionSelectBasicBlock(SelectionDAG &DAG) {
/// the main function.
void X86DAGToDAGISel::EmitSpecialCodeForMain(MachineBasicBlock *BB,
MachineFrameInfo *MFI) {
const TargetInstrInfo *TII = TM.getInstrInfo();
if (Subtarget->isTargetCygwin())
BuildMI(BB, X86::CALLpcrel32, 1).addExternalSymbol("__main");
BuildMI(BB, TII->get(X86::CALLpcrel32)).addExternalSymbol("__main");
// Switch the FPU to 64-bit precision mode for better compatibility and speed.
int CWFrameIdx = MFI->CreateStackObject(2, 2);
addFrameReference(BuildMI(BB, X86::FNSTCW16m, 4), CWFrameIdx);
addFrameReference(BuildMI(BB, TII->get(X86::FNSTCW16m)), CWFrameIdx);
// Set the high part to be 64-bit precision.
addFrameReference(BuildMI(BB, X86::MOV8mi, 5),
addFrameReference(BuildMI(BB, TII->get(X86::MOV8mi)),
CWFrameIdx, 1).addImm(2);
// Reload the modified control word now.
addFrameReference(BuildMI(BB, X86::FLDCW16m, 4), CWFrameIdx);
addFrameReference(BuildMI(BB, TII->get(X86::FLDCW16m)), CWFrameIdx);
}
void X86DAGToDAGISel::EmitFunctionEntryCode(Function &Fn, MachineFunction &MF) {
@ -943,11 +945,10 @@ SDNode *X86DAGToDAGISel::getGlobalBaseReg() {
MachineBasicBlock &FirstMBB = BB->getParent()->front();
MachineBasicBlock::iterator MBBI = FirstMBB.begin();
SSARegMap *RegMap = BB->getParent()->getSSARegMap();
// FIXME: when we get to LP64, we will need to create the appropriate
// type of register here.
GlobalBaseReg = RegMap->createVirtualRegister(X86::GR32RegisterClass);
BuildMI(FirstMBB, MBBI, X86::MovePCtoStack, 0);
BuildMI(FirstMBB, MBBI, X86::POP32r, 1, GlobalBaseReg);
const TargetInstrInfo *TII = TM.getInstrInfo();
BuildMI(FirstMBB, MBBI, TII->get(X86::MovePCtoStack));
BuildMI(FirstMBB, MBBI, TII->get(X86::POP32r), GlobalBaseReg);
}
return CurDAG->getRegister(GlobalBaseReg, TLI.getPointerTy()).Val;
}

22
llvm/lib/Target/X86/X86ISelLowering.cpp
View File

@ -5036,6 +5036,7 @@ bool X86TargetLowering::isVectorClearMaskLegal(std::vector<SDOperand> &BVOps,
MachineBasicBlock *
X86TargetLowering::InsertAtEndOfBasicBlock(MachineInstr *MI,
MachineBasicBlock *BB) {
const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
switch (MI->getOpcode()) {
default: assert(false && "Unexpected instr type to insert");
case X86::CMOV_FR32:
@ -5062,7 +5063,7 @@ X86TargetLowering::InsertAtEndOfBasicBlock(MachineInstr *MI,
MachineBasicBlock *sinkMBB = new MachineBasicBlock(LLVM_BB);
unsigned Opc =
X86::GetCondBranchFromCond((X86::CondCode)MI->getOperand(3).getImm());
BuildMI(BB, Opc, 1).addMBB(sinkMBB);
BuildMI(BB, TII->get(Opc)).addMBB(sinkMBB);
MachineFunction *F = BB->getParent();
F->getBasicBlockList().insert(It, copy0MBB);
F->getBasicBlockList().insert(It, sinkMBB);
@ -5090,7 +5091,7 @@ X86TargetLowering::InsertAtEndOfBasicBlock(MachineInstr *MI,
// %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
// ...
BB = sinkMBB;
BuildMI(BB, X86::PHI, 4, MI->getOperand(0).getReg())
BuildMI(BB, TII->get(X86::PHI), MI->getOperand(0).getReg())
.addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB)
.addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
@ -5105,21 +5106,23 @@ X86TargetLowering::InsertAtEndOfBasicBlock(MachineInstr *MI,
// mode when truncating to an integer value.
MachineFunction *F = BB->getParent();
int CWFrameIdx = F->getFrameInfo()->CreateStackObject(2, 2);
addFrameReference(BuildMI(BB, X86::FNSTCW16m, 4), CWFrameIdx);
addFrameReference(BuildMI(BB, TII->get(X86::FNSTCW16m)), CWFrameIdx);
// Load the old value of the high byte of the control word...
unsigned OldCW =
F->getSSARegMap()->createVirtualRegister(X86::GR16RegisterClass);
addFrameReference(BuildMI(BB, X86::MOV16rm, 4, OldCW), CWFrameIdx);
addFrameReference(BuildMI(BB, TII->get(X86::MOV16rm), OldCW), CWFrameIdx);
// Set the high part to be round to zero...
addFrameReference(BuildMI(BB, X86::MOV16mi, 5), CWFrameIdx).addImm(0xC7F);
addFrameReference(BuildMI(BB, TII->get(X86::MOV16mi)), CWFrameIdx)
.addImm(0xC7F);
// Reload the modified control word now...
addFrameReference(BuildMI(BB, X86::FLDCW16m, 4), CWFrameIdx);
addFrameReference(BuildMI(BB, TII->get(X86::FLDCW16m)), CWFrameIdx);
// Restore the memory image of control word to original value
addFrameReference(BuildMI(BB, X86::MOV16mr, 5), CWFrameIdx).addReg(OldCW);
addFrameReference(BuildMI(BB, TII->get(X86::MOV16mr)), CWFrameIdx)
.addReg(OldCW);
// Get the X86 opcode to use.
unsigned Opc;
@ -5151,10 +5154,11 @@ X86TargetLowering::InsertAtEndOfBasicBlock(MachineInstr *MI,
} else {
AM.Disp = Op.getImm();
}
addFullAddress(BuildMI(BB, Opc, 5), AM).addReg(MI->getOperand(4).getReg());
addFullAddress(BuildMI(BB, TII->get(Opc)), AM)
.addReg(MI->getOperand(4).getReg());
// Reload the original control word now.
addFrameReference(BuildMI(BB, X86::FLDCW16m, 4), CWFrameIdx);
addFrameReference(BuildMI(BB, TII->get(X86::FLDCW16m)), CWFrameIdx);
delete MI; // The pseudo instruction is gone now.
return BB;

30
llvm/lib/Target/X86/X86InstrInfo.cpp
View File

@ -139,7 +139,7 @@ MachineInstr *X86InstrInfo::convertToThreeAddress(MachineInstr *MI) const {
unsigned C = MI->getOperand(2).getReg();
unsigned M = MI->getOperand(3).getImmedValue();
if (!Subtarget->hasSSE2() || B != C) return 0;
NewMI = BuildMI(*this, X86::PSHUFDri, 2, A).addReg(B).addImm(M);
NewMI = BuildMI(get(X86::PSHUFDri), A).addReg(B).addImm(M);
NewMI->copyKillDeadInfo(MI);
return NewMI;
}
@ -158,41 +158,41 @@ MachineInstr *X86InstrInfo::convertToThreeAddress(MachineInstr *MI) const {
case X86::INC32r:
case X86::INC64_32r:
assert(MI->getNumOperands() == 2 && "Unknown inc instruction!");
NewMI = addRegOffset(BuildMI(*this, X86::LEA32r, 5, Dest), Src, 1);
NewMI = addRegOffset(BuildMI(get(X86::LEA32r), Dest), Src, 1);
break;
case X86::INC16r:
case X86::INC64_16r:
if (DisableLEA16) return 0;
assert(MI->getNumOperands() == 2 && "Unknown inc instruction!");
NewMI = addRegOffset(BuildMI(*this, X86::LEA16r, 5, Dest), Src, 1);
NewMI = addRegOffset(BuildMI(get(X86::LEA16r), Dest), Src, 1);
break;
case X86::DEC32r:
case X86::DEC64_32r:
assert(MI->getNumOperands() == 2 && "Unknown dec instruction!");
NewMI = addRegOffset(BuildMI(*this, X86::LEA32r, 5, Dest), Src, -1);
NewMI = addRegOffset(BuildMI(get(X86::LEA32r), Dest), Src, -1);
break;
case X86::DEC16r:
case X86::DEC64_16r:
if (DisableLEA16) return 0;
assert(MI->getNumOperands() == 2 && "Unknown dec instruction!");
NewMI = addRegOffset(BuildMI(*this, X86::LEA16r, 5, Dest), Src, -1);
NewMI = addRegOffset(BuildMI(get(X86::LEA16r), Dest), Src, -1);
break;
case X86::ADD32rr:
assert(MI->getNumOperands() == 3 && "Unknown add instruction!");
NewMI = addRegReg(BuildMI(*this, X86::LEA32r, 5, Dest), Src,
NewMI = addRegReg(BuildMI(get(X86::LEA32r), Dest), Src,
MI->getOperand(2).getReg());
break;
case X86::ADD16rr:
if (DisableLEA16) return 0;
assert(MI->getNumOperands() == 3 && "Unknown add instruction!");
NewMI = addRegReg(BuildMI(*this, X86::LEA16r, 5, Dest), Src,
NewMI = addRegReg(BuildMI(get(X86::LEA16r), Dest), Src,
MI->getOperand(2).getReg());
break;
case X86::ADD32ri:
case X86::ADD32ri8:
assert(MI->getNumOperands() == 3 && "Unknown add instruction!");
if (MI->getOperand(2).isImmediate())
NewMI = addRegOffset(BuildMI(*this, X86::LEA32r, 5, Dest), Src,
NewMI = addRegOffset(BuildMI(get(X86::LEA32r), Dest), Src,
MI->getOperand(2).getImmedValue());
break;
case X86::ADD16ri:
@ -200,7 +200,7 @@ MachineInstr *X86InstrInfo::convertToThreeAddress(MachineInstr *MI) const {
if (DisableLEA16) return 0;
assert(MI->getNumOperands() == 3 && "Unknown add instruction!");
if (MI->getOperand(2).isImmediate())
NewMI = addRegOffset(BuildMI(*this, X86::LEA16r, 5, Dest), Src,
NewMI = addRegOffset(BuildMI(get(X86::LEA16r), Dest), Src,
MI->getOperand(2).getImmedValue());
break;
case X86::SHL16ri:
@ -214,7 +214,7 @@ MachineInstr *X86InstrInfo::convertToThreeAddress(MachineInstr *MI) const {
AM.Scale = 1 << ShAmt;
AM.IndexReg = Src;
unsigned Opc = MI->getOpcode() == X86::SHL32ri ? X86::LEA32r :X86::LEA16r;
NewMI = addFullAddress(BuildMI(*this, Opc, 5, Dest), AM);
NewMI = addFullAddress(BuildMI(get(Opc), Dest), AM);
}
break;
}
@ -249,7 +249,7 @@ MachineInstr *X86InstrInfo::commuteInstruction(MachineInstr *MI) const {
unsigned C = MI->getOperand(2).getReg();
bool BisKill = MI->getOperand(1).isKill();
bool CisKill = MI->getOperand(2).isKill();
return BuildMI(*this, Opc, 3, A).addReg(C, false, false, CisKill)
return BuildMI(get(Opc), A).addReg(C, false, false, CisKill)
.addReg(B, false, false, BisKill).addImm(Size-Amt);
}
default:
@ -416,19 +416,19 @@ void X86InstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
if (FBB == 0) { // One way branch.
if (Cond.empty()) {
// Unconditional branch?
BuildMI(&MBB, X86::JMP, 1).addMBB(TBB);
BuildMI(&MBB, get(X86::JMP)).addMBB(TBB);
} else {
// Conditional branch.
unsigned Opc = GetCondBranchFromCond((X86::CondCode)Cond[0].getImm());
BuildMI(&MBB, Opc, 1).addMBB(TBB);
BuildMI(&MBB, get(Opc)).addMBB(TBB);
}
return;
}
// Two-way Conditional branch.
unsigned Opc = GetCondBranchFromCond((X86::CondCode)Cond[0].getImm());
BuildMI(&MBB, Opc, 1).addMBB(TBB);
BuildMI(&MBB, X86::JMP, 1).addMBB(FBB);
BuildMI(&MBB, get(Opc)).addMBB(TBB);
BuildMI(&MBB, get(X86::JMP)).addMBB(FBB);
}
bool X86InstrInfo::BlockHasNoFallThrough(MachineBasicBlock &MBB) const {

46
llvm/lib/Target/X86/X86RegisterInfo.cpp
View File

@ -93,7 +93,7 @@ void X86RegisterInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
assert(0 && "Unknown regclass");
abort();
}
addFrameReference(BuildMI(MBB, MI, Opc, 5), FrameIdx).addReg(SrcReg);
addFrameReference(BuildMI(MBB, MI, TII.get(Opc)), FrameIdx).addReg(SrcReg);
}
void X86RegisterInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
@ -125,7 +125,7 @@ void X86RegisterInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
assert(0 && "Unknown regclass");
abort();
}
addFrameReference(BuildMI(MBB, MI, Opc, 4, DestReg), FrameIdx);
addFrameReference(BuildMI(MBB, MI, TII.get(Opc), DestReg), FrameIdx);
}
void X86RegisterInfo::copyRegToReg(MachineBasicBlock &MBB,
@ -157,7 +157,7 @@ void X86RegisterInfo::copyRegToReg(MachineBasicBlock &MBB,
assert(0 && "Unknown regclass");
abort();
}
BuildMI(MBB, MI, Opc, 1, DestReg).addReg(SrcReg);
BuildMI(MBB, MI, TII.get(Opc), DestReg).addReg(SrcReg);
}
static MachineInstr *FuseTwoAddrInst(unsigned Opcode, unsigned FrameIndex,
@ -165,7 +165,7 @@ static MachineInstr *FuseTwoAddrInst(unsigned Opcode, unsigned FrameIndex,
const TargetInstrInfo &TII) {
unsigned NumOps = TII.getNumOperands(MI->getOpcode())-2;
// Create the base instruction with the memory operand as the first part.
MachineInstrBuilder MIB = addFrameReference(BuildMI(TII, Opcode, 4+NumOps),
MachineInstrBuilder MIB = addFrameReference(BuildMI(TII.get(Opcode)),
FrameIndex);
// Loop over the rest of the ri operands, converting them over.
@ -188,7 +188,7 @@ static MachineInstr *FuseTwoAddrInst(unsigned Opcode, unsigned FrameIndex,
static MachineInstr *FuseInst(unsigned Opcode, unsigned OpNo,
unsigned FrameIndex, MachineInstr *MI,
const TargetInstrInfo &TII) {
MachineInstrBuilder MIB = BuildMI(TII, Opcode, MI->getNumOperands()+3);
MachineInstrBuilder MIB = BuildMI(TII.get(Opcode));
for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
MachineOperand &MO = MI->getOperand(i);
@ -212,7 +212,7 @@ static MachineInstr *FuseInst(unsigned Opcode, unsigned OpNo,
static MachineInstr *MakeM0Inst(const TargetInstrInfo &TII,
unsigned Opcode, unsigned FrameIndex,
MachineInstr *MI) {
return addFrameReference(BuildMI(TII, Opcode, 5), FrameIndex).addImm(0);
return addFrameReference(BuildMI(TII.get(Opcode)), FrameIndex).addImm(0);
}
@ -908,7 +908,7 @@ eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
MachineInstr *New = 0;
if (Old->getOpcode() == X86::ADJCALLSTACKDOWN) {
New=BuildMI(TII, Is64Bit ? X86::SUB64ri32 : X86::SUB32ri, 1, StackPtr)
New=BuildMI(TII.get(Is64Bit ? X86::SUB64ri32 : X86::SUB32ri), StackPtr)
.addReg(StackPtr).addImm(Amount);
} else {
assert(Old->getOpcode() == X86::ADJCALLSTACKUP);
@ -919,7 +919,7 @@ eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
unsigned Opc = (Amount < 128) ?
(Is64Bit ? X86::ADD64ri8 : X86::ADD32ri8) :
(Is64Bit ? X86::ADD64ri32 : X86::ADD32ri);
New = BuildMI(TII, Opc, 1, StackPtr).addReg(StackPtr).addImm(Amount);
New = BuildMI(TII.get(Opc), StackPtr).addReg(StackPtr).addImm(Amount);
}
}
@ -935,7 +935,7 @@ eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
(Is64Bit ? X86::SUB64ri8 : X86::SUB32ri8) :
(Is64Bit ? X86::SUB64ri32 : X86::SUB32ri);
MachineInstr *New =
BuildMI(TII, Opc, 1, StackPtr).addReg(StackPtr).addImm(CalleeAmt);
BuildMI(TII.get(Opc), StackPtr).addReg(StackPtr).addImm(CalleeAmt);
MBB.insert(I, New);
}
}
@ -1012,15 +1012,15 @@ void X86RegisterInfo::emitPrologue(MachineFunction &MF) const {
// more than 4k bytes in one go. Touching the stack at 4K increments is
// necessary to ensure that the guard pages used by the OS virtual memory
// manager are allocated in correct sequence.
MI = BuildMI(TII, X86::MOV32ri, 2, X86::EAX).addImm(NumBytes);
MI = BuildMI(TII.get(X86::MOV32ri), X86::EAX).addImm(NumBytes);
MBB.insert(MBBI, MI);
MI = BuildMI(TII, X86::CALLpcrel32, 1).addExternalSymbol("_alloca");
MI = BuildMI(TII.get(X86::CALLpcrel32)).addExternalSymbol("_alloca");
MBB.insert(MBBI, MI);
} else {
unsigned Opc = (NumBytes < 128) ?
(Is64Bit ? X86::SUB64ri8 : X86::SUB32ri8) :
(Is64Bit ? X86::SUB64ri32 : X86::SUB32ri);
MI= BuildMI(TII, Opc, 1, StackPtr).addReg(StackPtr).addImm(NumBytes);
MI= BuildMI(TII.get(Opc), StackPtr).addReg(StackPtr).addImm(NumBytes);
MBB.insert(MBBI, MI);
}
}
@ -1034,17 +1034,17 @@ void X86RegisterInfo::emitPrologue(MachineFunction &MF) const {
// Save EBP into the appropriate stack slot...
// mov [ESP-<offset>], EBP
MI = addRegOffset(BuildMI(TII, Is64Bit ? X86::MOV64mr : X86::MOV32mr, 5),
MI = addRegOffset(BuildMI(TII.get(Is64Bit ? X86::MOV64mr : X86::MOV32mr)),
StackPtr, EBPOffset+NumBytes).addReg(FramePtr);
MBB.insert(MBBI, MI);
// Update EBP with the new base value...
if (NumBytes == SlotSize) // mov EBP, ESP
MI = BuildMI(TII, Is64Bit ? X86::MOV64rr : X86::MOV32rr, 2, FramePtr).
MI = BuildMI(TII.get(Is64Bit ? X86::MOV64rr : X86::MOV32rr), FramePtr).
addReg(StackPtr);
else // lea EBP, [ESP+StackSize]
MI = addRegOffset(BuildMI(TII, Is64Bit ? X86::LEA64r : X86::LEA32r,
5, FramePtr), StackPtr, NumBytes-SlotSize);
MI = addRegOffset(BuildMI(TII.get(Is64Bit ? X86::LEA64r : X86::LEA32r),
FramePtr), StackPtr, NumBytes-SlotSize);
MBB.insert(MBBI, MI);
}
@ -1052,13 +1052,13 @@ void X86RegisterInfo::emitPrologue(MachineFunction &MF) const {
// If it's main() on Cygwin\Mingw32 we should align stack as well
if (Fn->hasExternalLinkage() && Fn->getName() == "main" &&
Subtarget->isTargetCygwin()) {
MI= BuildMI(TII, X86::AND32ri, 2, X86::ESP).addReg(X86::ESP).addImm(-Align);
MI= BuildMI(TII.get(X86::AND32ri), X86::ESP).addReg(X86::ESP).addImm(-Align);
MBB.insert(MBBI, MI);
// Probe the stack
MI = BuildMI(TII, X86::MOV32ri, 2, X86::EAX).addImm(Align);
MI = BuildMI(TII.get(X86::MOV32ri), X86::EAX).addImm(Align);
MBB.insert(MBBI, MI);
MI = BuildMI(TII, X86::CALLpcrel32, 1).addExternalSymbol("_alloca");
MI = BuildMI(TII.get(X86::CALLpcrel32)).addExternalSymbol("_alloca");
MBB.insert(MBBI, MI);
}
}
@ -1080,11 +1080,11 @@ void X86RegisterInfo::emitEpilogue(MachineFunction &MF,
if (hasFP(MF)) {
// mov ESP, EBP
BuildMI(MBB, MBBI, Is64Bit ? X86::MOV64rr : X86::MOV32rr, 1, StackPtr).
BuildMI(MBB, MBBI, TII.get(Is64Bit ? X86::MOV64rr : X86::MOV32rr),StackPtr).
addReg(FramePtr);
// pop EBP
BuildMI(MBB, MBBI, Is64Bit ? X86::POP64r : X86::POP32r, 0, FramePtr);
BuildMI(MBB, MBBI, TII.get(Is64Bit ? X86::POP64r : X86::POP32r), FramePtr);
} else {
// Get the number of bytes allocated from the FrameInfo...
unsigned NumBytes = MFI->getStackSize();
@ -1112,12 +1112,12 @@ void X86RegisterInfo::emitEpilogue(MachineFunction &MF,
unsigned Opc = (NumBytes < 128) ?
(Is64Bit ? X86::ADD64ri8 : X86::ADD32ri8) :
(Is64Bit ? X86::ADD64ri32 : X86::ADD32ri);
BuildMI(MBB, MBBI, Opc, 2, StackPtr).addReg(StackPtr).addImm(NumBytes);
BuildMI(MBB, MBBI, TII.get(Opc), StackPtr).addReg(StackPtr).addImm(NumBytes);
} else if ((int)NumBytes < 0) {
unsigned Opc = (-NumBytes < 128) ?
(Is64Bit ? X86::SUB64ri8 : X86::SUB32ri8) :
(Is64Bit ? X86::SUB64ri32 : X86::SUB32ri);
BuildMI(MBB, MBBI, Opc, 2, StackPtr).addReg(StackPtr).addImm(-NumBytes);
BuildMI(MBB, MBBI, TII.get(Opc), StackPtr).addReg(StackPtr).addImm(-NumBytes);
}
}
}