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Migrate HexagonISelDAGToDAG to setting a subtarget pointer during 

runOnMachineFunction. Update all uses of the Subtarget accordingly.

llvm-svn: 227840
This commit is contained in:
Eric Christopher 2015-02-02 19:22:03 +00:00
parent 90295c9c63
commit 202f22bbda
3 changed files with 43 additions and 44 deletions
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24
llvm/lib/Target/Hexagon/Hexagon.td
View File

@ -34,18 +34,18 @@ def ArchV5 : SubtargetFeature<"v5", "HexagonArchVersion", "V5",
//===----------------------------------------------------------------------===//
// Hexagon Instruction Predicate Definitions.
//===----------------------------------------------------------------------===//
def HasV2T : Predicate<"Subtarget.hasV2TOps()">;
def HasV2TOnly : Predicate<"Subtarget.hasV2TOpsOnly()">;
def NoV2T : Predicate<"!Subtarget.hasV2TOps()">;
def HasV3T : Predicate<"Subtarget.hasV3TOps()">;
def HasV3TOnly : Predicate<"Subtarget.hasV3TOpsOnly()">;
def NoV3T : Predicate<"!Subtarget.hasV3TOps()">;
def HasV4T : Predicate<"Subtarget.hasV4TOps()">;
def NoV4T : Predicate<"!Subtarget.hasV4TOps()">;
def HasV5T : Predicate<"Subtarget.hasV5TOps()">;
def NoV5T : Predicate<"!Subtarget.hasV5TOps()">;
def UseMEMOP : Predicate<"Subtarget.useMemOps()">;
def IEEERndNearV5T : Predicate<"Subtarget.modeIEEERndNear()">;
def HasV2T : Predicate<"Subtarget->hasV2TOps()">;
def HasV2TOnly : Predicate<"Subtarget->hasV2TOpsOnly()">;
def NoV2T : Predicate<"!Subtarget->hasV2TOps()">;
def HasV3T : Predicate<"Subtarget->hasV3TOps()">;
def HasV3TOnly : Predicate<"Subtarget->hasV3TOpsOnly()">;
def NoV3T : Predicate<"!Subtarget->hasV3TOps()">;
def HasV4T : Predicate<"Subtarget->hasV4TOps()">;
def NoV4T : Predicate<"!Subtarget->hasV4TOps()">;
def HasV5T : Predicate<"Subtarget->hasV5TOps()">;
def NoV5T : Predicate<"!Subtarget->hasV5TOps()">;
def UseMEMOP : Predicate<"Subtarget->useMemOps()">;
def IEEERndNearV5T : Predicate<"Subtarget->modeIEEERndNear()">;
//===----------------------------------------------------------------------===//
// Classes used for relation maps.

23
llvm/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp
View File

@ -47,7 +47,7 @@ namespace {
class HexagonDAGToDAGISel : public SelectionDAGISel {
/// Subtarget - Keep a pointer to the Hexagon Subtarget around so that we can
/// make the right decision when generating code for different targets.
const HexagonSubtarget &Subtarget;
const HexagonSubtarget *Subtarget;
// Keep a reference to HexagonTargetMachine.
const HexagonTargetMachine& TM;
@ -55,9 +55,7 @@ class HexagonDAGToDAGISel : public SelectionDAGISel {
public:
explicit HexagonDAGToDAGISel(HexagonTargetMachine &targetmachine,
CodeGenOpt::Level OptLevel)
: SelectionDAGISel(targetmachine, OptLevel),
Subtarget(targetmachine.getSubtarget<HexagonSubtarget>()),
TM(targetmachine) {
: SelectionDAGISel(targetmachine, OptLevel), TM(targetmachine) {
initializeHexagonDAGToDAGISelPass(*PassRegistry::getPassRegistry());
}
bool hasNumUsesBelowThresGA(SDNode *N) const;
@ -85,6 +83,11 @@ public:
return "Hexagon DAG->DAG Pattern Instruction Selection";
}
bool runOnMachineFunction(MachineFunction &MF) override {
Subtarget = &MF.getSubtarget<HexagonSubtarget>();
return SelectionDAGISel::runOnMachineFunction(MF);
}
/// SelectInlineAsmMemoryOperand - Implement addressing mode selection for
/// inline asm expressions.
bool SelectInlineAsmMemoryOperand(const SDValue &Op,
@ -411,8 +414,7 @@ SDNode *HexagonDAGToDAGISel::SelectIndexedLoadSignExtend64(LoadSDNode *LD,
if (SelectADDRriS11_2(N1, CPTmpN1_0, CPTmpN1_1) &&
N1.getNode()->getValueType(0) == MVT::i32) {
const HexagonInstrInfo *TII = static_cast<const HexagonInstrInfo *>(
TM.getSubtargetImpl()->getInstrInfo());
const HexagonInstrInfo *TII = Subtarget->getInstrInfo();
if (TII->isValidAutoIncImm(LoadedVT, Val)) {
SDValue TargetConst = CurDAG->getTargetConstant(Val, MVT::i32);
SDNode *Result_1 = CurDAG->getMachineNode(Opcode, dl, MVT::i32, MVT::i32,
@ -478,8 +480,7 @@ SDNode *HexagonDAGToDAGISel::SelectIndexedLoadZeroExtend64(LoadSDNode *LD,
if (SelectADDRriS11_2(N1, CPTmpN1_0, CPTmpN1_1) &&
N1.getNode()->getValueType(0) == MVT::i32) {
const HexagonInstrInfo *TII = static_cast<const HexagonInstrInfo *>(
TM.getSubtargetImpl()->getInstrInfo());
const HexagonInstrInfo *TII = Subtarget->getInstrInfo();
if (TII->isValidAutoIncImm(LoadedVT, Val)) {
SDValue TargetConstVal = CurDAG->getTargetConstant(Val, MVT::i32);
SDValue TargetConst0 = CurDAG->getTargetConstant(0, MVT::i32);
@ -556,8 +557,7 @@ SDNode *HexagonDAGToDAGISel::SelectIndexedLoad(LoadSDNode *LD, SDLoc dl) {
bool zextval = (LD->getExtensionType() == ISD::ZEXTLOAD);
// Figure out the opcode.
const HexagonInstrInfo *TII = static_cast<const HexagonInstrInfo *>(
TM.getSubtargetImpl()->getInstrInfo());
const HexagonInstrInfo *TII = Subtarget->getInstrInfo();
if (LoadedVT == MVT::i64) {
if (TII->isValidAutoIncImm(LoadedVT, Val))
Opcode = Hexagon::L2_loadrd_pi;
@ -666,8 +666,7 @@ SDNode *HexagonDAGToDAGISel::SelectIndexedStore(StoreSDNode *ST, SDLoc dl) {
// Offset value must be within representable range
// and must have correct alignment properties.
const HexagonInstrInfo *TII = static_cast<const HexagonInstrInfo *>(
TM.getSubtargetImpl()->getInstrInfo());
const HexagonInstrInfo *TII = Subtarget->getInstrInfo();
if (TII->isValidAutoIncImm(StoredVT, Val)) {
SDValue Ops[] = {Base, CurDAG->getTargetConstant(Val, MVT::i32), Value,
Chain};

40
llvm/lib/Target/Hexagon/HexagonOperands.td
View File

@ -517,7 +517,7 @@ def u0AlwaysExt : Operand<i32>;
// Predicates for constant extendable operands
def s16ExtPred : PatLeaf<(i32 imm), [{
int64_t v = (int64_t)N->getSExtValue();
if (!Subtarget.hasV4TOps())
if (!Subtarget->hasV4TOps())
// Return true if the immediate can fit in a 16-bit sign extended field.
return isInt<16>(v);
else {
@ -532,7 +532,7 @@ def s16ExtPred : PatLeaf<(i32 imm), [{
def s10ExtPred : PatLeaf<(i32 imm), [{
int64_t v = (int64_t)N->getSExtValue();
if (!Subtarget.hasV4TOps())
if (!Subtarget->hasV4TOps())
// Return true if the immediate can fit in a 10-bit sign extended field.
return isInt<10>(v);
else {
@ -547,7 +547,7 @@ def s10ExtPred : PatLeaf<(i32 imm), [{
def s9ExtPred : PatLeaf<(i32 imm), [{
int64_t v = (int64_t)N->getSExtValue();
if (!Subtarget.hasV4TOps())
if (!Subtarget->hasV4TOps())
// Return true if the immediate can fit in a 9-bit sign extended field.
return isInt<9>(v);
else {
@ -562,7 +562,7 @@ def s9ExtPred : PatLeaf<(i32 imm), [{
def s8ExtPred : PatLeaf<(i32 imm), [{
int64_t v = (int64_t)N->getSExtValue();
if (!Subtarget.hasV4TOps())
if (!Subtarget->hasV4TOps())
// Return true if the immediate can fit in a 8-bit sign extended field.
return isInt<8>(v);
else {
@ -577,7 +577,7 @@ def s8ExtPred : PatLeaf<(i32 imm), [{
def s8_16ExtPred : PatLeaf<(i32 imm), [{
int64_t v = (int64_t)N->getSExtValue();
if (!Subtarget.hasV4TOps())
if (!Subtarget->hasV4TOps())
// Return true if the immediate fits in a 8-bit sign extended field.
return isInt<8>(v);
else {
@ -593,7 +593,7 @@ def s8_16ExtPred : PatLeaf<(i32 imm), [{
def s6ExtPred : PatLeaf<(i32 imm), [{
int64_t v = (int64_t)N->getSExtValue();
if (!Subtarget.hasV4TOps())
if (!Subtarget->hasV4TOps())
// Return true if the immediate can fit in a 6-bit sign extended field.
return isInt<6>(v);
else {
@ -608,7 +608,7 @@ def s6ExtPred : PatLeaf<(i32 imm), [{
def s6_16ExtPred : PatLeaf<(i32 imm), [{
int64_t v = (int64_t)N->getSExtValue();
if (!Subtarget.hasV4TOps())
if (!Subtarget->hasV4TOps())
// Return true if the immediate fits in a 6-bit sign extended field.
return isInt<6>(v);
else {
@ -624,7 +624,7 @@ def s6_16ExtPred : PatLeaf<(i32 imm), [{
def s6_10ExtPred : PatLeaf<(i32 imm), [{
int64_t v = (int64_t)N->getSExtValue();
if (!Subtarget.hasV4TOps())
if (!Subtarget->hasV4TOps())
// Return true if the immediate can fit in a 6-bit sign extended field.
return isInt<6>(v);
else {
@ -640,7 +640,7 @@ def s6_10ExtPred : PatLeaf<(i32 imm), [{
def s11_0ExtPred : PatLeaf<(i32 imm), [{
int64_t v = (int64_t)N->getSExtValue();
if (!Subtarget.hasV4TOps())
if (!Subtarget->hasV4TOps())
// Return true if the immediate can fit in a 11-bit sign extended field.
return isShiftedInt<11,0>(v);
else {
@ -655,7 +655,7 @@ def s11_0ExtPred : PatLeaf<(i32 imm), [{
def s11_1ExtPred : PatLeaf<(i32 imm), [{
int64_t v = (int64_t)N->getSExtValue();
if (!Subtarget.hasV4TOps())
if (!Subtarget->hasV4TOps())
// Return true if the immediate can fit in a 12-bit sign extended field and
// is 2 byte aligned.
return isShiftedInt<11,1>(v);
@ -671,7 +671,7 @@ def s11_1ExtPred : PatLeaf<(i32 imm), [{
def s11_2ExtPred : PatLeaf<(i32 imm), [{
int64_t v = (int64_t)N->getSExtValue();
if (!Subtarget.hasV4TOps())
if (!Subtarget->hasV4TOps())
// Return true if the immediate can fit in a 13-bit sign extended field and
// is 4-byte aligned.
return isShiftedInt<11,2>(v);
@ -687,7 +687,7 @@ def s11_2ExtPred : PatLeaf<(i32 imm), [{
def s11_3ExtPred : PatLeaf<(i32 imm), [{
int64_t v = (int64_t)N->getSExtValue();
if (!Subtarget.hasV4TOps())
if (!Subtarget->hasV4TOps())
// Return true if the immediate can fit in a 14-bit sign extended field and
// is 8-byte aligned.
return isShiftedInt<11,3>(v);
@ -703,7 +703,7 @@ def s11_3ExtPred : PatLeaf<(i32 imm), [{
def u0AlwaysExtPred : PatLeaf<(i32 imm), [{
// Predicate for an unsigned 32-bit value that always needs to be extended.
if (Subtarget.hasV4TOps()) {
if (Subtarget->hasV4TOps()) {
if (isConstExtProfitable(Node)) {
int64_t v = (int64_t)N->getSExtValue();
return isUInt<32>(v);
@ -714,7 +714,7 @@ def u0AlwaysExtPred : PatLeaf<(i32 imm), [{
def u6ExtPred : PatLeaf<(i32 imm), [{
int64_t v = (int64_t)N->getSExtValue();
if (!Subtarget.hasV4TOps())
if (!Subtarget->hasV4TOps())
// Return true if the immediate can fit in a 6-bit unsigned field.
return isUInt<6>(v);
else {
@ -729,7 +729,7 @@ def u6ExtPred : PatLeaf<(i32 imm), [{
def u7ExtPred : PatLeaf<(i32 imm), [{
int64_t v = (int64_t)N->getSExtValue();
if (!Subtarget.hasV4TOps())
if (!Subtarget->hasV4TOps())
// Return true if the immediate can fit in a 7-bit unsigned field.
return isUInt<7>(v);
else {
@ -744,7 +744,7 @@ def u7ExtPred : PatLeaf<(i32 imm), [{
def u8ExtPred : PatLeaf<(i32 imm), [{
int64_t v = (int64_t)N->getSExtValue();
if (!Subtarget.hasV4TOps())
if (!Subtarget->hasV4TOps())
// Return true if the immediate can fit in a 8-bit unsigned field.
return isUInt<8>(v);
else {
@ -759,7 +759,7 @@ def u8ExtPred : PatLeaf<(i32 imm), [{
def u9ExtPred : PatLeaf<(i32 imm), [{
int64_t v = (int64_t)N->getSExtValue();
if (!Subtarget.hasV4TOps())
if (!Subtarget->hasV4TOps())
// Return true if the immediate can fit in a 9-bit unsigned field.
return isUInt<9>(v);
else {
@ -774,7 +774,7 @@ def u9ExtPred : PatLeaf<(i32 imm), [{
def u6_1ExtPred : PatLeaf<(i32 imm), [{
int64_t v = (int64_t)N->getSExtValue();
if (!Subtarget.hasV4TOps())
if (!Subtarget->hasV4TOps())
// Return true if the immediate can fit in a 7-bit unsigned field and
// is 2-byte aligned.
return isShiftedUInt<6,1>(v);
@ -790,7 +790,7 @@ def u6_1ExtPred : PatLeaf<(i32 imm), [{
def u6_2ExtPred : PatLeaf<(i32 imm), [{
int64_t v = (int64_t)N->getSExtValue();
if (!Subtarget.hasV4TOps())
if (!Subtarget->hasV4TOps())
// Return true if the immediate can fit in a 8-bit unsigned field and
// is 4-byte aligned.
return isShiftedUInt<6,2>(v);
@ -806,7 +806,7 @@ def u6_2ExtPred : PatLeaf<(i32 imm), [{
def u6_3ExtPred : PatLeaf<(i32 imm), [{
int64_t v = (int64_t)N->getSExtValue();
if (!Subtarget.hasV4TOps())
if (!Subtarget->hasV4TOps())
// Return true if the immediate can fit in a 9-bit unsigned field and
// is 8-byte aligned.
return isShiftedUInt<6,3>(v);