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[X86] Replace some default cases in X86SelectShift with llvm_unreachable. 

llvm-svn: 316839
This commit is contained in:
Craig Topper 2017-10-28 19:56:56 +00:00
parent 0f759db2bd
commit 202b559ae0
1 changed files with 3 additions and 3 deletions
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6
llvm/lib/Target/X86/X86FastISel.cpp
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@ -1791,28 +1791,28 @@ bool X86FastISel::X86SelectShift(const Instruction *I) {
CReg = X86::CX;
RC = &X86::GR16RegClass;
switch (I->getOpcode()) {
default: llvm_unreachable("Unexpected shift opcode");
case Instruction::LShr: OpReg = X86::SHR16rCL; break;
case Instruction::AShr: OpReg = X86::SAR16rCL; break;
case Instruction::Shl: OpReg = X86::SHL16rCL; break;
default: return false;
}
} else if (I->getType()->isIntegerTy(32)) {
CReg = X86::ECX;
RC = &X86::GR32RegClass;
switch (I->getOpcode()) {
default: llvm_unreachable("Unexpected shift opcode");
case Instruction::LShr: OpReg = X86::SHR32rCL; break;
case Instruction::AShr: OpReg = X86::SAR32rCL; break;
case Instruction::Shl: OpReg = X86::SHL32rCL; break;
default: return false;
}
} else if (I->getType()->isIntegerTy(64)) {
CReg = X86::RCX;
RC = &X86::GR64RegClass;
switch (I->getOpcode()) {
default: llvm_unreachable("Unexpected shift opcode");
case Instruction::LShr: OpReg = X86::SHR64rCL; break;
case Instruction::AShr: OpReg = X86::SAR64rCL; break;
case Instruction::Shl: OpReg = X86::SHL64rCL; break;
default: return false;
}
} else {
return false;