forked from OSchip/llvm-project
Adjust a test that's expecting optimizations to be done
on MMX palignr; we don't do this for the intrinsics. llvm-svn: 113234
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@ -17,13 +17,13 @@ int4 align4(int4 a, int4 b) { return _mm_alignr_epi8(a, b, 32); }
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#define _mm_alignr_pi8(a, b, n) (__builtin_ia32_palignr((a), (b), (n)))
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typedef __attribute__((vector_size(8))) int int2;
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// CHECK-NOT: palignr
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// CHECK: palignr
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int2 align5(int2 a, int2 b) { return _mm_alignr_pi8(a, b, 8); }
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// CHECK: psrlq
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// CHECK: palignr
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int2 align6(int2 a, int2 b) { return _mm_alignr_pi8(a, b, 9); }
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// CHECK: xor
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// CHECK: palignr
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int2 align7(int2 a, int2 b) { return _mm_alignr_pi8(a, b, 16); }
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// CHECK: palignr
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