forked from OSchip/llvm-project
[TargetLowering] Use IRBuilderBase instead of IRBuilder<> (NFC)
Don't require a specific kind of IRBuilder for TargetLowering hooks. This allows us to drop the IRBuilder.h include from TargetLowering.h. Differential Revision: https://reviews.llvm.org/D103759
This commit is contained in:
parent
85dfb377dd
commit
1ffa6499ea
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@ -40,7 +40,6 @@
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#include "llvm/IR/DataLayout.h"
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#include "llvm/IR/DataLayout.h"
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#include "llvm/IR/DerivedTypes.h"
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#include "llvm/IR/DerivedTypes.h"
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#include "llvm/IR/Function.h"
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#include "llvm/IR/Function.h"
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#include "llvm/IR/IRBuilder.h"
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#include "llvm/IR/InlineAsm.h"
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#include "llvm/IR/InlineAsm.h"
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#include "llvm/IR/Instruction.h"
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#include "llvm/IR/Instruction.h"
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#include "llvm/IR/Instructions.h"
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#include "llvm/IR/Instructions.h"
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@ -72,6 +71,7 @@ class FunctionLoweringInfo;
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class GlobalValue;
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class GlobalValue;
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class GISelKnownBits;
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class GISelKnownBits;
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class IntrinsicInst;
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class IntrinsicInst;
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class IRBuilderBase;
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struct KnownBits;
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struct KnownBits;
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class LegacyDivergenceAnalysis;
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class LegacyDivergenceAnalysis;
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class LLVMContext;
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class LLVMContext;
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@ -1770,7 +1770,7 @@ public:
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/// returns the address of that location. Otherwise, returns nullptr.
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/// returns the address of that location. Otherwise, returns nullptr.
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/// DEPRECATED: please override useLoadStackGuardNode and customize
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/// DEPRECATED: please override useLoadStackGuardNode and customize
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/// LOAD_STACK_GUARD, or customize \@llvm.stackguard().
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/// LOAD_STACK_GUARD, or customize \@llvm.stackguard().
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virtual Value *getIRStackGuard(IRBuilder<> &IRB) const;
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virtual Value *getIRStackGuard(IRBuilderBase &IRB) const;
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/// Inserts necessary declarations for SSP (stack protection) purpose.
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/// Inserts necessary declarations for SSP (stack protection) purpose.
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/// Should be used only when getIRStackGuard returns nullptr.
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/// Should be used only when getIRStackGuard returns nullptr.
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@ -1800,12 +1800,12 @@ public:
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}
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}
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protected:
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protected:
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Value *getDefaultSafeStackPointerLocation(IRBuilder<> &IRB,
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Value *getDefaultSafeStackPointerLocation(IRBuilderBase &IRB,
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bool UseTLS) const;
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bool UseTLS) const;
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public:
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public:
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/// Returns the target-specific address of the unsafe stack pointer.
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/// Returns the target-specific address of the unsafe stack pointer.
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virtual Value *getSafeStackPointerLocation(IRBuilder<> &IRB) const;
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virtual Value *getSafeStackPointerLocation(IRBuilderBase &IRB) const;
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/// Returns the name of the symbol used to emit stack probes or the empty
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/// Returns the name of the symbol used to emit stack probes or the empty
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/// string if not applicable.
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/// string if not applicable.
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@ -1879,14 +1879,14 @@ public:
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/// corresponding pointee type. This may entail some non-trivial operations to
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/// corresponding pointee type. This may entail some non-trivial operations to
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/// truncate or reconstruct types that will be illegal in the backend. See
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/// truncate or reconstruct types that will be illegal in the backend. See
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/// ARMISelLowering for an example implementation.
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/// ARMISelLowering for an example implementation.
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virtual Value *emitLoadLinked(IRBuilder<> &Builder, Value *Addr,
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virtual Value *emitLoadLinked(IRBuilderBase &Builder, Value *Addr,
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AtomicOrdering Ord) const {
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AtomicOrdering Ord) const {
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llvm_unreachable("Load linked unimplemented on this target");
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llvm_unreachable("Load linked unimplemented on this target");
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}
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}
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/// Perform a store-conditional operation to Addr. Return the status of the
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/// Perform a store-conditional operation to Addr. Return the status of the
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/// store. This should be 0 if the store succeeded, non-zero otherwise.
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/// store. This should be 0 if the store succeeded, non-zero otherwise.
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virtual Value *emitStoreConditional(IRBuilder<> &Builder, Value *Val,
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virtual Value *emitStoreConditional(IRBuilderBase &Builder, Value *Val,
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Value *Addr, AtomicOrdering Ord) const {
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Value *Addr, AtomicOrdering Ord) const {
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llvm_unreachable("Store conditional unimplemented on this target");
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llvm_unreachable("Store conditional unimplemented on this target");
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}
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}
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@ -1894,7 +1894,7 @@ public:
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/// Perform a masked atomicrmw using a target-specific intrinsic. This
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/// Perform a masked atomicrmw using a target-specific intrinsic. This
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/// represents the core LL/SC loop which will be lowered at a late stage by
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/// represents the core LL/SC loop which will be lowered at a late stage by
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/// the backend.
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/// the backend.
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virtual Value *emitMaskedAtomicRMWIntrinsic(IRBuilder<> &Builder,
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virtual Value *emitMaskedAtomicRMWIntrinsic(IRBuilderBase &Builder,
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AtomicRMWInst *AI,
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AtomicRMWInst *AI,
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Value *AlignedAddr, Value *Incr,
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Value *AlignedAddr, Value *Incr,
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Value *Mask, Value *ShiftAmt,
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Value *Mask, Value *ShiftAmt,
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@ -1906,7 +1906,7 @@ public:
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/// represents the core LL/SC loop which will be lowered at a late stage by
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/// represents the core LL/SC loop which will be lowered at a late stage by
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/// the backend.
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/// the backend.
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virtual Value *emitMaskedAtomicCmpXchgIntrinsic(
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virtual Value *emitMaskedAtomicCmpXchgIntrinsic(
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IRBuilder<> &Builder, AtomicCmpXchgInst *CI, Value *AlignedAddr,
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IRBuilderBase &Builder, AtomicCmpXchgInst *CI, Value *AlignedAddr,
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Value *CmpVal, Value *NewVal, Value *Mask, AtomicOrdering Ord) const {
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Value *CmpVal, Value *NewVal, Value *Mask, AtomicOrdering Ord) const {
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llvm_unreachable("Masked cmpxchg expansion unimplemented on this target");
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llvm_unreachable("Masked cmpxchg expansion unimplemented on this target");
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}
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}
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@ -1944,10 +1944,11 @@ public:
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/// seq_cst. But if they are lowered to monotonic accesses, no amount of
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/// seq_cst. But if they are lowered to monotonic accesses, no amount of
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/// IR-level fences can prevent it.
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/// IR-level fences can prevent it.
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/// @{
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/// @{
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virtual Instruction *emitLeadingFence(IRBuilder<> &Builder, Instruction *Inst,
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virtual Instruction *emitLeadingFence(IRBuilderBase &Builder,
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Instruction *Inst,
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AtomicOrdering Ord) const;
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AtomicOrdering Ord) const;
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virtual Instruction *emitTrailingFence(IRBuilder<> &Builder,
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virtual Instruction *emitTrailingFence(IRBuilderBase &Builder,
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Instruction *Inst,
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Instruction *Inst,
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AtomicOrdering Ord) const;
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AtomicOrdering Ord) const;
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/// @}
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/// @}
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@ -1958,7 +1959,7 @@ public:
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// a dedicated instruction, if desired.
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// a dedicated instruction, if desired.
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// E.g., on ARM, if ldrex isn't followed by strex, the exclusive monitor would
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// E.g., on ARM, if ldrex isn't followed by strex, the exclusive monitor would
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// be unnecessarily held, except if clrex, inserted by this hook, is executed.
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// be unnecessarily held, except if clrex, inserted by this hook, is executed.
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virtual void emitAtomicCmpXchgNoStoreLLBalance(IRBuilder<> &Builder) const {}
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virtual void emitAtomicCmpXchgNoStoreLLBalance(IRBuilderBase &Builder) const {}
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/// Returns true if the given (atomic) store should be expanded by the
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/// Returns true if the given (atomic) store should be expanded by the
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/// IR-level AtomicExpand pass into an "atomic xchg" which ignores its input.
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/// IR-level AtomicExpand pass into an "atomic xchg" which ignores its input.
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@ -1860,8 +1860,9 @@ TargetLoweringBase::getTypeLegalizationCost(const DataLayout &DL,
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}
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}
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}
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}
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Value *TargetLoweringBase::getDefaultSafeStackPointerLocation(IRBuilder<> &IRB,
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Value *
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bool UseTLS) const {
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TargetLoweringBase::getDefaultSafeStackPointerLocation(IRBuilderBase &IRB,
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bool UseTLS) const {
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// compiler-rt provides a variable with a magic name. Targets that do not
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// compiler-rt provides a variable with a magic name. Targets that do not
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// link with compiler-rt may also provide such a variable.
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// link with compiler-rt may also provide such a variable.
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Module *M = IRB.GetInsertBlock()->getParent()->getParent();
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Module *M = IRB.GetInsertBlock()->getParent()->getParent();
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@ -1892,7 +1893,8 @@ Value *TargetLoweringBase::getDefaultSafeStackPointerLocation(IRBuilder<> &IRB,
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return UnsafeStackPtr;
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return UnsafeStackPtr;
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}
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}
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Value *TargetLoweringBase::getSafeStackPointerLocation(IRBuilder<> &IRB) const {
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Value *
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TargetLoweringBase::getSafeStackPointerLocation(IRBuilderBase &IRB) const {
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if (!TM.getTargetTriple().isAndroid())
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if (!TM.getTargetTriple().isAndroid())
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return getDefaultSafeStackPointerLocation(IRB, true);
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return getDefaultSafeStackPointerLocation(IRB, true);
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@ -1952,7 +1954,7 @@ bool TargetLoweringBase::isLegalAddressingMode(const DataLayout &DL,
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// For OpenBSD return its special guard variable. Otherwise return nullptr,
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// For OpenBSD return its special guard variable. Otherwise return nullptr,
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// so that SelectionDAG handle SSP.
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// so that SelectionDAG handle SSP.
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Value *TargetLoweringBase::getIRStackGuard(IRBuilder<> &IRB) const {
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Value *TargetLoweringBase::getIRStackGuard(IRBuilderBase &IRB) const {
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if (getTargetMachine().getTargetTriple().isOSOpenBSD()) {
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if (getTargetMachine().getTargetTriple().isOSOpenBSD()) {
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Module &M = *IRB.GetInsertBlock()->getParent()->getParent();
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Module &M = *IRB.GetInsertBlock()->getParent()->getParent();
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PointerType *PtrTy = Type::getInt8PtrTy(M.getContext());
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PointerType *PtrTy = Type::getInt8PtrTy(M.getContext());
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@ -2254,7 +2256,7 @@ TargetLoweringBase::getAtomicMemOperandFlags(const Instruction &AI,
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return Flags;
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return Flags;
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}
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}
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Instruction *TargetLoweringBase::emitLeadingFence(IRBuilder<> &Builder,
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Instruction *TargetLoweringBase::emitLeadingFence(IRBuilderBase &Builder,
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Instruction *Inst,
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Instruction *Inst,
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AtomicOrdering Ord) const {
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AtomicOrdering Ord) const {
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if (isReleaseOrStronger(Ord) && Inst->hasAtomicStore())
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if (isReleaseOrStronger(Ord) && Inst->hasAtomicStore())
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@ -2263,7 +2265,7 @@ Instruction *TargetLoweringBase::emitLeadingFence(IRBuilder<> &Builder,
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return nullptr;
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return nullptr;
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}
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}
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Instruction *TargetLoweringBase::emitTrailingFence(IRBuilder<> &Builder,
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Instruction *TargetLoweringBase::emitTrailingFence(IRBuilderBase &Builder,
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Instruction *Inst,
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Instruction *Inst,
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AtomicOrdering Ord) const {
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AtomicOrdering Ord) const {
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if (isAcquireOrStronger(Ord))
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if (isAcquireOrStronger(Ord))
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@ -17025,7 +17025,8 @@ AArch64TargetLowering::shouldExpandAtomicCmpXchgInIR(
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return AtomicExpansionKind::LLSC;
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return AtomicExpansionKind::LLSC;
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}
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}
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Value *AArch64TargetLowering::emitLoadLinked(IRBuilder<> &Builder, Value *Addr,
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Value *AArch64TargetLowering::emitLoadLinked(IRBuilderBase &Builder,
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Value *Addr,
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AtomicOrdering Ord) const {
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AtomicOrdering Ord) const {
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Module *M = Builder.GetInsertBlock()->getParent()->getParent();
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Module *M = Builder.GetInsertBlock()->getParent()->getParent();
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Type *ValTy = cast<PointerType>(Addr->getType())->getElementType();
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Type *ValTy = cast<PointerType>(Addr->getType())->getElementType();
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}
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}
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void AArch64TargetLowering::emitAtomicCmpXchgNoStoreLLBalance(
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void AArch64TargetLowering::emitAtomicCmpXchgNoStoreLLBalance(
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IRBuilder<> &Builder) const {
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IRBuilderBase &Builder) const {
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Module *M = Builder.GetInsertBlock()->getParent()->getParent();
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Module *M = Builder.GetInsertBlock()->getParent()->getParent();
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Builder.CreateCall(Intrinsic::getDeclaration(M, Intrinsic::aarch64_clrex));
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Builder.CreateCall(Intrinsic::getDeclaration(M, Intrinsic::aarch64_clrex));
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}
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}
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Value *AArch64TargetLowering::emitStoreConditional(IRBuilder<> &Builder,
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Value *AArch64TargetLowering::emitStoreConditional(IRBuilderBase &Builder,
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Value *Val, Value *Addr,
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Value *Val, Value *Addr,
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AtomicOrdering Ord) const {
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AtomicOrdering Ord) const {
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Module *M = Builder.GetInsertBlock()->getParent()->getParent();
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Module *M = Builder.GetInsertBlock()->getParent()->getParent();
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return false;
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return false;
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}
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}
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static Value *UseTlsOffset(IRBuilder<> &IRB, unsigned Offset) {
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static Value *UseTlsOffset(IRBuilderBase &IRB, unsigned Offset) {
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Module *M = IRB.GetInsertBlock()->getParent()->getParent();
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Module *M = IRB.GetInsertBlock()->getParent()->getParent();
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Function *ThreadPointerFunc =
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Function *ThreadPointerFunc =
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Intrinsic::getDeclaration(M, Intrinsic::thread_pointer);
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Intrinsic::getDeclaration(M, Intrinsic::thread_pointer);
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IRB.getInt8PtrTy()->getPointerTo(0));
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IRB.getInt8PtrTy()->getPointerTo(0));
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}
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}
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Value *AArch64TargetLowering::getIRStackGuard(IRBuilder<> &IRB) const {
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Value *AArch64TargetLowering::getIRStackGuard(IRBuilderBase &IRB) const {
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// Android provides a fixed TLS slot for the stack cookie. See the definition
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// Android provides a fixed TLS slot for the stack cookie. See the definition
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// of TLS_SLOT_STACK_GUARD in
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// of TLS_SLOT_STACK_GUARD in
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// https://android.googlesource.com/platform/bionic/+/master/libc/private/bionic_tls.h
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// https://android.googlesource.com/platform/bionic/+/master/libc/private/bionic_tls.h
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@ -17182,7 +17183,8 @@ Function *AArch64TargetLowering::getSSPStackGuardCheck(const Module &M) const {
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return TargetLowering::getSSPStackGuardCheck(M);
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return TargetLowering::getSSPStackGuardCheck(M);
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}
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}
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Value *AArch64TargetLowering::getSafeStackPointerLocation(IRBuilder<> &IRB) const {
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Value *
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AArch64TargetLowering::getSafeStackPointerLocation(IRBuilderBase &IRB) const {
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// Android provides a fixed TLS slot for the SafeStack pointer. See the
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// Android provides a fixed TLS slot for the SafeStack pointer. See the
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// definition of TLS_SLOT_SAFESTACK in
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// definition of TLS_SLOT_SAFESTACK in
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// https://android.googlesource.com/platform/bionic/+/master/libc/private/bionic_tls.h
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// https://android.googlesource.com/platform/bionic/+/master/libc/private/bionic_tls.h
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return TargetLowering::shouldFormOverflowOp(Opcode, VT, true);
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return TargetLowering::shouldFormOverflowOp(Opcode, VT, true);
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}
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}
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Value *emitLoadLinked(IRBuilder<> &Builder, Value *Addr,
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Value *emitLoadLinked(IRBuilderBase &Builder, Value *Addr,
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AtomicOrdering Ord) const override;
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AtomicOrdering Ord) const override;
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Value *emitStoreConditional(IRBuilder<> &Builder, Value *Val,
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Value *emitStoreConditional(IRBuilderBase &Builder, Value *Val, Value *Addr,
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Value *Addr, AtomicOrdering Ord) const override;
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AtomicOrdering Ord) const override;
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void emitAtomicCmpXchgNoStoreLLBalance(IRBuilder<> &Builder) const override;
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void emitAtomicCmpXchgNoStoreLLBalance(IRBuilderBase &Builder) const override;
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TargetLoweringBase::AtomicExpansionKind
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TargetLoweringBase::AtomicExpansionKind
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shouldExpandAtomicLoadInIR(LoadInst *LI) const override;
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shouldExpandAtomicLoadInIR(LoadInst *LI) const override;
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/// If the target has a standard location for the stack protector cookie,
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/// If the target has a standard location for the stack protector cookie,
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/// returns the address of that location. Otherwise, returns nullptr.
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/// returns the address of that location. Otherwise, returns nullptr.
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Value *getIRStackGuard(IRBuilder<> &IRB) const override;
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Value *getIRStackGuard(IRBuilderBase &IRB) const override;
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void insertSSPDeclarations(Module &M) const override;
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void insertSSPDeclarations(Module &M) const override;
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Value *getSDagStackGuard(const Module &M) const override;
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Value *getSDagStackGuard(const Module &M) const override;
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/// If the target has a standard location for the unsafe stack pointer,
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/// If the target has a standard location for the unsafe stack pointer,
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/// returns the address of that location. Otherwise, returns nullptr.
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/// returns the address of that location. Otherwise, returns nullptr.
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Value *getSafeStackPointerLocation(IRBuilder<> &IRB) const override;
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Value *getSafeStackPointerLocation(IRBuilderBase &IRB) const override;
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/// If a physical register, this returns the register that receives the
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/// If a physical register, this returns the register that receives the
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/// exception address on entry to an EH pad.
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/// exception address on entry to an EH pad.
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@ -19381,7 +19381,7 @@ bool ARMTargetLowering::isExtractSubvectorCheap(EVT ResVT, EVT SrcVT,
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return (Index == 0 || Index == ResVT.getVectorNumElements());
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return (Index == 0 || Index == ResVT.getVectorNumElements());
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}
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}
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Instruction* ARMTargetLowering::makeDMB(IRBuilder<> &Builder,
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Instruction *ARMTargetLowering::makeDMB(IRBuilderBase &Builder,
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ARM_MB::MemBOpt Domain) const {
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ARM_MB::MemBOpt Domain) const {
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Module *M = Builder.GetInsertBlock()->getParent()->getParent();
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Module *M = Builder.GetInsertBlock()->getParent()->getParent();
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@ -19411,7 +19411,7 @@ Instruction* ARMTargetLowering::makeDMB(IRBuilder<> &Builder,
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}
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}
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// Based on http://www.cl.cam.ac.uk/~pes20/cpp/cpp0xmappings.html
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// Based on http://www.cl.cam.ac.uk/~pes20/cpp/cpp0xmappings.html
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Instruction *ARMTargetLowering::emitLeadingFence(IRBuilder<> &Builder,
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Instruction *ARMTargetLowering::emitLeadingFence(IRBuilderBase &Builder,
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Instruction *Inst,
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Instruction *Inst,
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AtomicOrdering Ord) const {
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AtomicOrdering Ord) const {
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switch (Ord) {
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switch (Ord) {
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@ -19436,7 +19436,7 @@ Instruction *ARMTargetLowering::emitLeadingFence(IRBuilder<> &Builder,
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llvm_unreachable("Unknown fence ordering in emitLeadingFence");
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llvm_unreachable("Unknown fence ordering in emitLeadingFence");
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}
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}
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Instruction *ARMTargetLowering::emitTrailingFence(IRBuilder<> &Builder,
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Instruction *ARMTargetLowering::emitTrailingFence(IRBuilderBase &Builder,
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Instruction *Inst,
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Instruction *Inst,
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AtomicOrdering Ord) const {
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AtomicOrdering Ord) const {
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switch (Ord) {
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switch (Ord) {
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@ -19598,7 +19598,7 @@ bool ARMTargetLowering::shouldExpandShift(SelectionDAG &DAG, SDNode *N) const {
|
||||||
return !Subtarget->hasMinSize() || Subtarget->isTargetWindows();
|
return !Subtarget->hasMinSize() || Subtarget->isTargetWindows();
|
||||||
}
|
}
|
||||||
|
|
||||||
Value *ARMTargetLowering::emitLoadLinked(IRBuilder<> &Builder, Value *Addr,
|
Value *ARMTargetLowering::emitLoadLinked(IRBuilderBase &Builder, Value *Addr,
|
||||||
AtomicOrdering Ord) const {
|
AtomicOrdering Ord) const {
|
||||||
Module *M = Builder.GetInsertBlock()->getParent()->getParent();
|
Module *M = Builder.GetInsertBlock()->getParent()->getParent();
|
||||||
Type *ValTy = cast<PointerType>(Addr->getType())->getElementType();
|
Type *ValTy = cast<PointerType>(Addr->getType())->getElementType();
|
||||||
|
@ -19635,15 +19635,15 @@ Value *ARMTargetLowering::emitLoadLinked(IRBuilder<> &Builder, Value *Addr,
|
||||||
}
|
}
|
||||||
|
|
||||||
void ARMTargetLowering::emitAtomicCmpXchgNoStoreLLBalance(
|
void ARMTargetLowering::emitAtomicCmpXchgNoStoreLLBalance(
|
||||||
IRBuilder<> &Builder) const {
|
IRBuilderBase &Builder) const {
|
||||||
if (!Subtarget->hasV7Ops())
|
if (!Subtarget->hasV7Ops())
|
||||||
return;
|
return;
|
||||||
Module *M = Builder.GetInsertBlock()->getParent()->getParent();
|
Module *M = Builder.GetInsertBlock()->getParent()->getParent();
|
||||||
Builder.CreateCall(Intrinsic::getDeclaration(M, Intrinsic::arm_clrex));
|
Builder.CreateCall(Intrinsic::getDeclaration(M, Intrinsic::arm_clrex));
|
||||||
}
|
}
|
||||||
|
|
||||||
Value *ARMTargetLowering::emitStoreConditional(IRBuilder<> &Builder, Value *Val,
|
Value *ARMTargetLowering::emitStoreConditional(IRBuilderBase &Builder,
|
||||||
Value *Addr,
|
Value *Val, Value *Addr,
|
||||||
AtomicOrdering Ord) const {
|
AtomicOrdering Ord) const {
|
||||||
Module *M = Builder.GetInsertBlock()->getParent()->getParent();
|
Module *M = Builder.GetInsertBlock()->getParent()->getParent();
|
||||||
bool IsRelease = isReleaseOrStronger(Ord);
|
bool IsRelease = isReleaseOrStronger(Ord);
|
||||||
|
|
|
@ -627,17 +627,18 @@ class VectorType;
|
||||||
Register
|
Register
|
||||||
getExceptionSelectorRegister(const Constant *PersonalityFn) const override;
|
getExceptionSelectorRegister(const Constant *PersonalityFn) const override;
|
||||||
|
|
||||||
Instruction *makeDMB(IRBuilder<> &Builder, ARM_MB::MemBOpt Domain) const;
|
Instruction *makeDMB(IRBuilderBase &Builder, ARM_MB::MemBOpt Domain) const;
|
||||||
Value *emitLoadLinked(IRBuilder<> &Builder, Value *Addr,
|
Value *emitLoadLinked(IRBuilderBase &Builder, Value *Addr,
|
||||||
AtomicOrdering Ord) const override;
|
AtomicOrdering Ord) const override;
|
||||||
Value *emitStoreConditional(IRBuilder<> &Builder, Value *Val,
|
Value *emitStoreConditional(IRBuilderBase &Builder, Value *Val, Value *Addr,
|
||||||
Value *Addr, AtomicOrdering Ord) const override;
|
AtomicOrdering Ord) const override;
|
||||||
|
|
||||||
void emitAtomicCmpXchgNoStoreLLBalance(IRBuilder<> &Builder) const override;
|
void
|
||||||
|
emitAtomicCmpXchgNoStoreLLBalance(IRBuilderBase &Builder) const override;
|
||||||
|
|
||||||
Instruction *emitLeadingFence(IRBuilder<> &Builder, Instruction *Inst,
|
Instruction *emitLeadingFence(IRBuilderBase &Builder, Instruction *Inst,
|
||||||
AtomicOrdering Ord) const override;
|
AtomicOrdering Ord) const override;
|
||||||
Instruction *emitTrailingFence(IRBuilder<> &Builder, Instruction *Inst,
|
Instruction *emitTrailingFence(IRBuilderBase &Builder, Instruction *Inst,
|
||||||
AtomicOrdering Ord) const override;
|
AtomicOrdering Ord) const override;
|
||||||
|
|
||||||
unsigned getMaxSupportedInterleaveFactor() const override;
|
unsigned getMaxSupportedInterleaveFactor() const override;
|
||||||
|
|
|
@ -3554,8 +3554,9 @@ bool HexagonTargetLowering::shouldReduceLoadWidth(SDNode *Load,
|
||||||
return true;
|
return true;
|
||||||
}
|
}
|
||||||
|
|
||||||
Value *HexagonTargetLowering::emitLoadLinked(IRBuilder<> &Builder, Value *Addr,
|
Value *HexagonTargetLowering::emitLoadLinked(IRBuilderBase &Builder,
|
||||||
AtomicOrdering Ord) const {
|
Value *Addr,
|
||||||
|
AtomicOrdering Ord) const {
|
||||||
BasicBlock *BB = Builder.GetInsertBlock();
|
BasicBlock *BB = Builder.GetInsertBlock();
|
||||||
Module *M = BB->getParent()->getParent();
|
Module *M = BB->getParent()->getParent();
|
||||||
auto PT = cast<PointerType>(Addr->getType());
|
auto PT = cast<PointerType>(Addr->getType());
|
||||||
|
@ -3577,8 +3578,9 @@ Value *HexagonTargetLowering::emitLoadLinked(IRBuilder<> &Builder, Value *Addr,
|
||||||
|
|
||||||
/// Perform a store-conditional operation to Addr. Return the status of the
|
/// Perform a store-conditional operation to Addr. Return the status of the
|
||||||
/// store. This should be 0 if the store succeeded, non-zero otherwise.
|
/// store. This should be 0 if the store succeeded, non-zero otherwise.
|
||||||
Value *HexagonTargetLowering::emitStoreConditional(IRBuilder<> &Builder,
|
Value *HexagonTargetLowering::emitStoreConditional(IRBuilderBase &Builder,
|
||||||
Value *Val, Value *Addr, AtomicOrdering Ord) const {
|
Value *Val, Value *Addr,
|
||||||
|
AtomicOrdering Ord) const {
|
||||||
BasicBlock *BB = Builder.GetInsertBlock();
|
BasicBlock *BB = Builder.GetInsertBlock();
|
||||||
Module *M = BB->getParent()->getParent();
|
Module *M = BB->getParent()->getParent();
|
||||||
Type *Ty = Val->getType();
|
Type *Ty = Val->getType();
|
||||||
|
|
|
@ -323,10 +323,10 @@ public:
|
||||||
EVT NewVT) const override;
|
EVT NewVT) const override;
|
||||||
|
|
||||||
// Handling of atomic RMW instructions.
|
// Handling of atomic RMW instructions.
|
||||||
Value *emitLoadLinked(IRBuilder<> &Builder, Value *Addr,
|
Value *emitLoadLinked(IRBuilderBase &Builder, Value *Addr,
|
||||||
AtomicOrdering Ord) const override;
|
AtomicOrdering Ord) const override;
|
||||||
Value *emitStoreConditional(IRBuilder<> &Builder, Value *Val,
|
Value *emitStoreConditional(IRBuilderBase &Builder, Value *Val, Value *Addr,
|
||||||
Value *Addr, AtomicOrdering Ord) const override;
|
AtomicOrdering Ord) const override;
|
||||||
AtomicExpansionKind shouldExpandAtomicLoadInIR(LoadInst *LI) const override;
|
AtomicExpansionKind shouldExpandAtomicLoadInIR(LoadInst *LI) const override;
|
||||||
bool shouldExpandAtomicStoreInIR(StoreInst *SI) const override;
|
bool shouldExpandAtomicStoreInIR(StoreInst *SI) const override;
|
||||||
AtomicExpansionKind
|
AtomicExpansionKind
|
||||||
|
|
|
@ -10946,7 +10946,7 @@ void PPCTargetLowering::ReplaceNodeResults(SDNode *N,
|
||||||
// Other Lowering Code
|
// Other Lowering Code
|
||||||
//===----------------------------------------------------------------------===//
|
//===----------------------------------------------------------------------===//
|
||||||
|
|
||||||
static Instruction* callIntrinsic(IRBuilder<> &Builder, Intrinsic::ID Id) {
|
static Instruction *callIntrinsic(IRBuilderBase &Builder, Intrinsic::ID Id) {
|
||||||
Module *M = Builder.GetInsertBlock()->getParent()->getParent();
|
Module *M = Builder.GetInsertBlock()->getParent()->getParent();
|
||||||
Function *Func = Intrinsic::getDeclaration(M, Id);
|
Function *Func = Intrinsic::getDeclaration(M, Id);
|
||||||
return Builder.CreateCall(Func, {});
|
return Builder.CreateCall(Func, {});
|
||||||
|
@ -10954,7 +10954,7 @@ static Instruction* callIntrinsic(IRBuilder<> &Builder, Intrinsic::ID Id) {
|
||||||
|
|
||||||
// The mappings for emitLeading/TrailingFence is taken from
|
// The mappings for emitLeading/TrailingFence is taken from
|
||||||
// http://www.cl.cam.ac.uk/~pes20/cpp/cpp0xmappings.html
|
// http://www.cl.cam.ac.uk/~pes20/cpp/cpp0xmappings.html
|
||||||
Instruction *PPCTargetLowering::emitLeadingFence(IRBuilder<> &Builder,
|
Instruction *PPCTargetLowering::emitLeadingFence(IRBuilderBase &Builder,
|
||||||
Instruction *Inst,
|
Instruction *Inst,
|
||||||
AtomicOrdering Ord) const {
|
AtomicOrdering Ord) const {
|
||||||
if (Ord == AtomicOrdering::SequentiallyConsistent)
|
if (Ord == AtomicOrdering::SequentiallyConsistent)
|
||||||
|
@ -10964,7 +10964,7 @@ Instruction *PPCTargetLowering::emitLeadingFence(IRBuilder<> &Builder,
|
||||||
return nullptr;
|
return nullptr;
|
||||||
}
|
}
|
||||||
|
|
||||||
Instruction *PPCTargetLowering::emitTrailingFence(IRBuilder<> &Builder,
|
Instruction *PPCTargetLowering::emitTrailingFence(IRBuilderBase &Builder,
|
||||||
Instruction *Inst,
|
Instruction *Inst,
|
||||||
AtomicOrdering Ord) const {
|
AtomicOrdering Ord) const {
|
||||||
if (Inst->hasAtomicLoad() && isAcquireOrStronger(Ord)) {
|
if (Inst->hasAtomicLoad() && isAcquireOrStronger(Ord)) {
|
||||||
|
@ -17370,4 +17370,4 @@ CCAssignFn *PPCTargetLowering::ccAssignFnForCall(CallingConv::ID CC,
|
||||||
default:
|
default:
|
||||||
return CC_PPC64_ELF_FIS;
|
return CC_PPC64_ELF_FIS;
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
|
@ -871,9 +871,9 @@ namespace llvm {
|
||||||
return true;
|
return true;
|
||||||
}
|
}
|
||||||
|
|
||||||
Instruction *emitLeadingFence(IRBuilder<> &Builder, Instruction *Inst,
|
Instruction *emitLeadingFence(IRBuilderBase &Builder, Instruction *Inst,
|
||||||
AtomicOrdering Ord) const override;
|
AtomicOrdering Ord) const override;
|
||||||
Instruction *emitTrailingFence(IRBuilder<> &Builder, Instruction *Inst,
|
Instruction *emitTrailingFence(IRBuilderBase &Builder, Instruction *Inst,
|
||||||
AtomicOrdering Ord) const override;
|
AtomicOrdering Ord) const override;
|
||||||
|
|
||||||
MachineBasicBlock *
|
MachineBasicBlock *
|
||||||
|
|
|
@ -8239,7 +8239,7 @@ void RISCVTargetLowering::LowerAsmOperandForConstraint(
|
||||||
TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
|
TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
|
||||||
}
|
}
|
||||||
|
|
||||||
Instruction *RISCVTargetLowering::emitLeadingFence(IRBuilder<> &Builder,
|
Instruction *RISCVTargetLowering::emitLeadingFence(IRBuilderBase &Builder,
|
||||||
Instruction *Inst,
|
Instruction *Inst,
|
||||||
AtomicOrdering Ord) const {
|
AtomicOrdering Ord) const {
|
||||||
if (isa<LoadInst>(Inst) && Ord == AtomicOrdering::SequentiallyConsistent)
|
if (isa<LoadInst>(Inst) && Ord == AtomicOrdering::SequentiallyConsistent)
|
||||||
|
@ -8249,7 +8249,7 @@ Instruction *RISCVTargetLowering::emitLeadingFence(IRBuilder<> &Builder,
|
||||||
return nullptr;
|
return nullptr;
|
||||||
}
|
}
|
||||||
|
|
||||||
Instruction *RISCVTargetLowering::emitTrailingFence(IRBuilder<> &Builder,
|
Instruction *RISCVTargetLowering::emitTrailingFence(IRBuilderBase &Builder,
|
||||||
Instruction *Inst,
|
Instruction *Inst,
|
||||||
AtomicOrdering Ord) const {
|
AtomicOrdering Ord) const {
|
||||||
if (isa<LoadInst>(Inst) && isAcquireOrStronger(Ord))
|
if (isa<LoadInst>(Inst) && isAcquireOrStronger(Ord))
|
||||||
|
@ -8323,7 +8323,7 @@ getIntrinsicForMaskedAtomicRMWBinOp(unsigned XLen, AtomicRMWInst::BinOp BinOp) {
|
||||||
}
|
}
|
||||||
|
|
||||||
Value *RISCVTargetLowering::emitMaskedAtomicRMWIntrinsic(
|
Value *RISCVTargetLowering::emitMaskedAtomicRMWIntrinsic(
|
||||||
IRBuilder<> &Builder, AtomicRMWInst *AI, Value *AlignedAddr, Value *Incr,
|
IRBuilderBase &Builder, AtomicRMWInst *AI, Value *AlignedAddr, Value *Incr,
|
||||||
Value *Mask, Value *ShiftAmt, AtomicOrdering Ord) const {
|
Value *Mask, Value *ShiftAmt, AtomicOrdering Ord) const {
|
||||||
unsigned XLen = Subtarget.getXLen();
|
unsigned XLen = Subtarget.getXLen();
|
||||||
Value *Ordering =
|
Value *Ordering =
|
||||||
|
@ -8375,7 +8375,7 @@ RISCVTargetLowering::shouldExpandAtomicCmpXchgInIR(
|
||||||
}
|
}
|
||||||
|
|
||||||
Value *RISCVTargetLowering::emitMaskedAtomicCmpXchgIntrinsic(
|
Value *RISCVTargetLowering::emitMaskedAtomicCmpXchgIntrinsic(
|
||||||
IRBuilder<> &Builder, AtomicCmpXchgInst *CI, Value *AlignedAddr,
|
IRBuilderBase &Builder, AtomicCmpXchgInst *CI, Value *AlignedAddr,
|
||||||
Value *CmpVal, Value *NewVal, Value *Mask, AtomicOrdering Ord) const {
|
Value *CmpVal, Value *NewVal, Value *Mask, AtomicOrdering Ord) const {
|
||||||
unsigned XLen = Subtarget.getXLen();
|
unsigned XLen = Subtarget.getXLen();
|
||||||
Value *Ordering = Builder.getIntN(XLen, static_cast<uint64_t>(Ord));
|
Value *Ordering = Builder.getIntN(XLen, static_cast<uint64_t>(Ord));
|
||||||
|
|
|
@ -369,9 +369,9 @@ public:
|
||||||
bool shouldInsertFencesForAtomic(const Instruction *I) const override {
|
bool shouldInsertFencesForAtomic(const Instruction *I) const override {
|
||||||
return isa<LoadInst>(I) || isa<StoreInst>(I);
|
return isa<LoadInst>(I) || isa<StoreInst>(I);
|
||||||
}
|
}
|
||||||
Instruction *emitLeadingFence(IRBuilder<> &Builder, Instruction *Inst,
|
Instruction *emitLeadingFence(IRBuilderBase &Builder, Instruction *Inst,
|
||||||
AtomicOrdering Ord) const override;
|
AtomicOrdering Ord) const override;
|
||||||
Instruction *emitTrailingFence(IRBuilder<> &Builder, Instruction *Inst,
|
Instruction *emitTrailingFence(IRBuilderBase &Builder, Instruction *Inst,
|
||||||
AtomicOrdering Ord) const override;
|
AtomicOrdering Ord) const override;
|
||||||
|
|
||||||
bool isFMAFasterThanFMulAndFAdd(const MachineFunction &MF,
|
bool isFMAFasterThanFMulAndFAdd(const MachineFunction &MF,
|
||||||
|
@ -442,13 +442,13 @@ public:
|
||||||
|
|
||||||
TargetLowering::AtomicExpansionKind
|
TargetLowering::AtomicExpansionKind
|
||||||
shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const override;
|
shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const override;
|
||||||
Value *emitMaskedAtomicRMWIntrinsic(IRBuilder<> &Builder, AtomicRMWInst *AI,
|
Value *emitMaskedAtomicRMWIntrinsic(IRBuilderBase &Builder, AtomicRMWInst *AI,
|
||||||
Value *AlignedAddr, Value *Incr,
|
Value *AlignedAddr, Value *Incr,
|
||||||
Value *Mask, Value *ShiftAmt,
|
Value *Mask, Value *ShiftAmt,
|
||||||
AtomicOrdering Ord) const override;
|
AtomicOrdering Ord) const override;
|
||||||
TargetLowering::AtomicExpansionKind
|
TargetLowering::AtomicExpansionKind
|
||||||
shouldExpandAtomicCmpXchgInIR(AtomicCmpXchgInst *CI) const override;
|
shouldExpandAtomicCmpXchgInIR(AtomicCmpXchgInst *CI) const override;
|
||||||
Value *emitMaskedAtomicCmpXchgIntrinsic(IRBuilder<> &Builder,
|
Value *emitMaskedAtomicCmpXchgIntrinsic(IRBuilderBase &Builder,
|
||||||
AtomicCmpXchgInst *CI,
|
AtomicCmpXchgInst *CI,
|
||||||
Value *AlignedAddr, Value *CmpVal,
|
Value *AlignedAddr, Value *CmpVal,
|
||||||
Value *NewVal, Value *Mask,
|
Value *NewVal, Value *Mask,
|
||||||
|
|
|
@ -2494,14 +2494,14 @@ static bool hasStackGuardSlotTLS(const Triple &TargetTriple) {
|
||||||
(TargetTriple.isAndroid() && !TargetTriple.isAndroidVersionLT(17));
|
(TargetTriple.isAndroid() && !TargetTriple.isAndroidVersionLT(17));
|
||||||
}
|
}
|
||||||
|
|
||||||
static Constant* SegmentOffset(IRBuilder<> &IRB,
|
static Constant* SegmentOffset(IRBuilderBase &IRB,
|
||||||
int Offset, unsigned AddressSpace) {
|
int Offset, unsigned AddressSpace) {
|
||||||
return ConstantExpr::getIntToPtr(
|
return ConstantExpr::getIntToPtr(
|
||||||
ConstantInt::get(Type::getInt32Ty(IRB.getContext()), Offset),
|
ConstantInt::get(Type::getInt32Ty(IRB.getContext()), Offset),
|
||||||
Type::getInt8PtrTy(IRB.getContext())->getPointerTo(AddressSpace));
|
Type::getInt8PtrTy(IRB.getContext())->getPointerTo(AddressSpace));
|
||||||
}
|
}
|
||||||
|
|
||||||
Value *X86TargetLowering::getIRStackGuard(IRBuilder<> &IRB) const {
|
Value *X86TargetLowering::getIRStackGuard(IRBuilderBase &IRB) const {
|
||||||
// glibc, bionic, and Fuchsia have a special slot for the stack guard in
|
// glibc, bionic, and Fuchsia have a special slot for the stack guard in
|
||||||
// tcbhead_t; use it instead of the usual global variable (see
|
// tcbhead_t; use it instead of the usual global variable (see
|
||||||
// sysdeps/{i386,x86_64}/nptl/tls.h)
|
// sysdeps/{i386,x86_64}/nptl/tls.h)
|
||||||
|
@ -2577,7 +2577,8 @@ Function *X86TargetLowering::getSSPStackGuardCheck(const Module &M) const {
|
||||||
return TargetLowering::getSSPStackGuardCheck(M);
|
return TargetLowering::getSSPStackGuardCheck(M);
|
||||||
}
|
}
|
||||||
|
|
||||||
Value *X86TargetLowering::getSafeStackPointerLocation(IRBuilder<> &IRB) const {
|
Value *
|
||||||
|
X86TargetLowering::getSafeStackPointerLocation(IRBuilderBase &IRB) const {
|
||||||
if (Subtarget.getTargetTriple().isOSContiki())
|
if (Subtarget.getTargetTriple().isOSContiki())
|
||||||
return getDefaultSafeStackPointerLocation(IRB, false);
|
return getDefaultSafeStackPointerLocation(IRB, false);
|
||||||
|
|
||||||
|
|
|
@ -1357,7 +1357,7 @@ namespace llvm {
|
||||||
|
|
||||||
/// If the target has a standard location for the stack protector cookie,
|
/// If the target has a standard location for the stack protector cookie,
|
||||||
/// returns the address of that location. Otherwise, returns nullptr.
|
/// returns the address of that location. Otherwise, returns nullptr.
|
||||||
Value *getIRStackGuard(IRBuilder<> &IRB) const override;
|
Value *getIRStackGuard(IRBuilderBase &IRB) const override;
|
||||||
|
|
||||||
bool useLoadStackGuardNode() const override;
|
bool useLoadStackGuardNode() const override;
|
||||||
bool useStackGuardXorFP() const override;
|
bool useStackGuardXorFP() const override;
|
||||||
|
@ -1371,7 +1371,7 @@ namespace llvm {
|
||||||
/// Return true if the target stores SafeStack pointer at a fixed offset in
|
/// Return true if the target stores SafeStack pointer at a fixed offset in
|
||||||
/// some non-standard address space, and populates the address space and
|
/// some non-standard address space, and populates the address space and
|
||||||
/// offset as appropriate.
|
/// offset as appropriate.
|
||||||
Value *getSafeStackPointerLocation(IRBuilder<> &IRB) const override;
|
Value *getSafeStackPointerLocation(IRBuilderBase &IRB) const override;
|
||||||
|
|
||||||
std::pair<SDValue, SDValue> BuildFILD(EVT DstVT, EVT SrcVT, const SDLoc &DL,
|
std::pair<SDValue, SDValue> BuildFILD(EVT DstVT, EVT SrcVT, const SDLoc &DL,
|
||||||
SDValue Chain, SDValue Pointer,
|
SDValue Chain, SDValue Pointer,
|
||||||
|
|
Loading…
Reference in New Issue