From 1ffa6499ea3b7fde687666a45e89909fbf72a450 Mon Sep 17 00:00:00 2001 From: Nikita Popov Date: Sat, 5 Jun 2021 22:56:19 +0200 Subject: [PATCH] [TargetLowering] Use IRBuilderBase instead of IRBuilder<> (NFC) Don't require a specific kind of IRBuilder for TargetLowering hooks. This allows us to drop the IRBuilder.h include from TargetLowering.h. Differential Revision: https://reviews.llvm.org/D103759 --- llvm/include/llvm/CodeGen/TargetLowering.h | 23 ++++++++++--------- llvm/lib/CodeGen/TargetLoweringBase.cpp | 14 ++++++----- .../Target/AArch64/AArch64ISelLowering.cpp | 14 ++++++----- llvm/lib/Target/AArch64/AArch64ISelLowering.h | 12 +++++----- llvm/lib/Target/ARM/ARMISelLowering.cpp | 14 +++++------ llvm/lib/Target/ARM/ARMISelLowering.h | 15 ++++++------ .../Target/Hexagon/HexagonISelLowering.cpp | 10 ++++---- llvm/lib/Target/Hexagon/HexagonISelLowering.h | 8 +++---- llvm/lib/Target/PowerPC/PPCISelLowering.cpp | 8 +++---- llvm/lib/Target/PowerPC/PPCISelLowering.h | 4 ++-- llvm/lib/Target/RISCV/RISCVISelLowering.cpp | 8 +++---- llvm/lib/Target/RISCV/RISCVISelLowering.h | 8 +++---- llvm/lib/Target/X86/X86ISelLowering.cpp | 7 +++--- llvm/lib/Target/X86/X86ISelLowering.h | 4 ++-- 14 files changed, 79 insertions(+), 70 deletions(-) diff --git a/llvm/include/llvm/CodeGen/TargetLowering.h b/llvm/include/llvm/CodeGen/TargetLowering.h index f93415f2ccae..a2529bf4ce74 100644 --- a/llvm/include/llvm/CodeGen/TargetLowering.h +++ b/llvm/include/llvm/CodeGen/TargetLowering.h @@ -40,7 +40,6 @@ #include "llvm/IR/DataLayout.h" #include "llvm/IR/DerivedTypes.h" #include "llvm/IR/Function.h" -#include "llvm/IR/IRBuilder.h" #include "llvm/IR/InlineAsm.h" #include "llvm/IR/Instruction.h" #include "llvm/IR/Instructions.h" @@ -72,6 +71,7 @@ class FunctionLoweringInfo; class GlobalValue; class GISelKnownBits; class IntrinsicInst; +class IRBuilderBase; struct KnownBits; class LegacyDivergenceAnalysis; class LLVMContext; @@ -1770,7 +1770,7 @@ public: /// returns the address of that location. Otherwise, returns nullptr. /// DEPRECATED: please override useLoadStackGuardNode and customize /// LOAD_STACK_GUARD, or customize \@llvm.stackguard(). - virtual Value *getIRStackGuard(IRBuilder<> &IRB) const; + virtual Value *getIRStackGuard(IRBuilderBase &IRB) const; /// Inserts necessary declarations for SSP (stack protection) purpose. /// Should be used only when getIRStackGuard returns nullptr. @@ -1800,12 +1800,12 @@ public: } protected: - Value *getDefaultSafeStackPointerLocation(IRBuilder<> &IRB, + Value *getDefaultSafeStackPointerLocation(IRBuilderBase &IRB, bool UseTLS) const; public: /// Returns the target-specific address of the unsafe stack pointer. - virtual Value *getSafeStackPointerLocation(IRBuilder<> &IRB) const; + virtual Value *getSafeStackPointerLocation(IRBuilderBase &IRB) const; /// Returns the name of the symbol used to emit stack probes or the empty /// string if not applicable. @@ -1879,14 +1879,14 @@ public: /// corresponding pointee type. This may entail some non-trivial operations to /// truncate or reconstruct types that will be illegal in the backend. See /// ARMISelLowering for an example implementation. - virtual Value *emitLoadLinked(IRBuilder<> &Builder, Value *Addr, + virtual Value *emitLoadLinked(IRBuilderBase &Builder, Value *Addr, AtomicOrdering Ord) const { llvm_unreachable("Load linked unimplemented on this target"); } /// Perform a store-conditional operation to Addr. Return the status of the /// store. This should be 0 if the store succeeded, non-zero otherwise. - virtual Value *emitStoreConditional(IRBuilder<> &Builder, Value *Val, + virtual Value *emitStoreConditional(IRBuilderBase &Builder, Value *Val, Value *Addr, AtomicOrdering Ord) const { llvm_unreachable("Store conditional unimplemented on this target"); } @@ -1894,7 +1894,7 @@ public: /// Perform a masked atomicrmw using a target-specific intrinsic. This /// represents the core LL/SC loop which will be lowered at a late stage by /// the backend. - virtual Value *emitMaskedAtomicRMWIntrinsic(IRBuilder<> &Builder, + virtual Value *emitMaskedAtomicRMWIntrinsic(IRBuilderBase &Builder, AtomicRMWInst *AI, Value *AlignedAddr, Value *Incr, Value *Mask, Value *ShiftAmt, @@ -1906,7 +1906,7 @@ public: /// represents the core LL/SC loop which will be lowered at a late stage by /// the backend. virtual Value *emitMaskedAtomicCmpXchgIntrinsic( - IRBuilder<> &Builder, AtomicCmpXchgInst *CI, Value *AlignedAddr, + IRBuilderBase &Builder, AtomicCmpXchgInst *CI, Value *AlignedAddr, Value *CmpVal, Value *NewVal, Value *Mask, AtomicOrdering Ord) const { llvm_unreachable("Masked cmpxchg expansion unimplemented on this target"); } @@ -1944,10 +1944,11 @@ public: /// seq_cst. But if they are lowered to monotonic accesses, no amount of /// IR-level fences can prevent it. /// @{ - virtual Instruction *emitLeadingFence(IRBuilder<> &Builder, Instruction *Inst, + virtual Instruction *emitLeadingFence(IRBuilderBase &Builder, + Instruction *Inst, AtomicOrdering Ord) const; - virtual Instruction *emitTrailingFence(IRBuilder<> &Builder, + virtual Instruction *emitTrailingFence(IRBuilderBase &Builder, Instruction *Inst, AtomicOrdering Ord) const; /// @} @@ -1958,7 +1959,7 @@ public: // a dedicated instruction, if desired. // E.g., on ARM, if ldrex isn't followed by strex, the exclusive monitor would // be unnecessarily held, except if clrex, inserted by this hook, is executed. - virtual void emitAtomicCmpXchgNoStoreLLBalance(IRBuilder<> &Builder) const {} + virtual void emitAtomicCmpXchgNoStoreLLBalance(IRBuilderBase &Builder) const {} /// Returns true if the given (atomic) store should be expanded by the /// IR-level AtomicExpand pass into an "atomic xchg" which ignores its input. diff --git a/llvm/lib/CodeGen/TargetLoweringBase.cpp b/llvm/lib/CodeGen/TargetLoweringBase.cpp index f42072a8d2c0..7319753f8fa5 100644 --- a/llvm/lib/CodeGen/TargetLoweringBase.cpp +++ b/llvm/lib/CodeGen/TargetLoweringBase.cpp @@ -1860,8 +1860,9 @@ TargetLoweringBase::getTypeLegalizationCost(const DataLayout &DL, } } -Value *TargetLoweringBase::getDefaultSafeStackPointerLocation(IRBuilder<> &IRB, - bool UseTLS) const { +Value * +TargetLoweringBase::getDefaultSafeStackPointerLocation(IRBuilderBase &IRB, + bool UseTLS) const { // compiler-rt provides a variable with a magic name. Targets that do not // link with compiler-rt may also provide such a variable. Module *M = IRB.GetInsertBlock()->getParent()->getParent(); @@ -1892,7 +1893,8 @@ Value *TargetLoweringBase::getDefaultSafeStackPointerLocation(IRBuilder<> &IRB, return UnsafeStackPtr; } -Value *TargetLoweringBase::getSafeStackPointerLocation(IRBuilder<> &IRB) const { +Value * +TargetLoweringBase::getSafeStackPointerLocation(IRBuilderBase &IRB) const { if (!TM.getTargetTriple().isAndroid()) return getDefaultSafeStackPointerLocation(IRB, true); @@ -1952,7 +1954,7 @@ bool TargetLoweringBase::isLegalAddressingMode(const DataLayout &DL, // For OpenBSD return its special guard variable. Otherwise return nullptr, // so that SelectionDAG handle SSP. -Value *TargetLoweringBase::getIRStackGuard(IRBuilder<> &IRB) const { +Value *TargetLoweringBase::getIRStackGuard(IRBuilderBase &IRB) const { if (getTargetMachine().getTargetTriple().isOSOpenBSD()) { Module &M = *IRB.GetInsertBlock()->getParent()->getParent(); PointerType *PtrTy = Type::getInt8PtrTy(M.getContext()); @@ -2254,7 +2256,7 @@ TargetLoweringBase::getAtomicMemOperandFlags(const Instruction &AI, return Flags; } -Instruction *TargetLoweringBase::emitLeadingFence(IRBuilder<> &Builder, +Instruction *TargetLoweringBase::emitLeadingFence(IRBuilderBase &Builder, Instruction *Inst, AtomicOrdering Ord) const { if (isReleaseOrStronger(Ord) && Inst->hasAtomicStore()) @@ -2263,7 +2265,7 @@ Instruction *TargetLoweringBase::emitLeadingFence(IRBuilder<> &Builder, return nullptr; } -Instruction *TargetLoweringBase::emitTrailingFence(IRBuilder<> &Builder, +Instruction *TargetLoweringBase::emitTrailingFence(IRBuilderBase &Builder, Instruction *Inst, AtomicOrdering Ord) const { if (isAcquireOrStronger(Ord)) diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp index 1d5a20d0ffda..0f89bffd9f21 100644 --- a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp +++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp @@ -17025,7 +17025,8 @@ AArch64TargetLowering::shouldExpandAtomicCmpXchgInIR( return AtomicExpansionKind::LLSC; } -Value *AArch64TargetLowering::emitLoadLinked(IRBuilder<> &Builder, Value *Addr, +Value *AArch64TargetLowering::emitLoadLinked(IRBuilderBase &Builder, + Value *Addr, AtomicOrdering Ord) const { Module *M = Builder.GetInsertBlock()->getParent()->getParent(); Type *ValTy = cast(Addr->getType())->getElementType(); @@ -17065,12 +17066,12 @@ Value *AArch64TargetLowering::emitLoadLinked(IRBuilder<> &Builder, Value *Addr, } void AArch64TargetLowering::emitAtomicCmpXchgNoStoreLLBalance( - IRBuilder<> &Builder) const { + IRBuilderBase &Builder) const { Module *M = Builder.GetInsertBlock()->getParent()->getParent(); Builder.CreateCall(Intrinsic::getDeclaration(M, Intrinsic::aarch64_clrex)); } -Value *AArch64TargetLowering::emitStoreConditional(IRBuilder<> &Builder, +Value *AArch64TargetLowering::emitStoreConditional(IRBuilderBase &Builder, Value *Val, Value *Addr, AtomicOrdering Ord) const { Module *M = Builder.GetInsertBlock()->getParent()->getParent(); @@ -17123,7 +17124,7 @@ bool AArch64TargetLowering::shouldNormalizeToSelectSequence(LLVMContext &, return false; } -static Value *UseTlsOffset(IRBuilder<> &IRB, unsigned Offset) { +static Value *UseTlsOffset(IRBuilderBase &IRB, unsigned Offset) { Module *M = IRB.GetInsertBlock()->getParent()->getParent(); Function *ThreadPointerFunc = Intrinsic::getDeclaration(M, Intrinsic::thread_pointer); @@ -17133,7 +17134,7 @@ static Value *UseTlsOffset(IRBuilder<> &IRB, unsigned Offset) { IRB.getInt8PtrTy()->getPointerTo(0)); } -Value *AArch64TargetLowering::getIRStackGuard(IRBuilder<> &IRB) const { +Value *AArch64TargetLowering::getIRStackGuard(IRBuilderBase &IRB) const { // Android provides a fixed TLS slot for the stack cookie. See the definition // of TLS_SLOT_STACK_GUARD in // https://android.googlesource.com/platform/bionic/+/master/libc/private/bionic_tls.h @@ -17182,7 +17183,8 @@ Function *AArch64TargetLowering::getSSPStackGuardCheck(const Module &M) const { return TargetLowering::getSSPStackGuardCheck(M); } -Value *AArch64TargetLowering::getSafeStackPointerLocation(IRBuilder<> &IRB) const { +Value * +AArch64TargetLowering::getSafeStackPointerLocation(IRBuilderBase &IRB) const { // Android provides a fixed TLS slot for the SafeStack pointer. See the // definition of TLS_SLOT_SAFESTACK in // https://android.googlesource.com/platform/bionic/+/master/libc/private/bionic_tls.h diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.h b/llvm/lib/Target/AArch64/AArch64ISelLowering.h index b79d75e7fc8c..c2ada6f35acc 100644 --- a/llvm/lib/Target/AArch64/AArch64ISelLowering.h +++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.h @@ -647,12 +647,12 @@ public: return TargetLowering::shouldFormOverflowOp(Opcode, VT, true); } - Value *emitLoadLinked(IRBuilder<> &Builder, Value *Addr, + Value *emitLoadLinked(IRBuilderBase &Builder, Value *Addr, AtomicOrdering Ord) const override; - Value *emitStoreConditional(IRBuilder<> &Builder, Value *Val, - Value *Addr, AtomicOrdering Ord) const override; + Value *emitStoreConditional(IRBuilderBase &Builder, Value *Val, Value *Addr, + AtomicOrdering Ord) const override; - void emitAtomicCmpXchgNoStoreLLBalance(IRBuilder<> &Builder) const override; + void emitAtomicCmpXchgNoStoreLLBalance(IRBuilderBase &Builder) const override; TargetLoweringBase::AtomicExpansionKind shouldExpandAtomicLoadInIR(LoadInst *LI) const override; @@ -669,7 +669,7 @@ public: /// If the target has a standard location for the stack protector cookie, /// returns the address of that location. Otherwise, returns nullptr. - Value *getIRStackGuard(IRBuilder<> &IRB) const override; + Value *getIRStackGuard(IRBuilderBase &IRB) const override; void insertSSPDeclarations(Module &M) const override; Value *getSDagStackGuard(const Module &M) const override; @@ -677,7 +677,7 @@ public: /// If the target has a standard location for the unsafe stack pointer, /// returns the address of that location. Otherwise, returns nullptr. - Value *getSafeStackPointerLocation(IRBuilder<> &IRB) const override; + Value *getSafeStackPointerLocation(IRBuilderBase &IRB) const override; /// If a physical register, this returns the register that receives the /// exception address on entry to an EH pad. diff --git a/llvm/lib/Target/ARM/ARMISelLowering.cpp b/llvm/lib/Target/ARM/ARMISelLowering.cpp index 8dd013d5a0a5..e6e495d670c1 100644 --- a/llvm/lib/Target/ARM/ARMISelLowering.cpp +++ b/llvm/lib/Target/ARM/ARMISelLowering.cpp @@ -19381,7 +19381,7 @@ bool ARMTargetLowering::isExtractSubvectorCheap(EVT ResVT, EVT SrcVT, return (Index == 0 || Index == ResVT.getVectorNumElements()); } -Instruction* ARMTargetLowering::makeDMB(IRBuilder<> &Builder, +Instruction *ARMTargetLowering::makeDMB(IRBuilderBase &Builder, ARM_MB::MemBOpt Domain) const { Module *M = Builder.GetInsertBlock()->getParent()->getParent(); @@ -19411,7 +19411,7 @@ Instruction* ARMTargetLowering::makeDMB(IRBuilder<> &Builder, } // Based on http://www.cl.cam.ac.uk/~pes20/cpp/cpp0xmappings.html -Instruction *ARMTargetLowering::emitLeadingFence(IRBuilder<> &Builder, +Instruction *ARMTargetLowering::emitLeadingFence(IRBuilderBase &Builder, Instruction *Inst, AtomicOrdering Ord) const { switch (Ord) { @@ -19436,7 +19436,7 @@ Instruction *ARMTargetLowering::emitLeadingFence(IRBuilder<> &Builder, llvm_unreachable("Unknown fence ordering in emitLeadingFence"); } -Instruction *ARMTargetLowering::emitTrailingFence(IRBuilder<> &Builder, +Instruction *ARMTargetLowering::emitTrailingFence(IRBuilderBase &Builder, Instruction *Inst, AtomicOrdering Ord) const { switch (Ord) { @@ -19598,7 +19598,7 @@ bool ARMTargetLowering::shouldExpandShift(SelectionDAG &DAG, SDNode *N) const { return !Subtarget->hasMinSize() || Subtarget->isTargetWindows(); } -Value *ARMTargetLowering::emitLoadLinked(IRBuilder<> &Builder, Value *Addr, +Value *ARMTargetLowering::emitLoadLinked(IRBuilderBase &Builder, Value *Addr, AtomicOrdering Ord) const { Module *M = Builder.GetInsertBlock()->getParent()->getParent(); Type *ValTy = cast(Addr->getType())->getElementType(); @@ -19635,15 +19635,15 @@ Value *ARMTargetLowering::emitLoadLinked(IRBuilder<> &Builder, Value *Addr, } void ARMTargetLowering::emitAtomicCmpXchgNoStoreLLBalance( - IRBuilder<> &Builder) const { + IRBuilderBase &Builder) const { if (!Subtarget->hasV7Ops()) return; Module *M = Builder.GetInsertBlock()->getParent()->getParent(); Builder.CreateCall(Intrinsic::getDeclaration(M, Intrinsic::arm_clrex)); } -Value *ARMTargetLowering::emitStoreConditional(IRBuilder<> &Builder, Value *Val, - Value *Addr, +Value *ARMTargetLowering::emitStoreConditional(IRBuilderBase &Builder, + Value *Val, Value *Addr, AtomicOrdering Ord) const { Module *M = Builder.GetInsertBlock()->getParent()->getParent(); bool IsRelease = isReleaseOrStronger(Ord); diff --git a/llvm/lib/Target/ARM/ARMISelLowering.h b/llvm/lib/Target/ARM/ARMISelLowering.h index 5b4a96d93cab..f94c8aed5896 100644 --- a/llvm/lib/Target/ARM/ARMISelLowering.h +++ b/llvm/lib/Target/ARM/ARMISelLowering.h @@ -627,17 +627,18 @@ class VectorType; Register getExceptionSelectorRegister(const Constant *PersonalityFn) const override; - Instruction *makeDMB(IRBuilder<> &Builder, ARM_MB::MemBOpt Domain) const; - Value *emitLoadLinked(IRBuilder<> &Builder, Value *Addr, + Instruction *makeDMB(IRBuilderBase &Builder, ARM_MB::MemBOpt Domain) const; + Value *emitLoadLinked(IRBuilderBase &Builder, Value *Addr, AtomicOrdering Ord) const override; - Value *emitStoreConditional(IRBuilder<> &Builder, Value *Val, - Value *Addr, AtomicOrdering Ord) const override; + Value *emitStoreConditional(IRBuilderBase &Builder, Value *Val, Value *Addr, + AtomicOrdering Ord) const override; - void emitAtomicCmpXchgNoStoreLLBalance(IRBuilder<> &Builder) const override; + void + emitAtomicCmpXchgNoStoreLLBalance(IRBuilderBase &Builder) const override; - Instruction *emitLeadingFence(IRBuilder<> &Builder, Instruction *Inst, + Instruction *emitLeadingFence(IRBuilderBase &Builder, Instruction *Inst, AtomicOrdering Ord) const override; - Instruction *emitTrailingFence(IRBuilder<> &Builder, Instruction *Inst, + Instruction *emitTrailingFence(IRBuilderBase &Builder, Instruction *Inst, AtomicOrdering Ord) const override; unsigned getMaxSupportedInterleaveFactor() const override; diff --git a/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp b/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp index 5e2771a7ab6d..db755b4feda6 100644 --- a/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp +++ b/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp @@ -3554,8 +3554,9 @@ bool HexagonTargetLowering::shouldReduceLoadWidth(SDNode *Load, return true; } -Value *HexagonTargetLowering::emitLoadLinked(IRBuilder<> &Builder, Value *Addr, - AtomicOrdering Ord) const { +Value *HexagonTargetLowering::emitLoadLinked(IRBuilderBase &Builder, + Value *Addr, + AtomicOrdering Ord) const { BasicBlock *BB = Builder.GetInsertBlock(); Module *M = BB->getParent()->getParent(); auto PT = cast(Addr->getType()); @@ -3577,8 +3578,9 @@ Value *HexagonTargetLowering::emitLoadLinked(IRBuilder<> &Builder, Value *Addr, /// Perform a store-conditional operation to Addr. Return the status of the /// store. This should be 0 if the store succeeded, non-zero otherwise. -Value *HexagonTargetLowering::emitStoreConditional(IRBuilder<> &Builder, - Value *Val, Value *Addr, AtomicOrdering Ord) const { +Value *HexagonTargetLowering::emitStoreConditional(IRBuilderBase &Builder, + Value *Val, Value *Addr, + AtomicOrdering Ord) const { BasicBlock *BB = Builder.GetInsertBlock(); Module *M = BB->getParent()->getParent(); Type *Ty = Val->getType(); diff --git a/llvm/lib/Target/Hexagon/HexagonISelLowering.h b/llvm/lib/Target/Hexagon/HexagonISelLowering.h index a40c1f7f268a..84c4355927b2 100644 --- a/llvm/lib/Target/Hexagon/HexagonISelLowering.h +++ b/llvm/lib/Target/Hexagon/HexagonISelLowering.h @@ -323,10 +323,10 @@ public: EVT NewVT) const override; // Handling of atomic RMW instructions. - Value *emitLoadLinked(IRBuilder<> &Builder, Value *Addr, - AtomicOrdering Ord) const override; - Value *emitStoreConditional(IRBuilder<> &Builder, Value *Val, - Value *Addr, AtomicOrdering Ord) const override; + Value *emitLoadLinked(IRBuilderBase &Builder, Value *Addr, + AtomicOrdering Ord) const override; + Value *emitStoreConditional(IRBuilderBase &Builder, Value *Val, Value *Addr, + AtomicOrdering Ord) const override; AtomicExpansionKind shouldExpandAtomicLoadInIR(LoadInst *LI) const override; bool shouldExpandAtomicStoreInIR(StoreInst *SI) const override; AtomicExpansionKind diff --git a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp index 4e42c029fcef..aefa48d78265 100644 --- a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp +++ b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp @@ -10946,7 +10946,7 @@ void PPCTargetLowering::ReplaceNodeResults(SDNode *N, // Other Lowering Code //===----------------------------------------------------------------------===// -static Instruction* callIntrinsic(IRBuilder<> &Builder, Intrinsic::ID Id) { +static Instruction *callIntrinsic(IRBuilderBase &Builder, Intrinsic::ID Id) { Module *M = Builder.GetInsertBlock()->getParent()->getParent(); Function *Func = Intrinsic::getDeclaration(M, Id); return Builder.CreateCall(Func, {}); @@ -10954,7 +10954,7 @@ static Instruction* callIntrinsic(IRBuilder<> &Builder, Intrinsic::ID Id) { // The mappings for emitLeading/TrailingFence is taken from // http://www.cl.cam.ac.uk/~pes20/cpp/cpp0xmappings.html -Instruction *PPCTargetLowering::emitLeadingFence(IRBuilder<> &Builder, +Instruction *PPCTargetLowering::emitLeadingFence(IRBuilderBase &Builder, Instruction *Inst, AtomicOrdering Ord) const { if (Ord == AtomicOrdering::SequentiallyConsistent) @@ -10964,7 +10964,7 @@ Instruction *PPCTargetLowering::emitLeadingFence(IRBuilder<> &Builder, return nullptr; } -Instruction *PPCTargetLowering::emitTrailingFence(IRBuilder<> &Builder, +Instruction *PPCTargetLowering::emitTrailingFence(IRBuilderBase &Builder, Instruction *Inst, AtomicOrdering Ord) const { if (Inst->hasAtomicLoad() && isAcquireOrStronger(Ord)) { @@ -17370,4 +17370,4 @@ CCAssignFn *PPCTargetLowering::ccAssignFnForCall(CallingConv::ID CC, default: return CC_PPC64_ELF_FIS; } -} \ No newline at end of file +} diff --git a/llvm/lib/Target/PowerPC/PPCISelLowering.h b/llvm/lib/Target/PowerPC/PPCISelLowering.h index fd9ec59845f0..f06c4ee21394 100644 --- a/llvm/lib/Target/PowerPC/PPCISelLowering.h +++ b/llvm/lib/Target/PowerPC/PPCISelLowering.h @@ -871,9 +871,9 @@ namespace llvm { return true; } - Instruction *emitLeadingFence(IRBuilder<> &Builder, Instruction *Inst, + Instruction *emitLeadingFence(IRBuilderBase &Builder, Instruction *Inst, AtomicOrdering Ord) const override; - Instruction *emitTrailingFence(IRBuilder<> &Builder, Instruction *Inst, + Instruction *emitTrailingFence(IRBuilderBase &Builder, Instruction *Inst, AtomicOrdering Ord) const override; MachineBasicBlock * diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp index db8ed70b38df..87c46893cdd4 100644 --- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp +++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp @@ -8239,7 +8239,7 @@ void RISCVTargetLowering::LowerAsmOperandForConstraint( TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG); } -Instruction *RISCVTargetLowering::emitLeadingFence(IRBuilder<> &Builder, +Instruction *RISCVTargetLowering::emitLeadingFence(IRBuilderBase &Builder, Instruction *Inst, AtomicOrdering Ord) const { if (isa(Inst) && Ord == AtomicOrdering::SequentiallyConsistent) @@ -8249,7 +8249,7 @@ Instruction *RISCVTargetLowering::emitLeadingFence(IRBuilder<> &Builder, return nullptr; } -Instruction *RISCVTargetLowering::emitTrailingFence(IRBuilder<> &Builder, +Instruction *RISCVTargetLowering::emitTrailingFence(IRBuilderBase &Builder, Instruction *Inst, AtomicOrdering Ord) const { if (isa(Inst) && isAcquireOrStronger(Ord)) @@ -8323,7 +8323,7 @@ getIntrinsicForMaskedAtomicRMWBinOp(unsigned XLen, AtomicRMWInst::BinOp BinOp) { } Value *RISCVTargetLowering::emitMaskedAtomicRMWIntrinsic( - IRBuilder<> &Builder, AtomicRMWInst *AI, Value *AlignedAddr, Value *Incr, + IRBuilderBase &Builder, AtomicRMWInst *AI, Value *AlignedAddr, Value *Incr, Value *Mask, Value *ShiftAmt, AtomicOrdering Ord) const { unsigned XLen = Subtarget.getXLen(); Value *Ordering = @@ -8375,7 +8375,7 @@ RISCVTargetLowering::shouldExpandAtomicCmpXchgInIR( } Value *RISCVTargetLowering::emitMaskedAtomicCmpXchgIntrinsic( - IRBuilder<> &Builder, AtomicCmpXchgInst *CI, Value *AlignedAddr, + IRBuilderBase &Builder, AtomicCmpXchgInst *CI, Value *AlignedAddr, Value *CmpVal, Value *NewVal, Value *Mask, AtomicOrdering Ord) const { unsigned XLen = Subtarget.getXLen(); Value *Ordering = Builder.getIntN(XLen, static_cast(Ord)); diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.h b/llvm/lib/Target/RISCV/RISCVISelLowering.h index ffed714d8311..eee680f39860 100644 --- a/llvm/lib/Target/RISCV/RISCVISelLowering.h +++ b/llvm/lib/Target/RISCV/RISCVISelLowering.h @@ -369,9 +369,9 @@ public: bool shouldInsertFencesForAtomic(const Instruction *I) const override { return isa(I) || isa(I); } - Instruction *emitLeadingFence(IRBuilder<> &Builder, Instruction *Inst, + Instruction *emitLeadingFence(IRBuilderBase &Builder, Instruction *Inst, AtomicOrdering Ord) const override; - Instruction *emitTrailingFence(IRBuilder<> &Builder, Instruction *Inst, + Instruction *emitTrailingFence(IRBuilderBase &Builder, Instruction *Inst, AtomicOrdering Ord) const override; bool isFMAFasterThanFMulAndFAdd(const MachineFunction &MF, @@ -442,13 +442,13 @@ public: TargetLowering::AtomicExpansionKind shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const override; - Value *emitMaskedAtomicRMWIntrinsic(IRBuilder<> &Builder, AtomicRMWInst *AI, + Value *emitMaskedAtomicRMWIntrinsic(IRBuilderBase &Builder, AtomicRMWInst *AI, Value *AlignedAddr, Value *Incr, Value *Mask, Value *ShiftAmt, AtomicOrdering Ord) const override; TargetLowering::AtomicExpansionKind shouldExpandAtomicCmpXchgInIR(AtomicCmpXchgInst *CI) const override; - Value *emitMaskedAtomicCmpXchgIntrinsic(IRBuilder<> &Builder, + Value *emitMaskedAtomicCmpXchgIntrinsic(IRBuilderBase &Builder, AtomicCmpXchgInst *CI, Value *AlignedAddr, Value *CmpVal, Value *NewVal, Value *Mask, diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp index a883347cf383..5d6dbd190a3a 100644 --- a/llvm/lib/Target/X86/X86ISelLowering.cpp +++ b/llvm/lib/Target/X86/X86ISelLowering.cpp @@ -2494,14 +2494,14 @@ static bool hasStackGuardSlotTLS(const Triple &TargetTriple) { (TargetTriple.isAndroid() && !TargetTriple.isAndroidVersionLT(17)); } -static Constant* SegmentOffset(IRBuilder<> &IRB, +static Constant* SegmentOffset(IRBuilderBase &IRB, int Offset, unsigned AddressSpace) { return ConstantExpr::getIntToPtr( ConstantInt::get(Type::getInt32Ty(IRB.getContext()), Offset), Type::getInt8PtrTy(IRB.getContext())->getPointerTo(AddressSpace)); } -Value *X86TargetLowering::getIRStackGuard(IRBuilder<> &IRB) const { +Value *X86TargetLowering::getIRStackGuard(IRBuilderBase &IRB) const { // glibc, bionic, and Fuchsia have a special slot for the stack guard in // tcbhead_t; use it instead of the usual global variable (see // sysdeps/{i386,x86_64}/nptl/tls.h) @@ -2577,7 +2577,8 @@ Function *X86TargetLowering::getSSPStackGuardCheck(const Module &M) const { return TargetLowering::getSSPStackGuardCheck(M); } -Value *X86TargetLowering::getSafeStackPointerLocation(IRBuilder<> &IRB) const { +Value * +X86TargetLowering::getSafeStackPointerLocation(IRBuilderBase &IRB) const { if (Subtarget.getTargetTriple().isOSContiki()) return getDefaultSafeStackPointerLocation(IRB, false); diff --git a/llvm/lib/Target/X86/X86ISelLowering.h b/llvm/lib/Target/X86/X86ISelLowering.h index d8b152aee5aa..869857bcc0d6 100644 --- a/llvm/lib/Target/X86/X86ISelLowering.h +++ b/llvm/lib/Target/X86/X86ISelLowering.h @@ -1357,7 +1357,7 @@ namespace llvm { /// If the target has a standard location for the stack protector cookie, /// returns the address of that location. Otherwise, returns nullptr. - Value *getIRStackGuard(IRBuilder<> &IRB) const override; + Value *getIRStackGuard(IRBuilderBase &IRB) const override; bool useLoadStackGuardNode() const override; bool useStackGuardXorFP() const override; @@ -1371,7 +1371,7 @@ namespace llvm { /// Return true if the target stores SafeStack pointer at a fixed offset in /// some non-standard address space, and populates the address space and /// offset as appropriate. - Value *getSafeStackPointerLocation(IRBuilder<> &IRB) const override; + Value *getSafeStackPointerLocation(IRBuilderBase &IRB) const override; std::pair BuildFILD(EVT DstVT, EVT SrcVT, const SDLoc &DL, SDValue Chain, SDValue Pointer,