Fix for PR1540: Specify F0, F1 are sub-registers of D0, etc.

llvm-svn: 39843
2007-07-13 23:55:50 +00:00 · 2007-07-13 23:55:50 +00:00 · 1fae1cd3e1
parent 03a0073b36
commit 1fae1cd3e1
1 changed files with 2 additions and 2 deletions
--- a/llvm/lib/Target/Sparc/SparcRegisterInfo.td
+++ b/llvm/lib/Target/Sparc/SparcRegisterInfo.td
@ -26,9 +26,9 @@ class Rf<bits<5> num, string n> : SparcReg<n> {
  let Num = num;
 }
 // Rd - Slots in the FP register file for 64-bit floating-point values.
-class Rd<bits<5> num, string n, list<Register> aliases> : SparcReg<n> {
+class Rd<bits<5> num, string n, list<Register> subregs> : SparcReg<n> {
  let Num = num;
-  let Aliases = aliases;
+  let SubRegs = subregs;
 }

 // Integer registers