forked from OSchip/llvm-project
[X86] Don't pass ParitySrc array into isAddSubOrSubAddMask. Instead use a bool output parameter to get the real piece of info we care about. NFC
The ParitySrc array is more of an implementation detail. A single bool to get the final parity is sufficient. llvm-svn: 333935
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@ -30452,8 +30452,9 @@ static SDValue combineTargetShuffle(SDValue N, SelectionDAG &DAG,
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/// Checks if the shuffle mask takes subsequent elements
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/// Checks if the shuffle mask takes subsequent elements
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/// alternately from two vectors.
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/// alternately from two vectors.
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/// For example <0, 5, 2, 7> or <8, 1, 10, 3, 12, 5, 14, 7> are both correct.
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/// For example <0, 5, 2, 7> or <8, 1, 10, 3, 12, 5, 14, 7> are both correct.
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static bool isAddSubOrSubAddMask(ArrayRef<int> Mask, int ParitySrc[2]) {
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static bool isAddSubOrSubAddMask(ArrayRef<int> Mask, bool &Op0Even) {
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int ParitySrc[2] = {-1, -1};
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unsigned Size = Mask.size();
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unsigned Size = Mask.size();
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for (unsigned i = 0; i != Size; ++i) {
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for (unsigned i = 0; i != Size; ++i) {
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int M = Mask[i];
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int M = Mask[i];
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@ -30475,6 +30476,7 @@ static bool isAddSubOrSubAddMask(ArrayRef<int> Mask, int ParitySrc[2]) {
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if (ParitySrc[0] < 0 || ParitySrc[1] < 0 || ParitySrc[0] == ParitySrc[1])
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if (ParitySrc[0] < 0 || ParitySrc[1] < 0 || ParitySrc[0] == ParitySrc[1])
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return false;
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return false;
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Op0Even = ParitySrc[0] == 0;
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return true;
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return true;
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}
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}
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@ -30533,12 +30535,12 @@ static bool isAddSubOrSubAdd(SDNode *N, const X86Subtarget &Subtarget,
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}
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}
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ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(N)->getMask();
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ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(N)->getMask();
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int ParitySrc[2] = {-1, -1};
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bool Op0Even;
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if (!isAddSubOrSubAddMask(Mask, ParitySrc))
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if (!isAddSubOrSubAddMask(Mask, Op0Even))
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return false;
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return false;
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// It's a subadd if the vector in the even parity is an FADD.
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// It's a subadd if the vector in the even parity is an FADD.
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IsSubAdd = ParitySrc[0] == 0 ? V1->getOpcode() == ISD::FADD
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IsSubAdd = Op0Even ? V1->getOpcode() == ISD::FADD
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: V2->getOpcode() == ISD::FADD;
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: V2->getOpcode() == ISD::FADD;
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Opnd0 = LHS;
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Opnd0 = LHS;
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@ -30576,13 +30578,13 @@ static SDValue combineShuffleToFMAddSub(SDNode *N,
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// Check for correct shuffle mask.
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// Check for correct shuffle mask.
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ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(N)->getMask();
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ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(N)->getMask();
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int ParitySrc[2] = {-1, -1};
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bool Op0Even;
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if (!isAddSubOrSubAddMask(Mask, ParitySrc))
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if (!isAddSubOrSubAddMask(Mask, Op0Even))
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return SDValue();
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return SDValue();
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// FMAddSub takes zeroth operand from FMSub node.
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// FMAddSub takes zeroth operand from FMSub node.
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SDLoc DL(N);
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SDLoc DL(N);
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bool IsSubAdd = ParitySrc[0] == 0 ? Op0 == FMAdd : Op1 == FMAdd;
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bool IsSubAdd = Op0Even ? Op0 == FMAdd : Op1 == FMAdd;
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unsigned Opcode = IsSubAdd ? X86ISD::FMSUBADD : X86ISD::FMADDSUB;
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unsigned Opcode = IsSubAdd ? X86ISD::FMSUBADD : X86ISD::FMADDSUB;
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return DAG.getNode(Opcode, DL, VT, FMAdd.getOperand(0), FMAdd.getOperand(1),
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return DAG.getNode(Opcode, DL, VT, FMAdd.getOperand(0), FMAdd.getOperand(1),
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FMAdd.getOperand(2));
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FMAdd.getOperand(2));
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