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[AMDGPU] Simplify calls to getDefSrcRegIgnoringCopies. NFC. 

getDefSrcRegIgnoringCopies never returns None on valid MIR.
This commit is contained in:
Jay Foad 2022-04-20 12:37:02 +01:00
parent 4cec789c17
commit 1f91512268
1 changed files with 3 additions and 16 deletions
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19
llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
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@ -3626,9 +3626,6 @@ AMDGPUInstructionSelector::selectGlobalSAddr(MachineOperand &Root) const {
ImmOffset = ConstOffset;
} else {
auto PtrBaseDef = getDefSrcRegIgnoringCopies(PtrBase, *MRI);
if (!PtrBaseDef)
return None;
if (isSGPR(PtrBaseDef->Reg)) {
if (ConstOffset > 0) {
// Offset is too large.
@ -3674,11 +3671,8 @@ AMDGPUInstructionSelector::selectGlobalSAddr(MachineOperand &Root) const {
}
}
auto AddrDef = getDefSrcRegIgnoringCopies(Addr, *MRI);
if (!AddrDef)
return None;
// Match the variable offset.
auto AddrDef = getDefSrcRegIgnoringCopies(Addr, *MRI);
if (AddrDef->MI->getOpcode() == AMDGPU::G_PTR_ADD) {
// Look through the SGPR->VGPR copy.
Register SAddr =
@ -3744,9 +3738,6 @@ AMDGPUInstructionSelector::selectScratchSAddr(MachineOperand &Root) const {
}
auto AddrDef = getDefSrcRegIgnoringCopies(Addr, *MRI);
if (!AddrDef)
return None;
if (AddrDef->MI->getOpcode() == AMDGPU::G_FRAME_INDEX) {
int FI = AddrDef->MI->getOperand(1).getIndex();
return {{
@ -3763,8 +3754,7 @@ AMDGPUInstructionSelector::selectScratchSAddr(MachineOperand &Root) const {
auto LHSDef = getDefSrcRegIgnoringCopies(LHS, *MRI);
auto RHSDef = getDefSrcRegIgnoringCopies(RHS, *MRI);
if (LHSDef && RHSDef &&
LHSDef->MI->getOpcode() == AMDGPU::G_FRAME_INDEX &&
if (LHSDef->MI->getOpcode() == AMDGPU::G_FRAME_INDEX &&
isSGPR(RHSDef->Reg)) {
int FI = LHSDef->MI->getOperand(1).getIndex();
MachineInstr &I = *Root.getParent();
@ -3805,9 +3795,6 @@ AMDGPUInstructionSelector::selectScratchSVAddr(MachineOperand &Root) const {
}
auto AddrDef = getDefSrcRegIgnoringCopies(Addr, *MRI);
if (!AddrDef)
return None;
if (AddrDef->MI->getOpcode() != AMDGPU::G_PTR_ADD)
return None;
@ -3818,7 +3805,7 @@ AMDGPUInstructionSelector::selectScratchSVAddr(MachineOperand &Root) const {
Register LHS = AddrDef->MI->getOperand(1).getReg();
auto LHSDef = getDefSrcRegIgnoringCopies(LHS, *MRI);
if (LHSDef && LHSDef->MI->getOpcode() == AMDGPU::G_FRAME_INDEX) {
if (LHSDef->MI->getOpcode() == AMDGPU::G_FRAME_INDEX) {
int FI = LHSDef->MI->getOperand(1).getIndex();
return {{
[=](MachineInstrBuilder &MIB) { MIB.addReg(RHS); }, // vaddr