From 1f83777bd39baa9af46b56cc30fe9eced798f74f Mon Sep 17 00:00:00 2001
From: Amara Emerson <aemerson@apple.com>
Date: Sun, 8 Oct 2017 15:29:35 +0000
Subject: [PATCH] [AArch64][GlobalISel] Add a test case for G_PHI of p0
 instruction selection.

llvm-svn: 315179
---
 .../CodeGen/AArch64/GlobalISel/select-phi.mir | 45 +++++++++++++++++++
 1 file changed, 45 insertions(+)

diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-phi.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-phi.mir
index 5a56e79c46e0..cbdab49da98d 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/select-phi.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-phi.mir
@@ -23,6 +23,11 @@
     ret i32 %res
   }
 
+  define i64* @test_phi_ptr(i64* %a, i64* %b, i1 %cond) {
+  entry:
+    ret i64* null
+  }
+
 ...
 ---
 name:            test_phi
@@ -76,3 +81,43 @@ body:             |
     RET_ReallyLR implicit %w0
 
 ...
+
+---
+name:            test_phi_ptr
+alignment:       2
+exposesReturnsTwice: false
+legalized:       true
+regBankSelected: true
+selected:        false
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr, preferred-register: '' }
+  - { id: 1, class: gpr, preferred-register: '' }
+  - { id: 2, class: gpr, preferred-register: '' }
+  - { id: 3, class: gpr, preferred-register: '' }
+  - { id: 4, class: _, preferred-register: '' }
+  - { id: 5, class: _, preferred-register: '' }
+liveins:
+body:             |
+  bb.0:
+    successors: %bb.1, %bb.2
+    liveins: %w2, %x0, %x1
+    ; CHECK-LABEL: name: test_phi_ptr
+
+    %0(p0) = COPY %x0
+    %1(p0) = COPY %x1
+    %2(s1) = COPY %w2
+    G_BRCOND %2(s1), %bb.1
+    G_BR %bb.2
+
+  bb.1:
+    successors: %bb.2
+
+
+  bb.2:
+    ; CHECK: %{{[0-9]+}} = PHI %{{[0-9]+}}, %bb.0, %{{[0-9]+}}, %bb.1
+    %3(p0) = G_PHI %0(p0), %bb.0, %1(p0), %bb.1
+    %x0 = COPY %3(p0)
+    RET_ReallyLR implicit %x0
+
+...