forked from OSchip/llvm-project
[ARM] OrCombineToBFI function
Extract the functionality to combine OR to BFI into its own function. Differential Revision: https://reviews.llvm.org/D39001 llvm-svn: 316563
This commit is contained in:
Sam Parker
parent
ccb209bb97
commit
1f742117bd
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@ -10357,6 +10357,132 @@ static SDValue PerformORCombineToSMULWBT(SDNode *OR,
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return SDValue(OR, 0);
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}
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static SDValue PerformORCombineToBFI(SDNode *N,
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TargetLowering::DAGCombinerInfo &DCI,
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const ARMSubtarget *Subtarget) {
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// BFI is only available on V6T2+
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if (Subtarget->isThumb1Only() || !Subtarget->hasV6T2Ops())
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return SDValue();
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EVT VT = N->getValueType(0);
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SDValue N0 = N->getOperand(0);
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SDValue N1 = N->getOperand(1);
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SelectionDAG &DAG = DCI.DAG;
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SDLoc DL(N);
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// 1) or (and A, mask), val => ARMbfi A, val, mask
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// iff (val & mask) == val
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//
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// 2) or (and A, mask), (and B, mask2) => ARMbfi A, (lsr B, amt), mask
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// 2a) iff isBitFieldInvertedMask(mask) && isBitFieldInvertedMask(~mask2)
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// && mask == ~mask2
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// 2b) iff isBitFieldInvertedMask(~mask) && isBitFieldInvertedMask(mask2)
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// && ~mask == mask2
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// (i.e., copy a bitfield value into another bitfield of the same width)
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if (VT != MVT::i32)
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return SDValue();
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SDValue N00 = N0.getOperand(0);
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// The value and the mask need to be constants so we can verify this is
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// actually a bitfield set. If the mask is 0xffff, we can do better
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// via a movt instruction, so don't use BFI in that case.
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SDValue MaskOp = N0.getOperand(1);
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ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(MaskOp);
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if (!MaskC)
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return SDValue();
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unsigned Mask = MaskC->getZExtValue();
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if (Mask == 0xffff)
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return SDValue();
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SDValue Res;
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// Case (1): or (and A, mask), val => ARMbfi A, val, mask
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ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
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if (N1C) {
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unsigned Val = N1C->getZExtValue();
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if ((Val & ~Mask) != Val)
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return SDValue();
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if (ARM::isBitFieldInvertedMask(Mask)) {
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Val >>= countTrailingZeros(~Mask);
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Res = DAG.getNode(ARMISD::BFI, DL, VT, N00,
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DAG.getConstant(Val, DL, MVT::i32),
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DAG.getConstant(Mask, DL, MVT::i32));
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DCI.CombineTo(N, Res, false);
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// Return value from the original node to inform the combiner than N is
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// now dead.
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return SDValue(N, 0);
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}
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} else if (N1.getOpcode() == ISD::AND) {
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// case (2) or (and A, mask), (and B, mask2) => ARMbfi A, (lsr B, amt), mask
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ConstantSDNode *N11C = dyn_cast<ConstantSDNode>(N1.getOperand(1));
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if (!N11C)
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return SDValue();
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unsigned Mask2 = N11C->getZExtValue();
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// Mask and ~Mask2 (or reverse) must be equivalent for the BFI pattern
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// as is to match.
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if (ARM::isBitFieldInvertedMask(Mask) &&
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(Mask == ~Mask2)) {
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// The pack halfword instruction works better for masks that fit it,
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// so use that when it's available.
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if (Subtarget->hasDSP() &&
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(Mask == 0xffff || Mask == 0xffff0000))
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return SDValue();
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// 2a
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unsigned amt = countTrailingZeros(Mask2);
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Res = DAG.getNode(ISD::SRL, DL, VT, N1.getOperand(0),
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DAG.getConstant(amt, DL, MVT::i32));
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Res = DAG.getNode(ARMISD::BFI, DL, VT, N00, Res,
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DAG.getConstant(Mask, DL, MVT::i32));
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DCI.CombineTo(N, Res, false);
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// Return value from the original node to inform the combiner than N is
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// now dead.
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return SDValue(N, 0);
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} else if (ARM::isBitFieldInvertedMask(~Mask) &&
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(~Mask == Mask2)) {
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// The pack halfword instruction works better for masks that fit it,
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// so use that when it's available.
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if (Subtarget->hasDSP() &&
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(Mask2 == 0xffff || Mask2 == 0xffff0000))
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return SDValue();
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// 2b
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unsigned lsb = countTrailingZeros(Mask);
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Res = DAG.getNode(ISD::SRL, DL, VT, N00,
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DAG.getConstant(lsb, DL, MVT::i32));
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Res = DAG.getNode(ARMISD::BFI, DL, VT, N1.getOperand(0), Res,
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DAG.getConstant(Mask2, DL, MVT::i32));
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DCI.CombineTo(N, Res, false);
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// Return value from the original node to inform the combiner than N is
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// now dead.
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return SDValue(N, 0);
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}
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}
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if (DAG.MaskedValueIsZero(N1, MaskC->getAPIntValue()) &&
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N00.getOpcode() == ISD::SHL && isa<ConstantSDNode>(N00.getOperand(1)) &&
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ARM::isBitFieldInvertedMask(~Mask)) {
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// Case (3): or (and (shl A, #shamt), mask), B => ARMbfi B, A, ~mask
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// where lsb(mask) == #shamt and masked bits of B are known zero.
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SDValue ShAmt = N00.getOperand(1);
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unsigned ShAmtC = cast<ConstantSDNode>(ShAmt)->getZExtValue();
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unsigned LSB = countTrailingZeros(Mask);
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if (ShAmtC != LSB)
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return SDValue();
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Res = DAG.getNode(ARMISD::BFI, DL, VT, N1, N00.getOperand(0),
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DAG.getConstant(~Mask, DL, MVT::i32));
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DCI.CombineTo(N, Res, false);
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// Return value from the original node to inform the combiner than N is
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// now dead.
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return SDValue(N, 0);
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}
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return SDValue();
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}
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/// PerformORCombine - Target-specific dag combine xforms for ISD::OR
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static SDValue PerformORCombine(SDNode *N,
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TargetLowering::DAGCombinerInfo &DCI,
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@ -10441,117 +10567,8 @@ static SDValue PerformORCombine(SDNode *N,
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// Try to use the ARM/Thumb2 BFI (bitfield insert) instruction when
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// reasonable.
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// BFI is only available on V6T2+
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if (Subtarget->isThumb1Only() || !Subtarget->hasV6T2Ops())
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return SDValue();
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SDLoc DL(N);
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// 1) or (and A, mask), val => ARMbfi A, val, mask
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// iff (val & mask) == val
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//
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// 2) or (and A, mask), (and B, mask2) => ARMbfi A, (lsr B, amt), mask
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// 2a) iff isBitFieldInvertedMask(mask) && isBitFieldInvertedMask(~mask2)
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// && mask == ~mask2
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// 2b) iff isBitFieldInvertedMask(~mask) && isBitFieldInvertedMask(mask2)
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// && ~mask == mask2
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// (i.e., copy a bitfield value into another bitfield of the same width)
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if (VT != MVT::i32)
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return SDValue();
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SDValue N00 = N0.getOperand(0);
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// The value and the mask need to be constants so we can verify this is
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// actually a bitfield set. If the mask is 0xffff, we can do better
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// via a movt instruction, so don't use BFI in that case.
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SDValue MaskOp = N0.getOperand(1);
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ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(MaskOp);
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if (!MaskC)
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return SDValue();
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unsigned Mask = MaskC->getZExtValue();
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if (Mask == 0xffff)
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return SDValue();
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SDValue Res;
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// Case (1): or (and A, mask), val => ARMbfi A, val, mask
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ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
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if (N1C) {
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unsigned Val = N1C->getZExtValue();
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if ((Val & ~Mask) != Val)
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return SDValue();
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if (ARM::isBitFieldInvertedMask(Mask)) {
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Val >>= countTrailingZeros(~Mask);
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Res = DAG.getNode(ARMISD::BFI, DL, VT, N00,
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DAG.getConstant(Val, DL, MVT::i32),
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DAG.getConstant(Mask, DL, MVT::i32));
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// Do not add new nodes to DAG combiner worklist.
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DCI.CombineTo(N, Res, false);
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return SDValue();
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}
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} else if (N1.getOpcode() == ISD::AND) {
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// case (2) or (and A, mask), (and B, mask2) => ARMbfi A, (lsr B, amt), mask
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ConstantSDNode *N11C = dyn_cast<ConstantSDNode>(N1.getOperand(1));
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if (!N11C)
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return SDValue();
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unsigned Mask2 = N11C->getZExtValue();
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// Mask and ~Mask2 (or reverse) must be equivalent for the BFI pattern
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// as is to match.
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if (ARM::isBitFieldInvertedMask(Mask) &&
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(Mask == ~Mask2)) {
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// The pack halfword instruction works better for masks that fit it,
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// so use that when it's available.
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if (Subtarget->hasDSP() &&
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(Mask == 0xffff || Mask == 0xffff0000))
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return SDValue();
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// 2a
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unsigned amt = countTrailingZeros(Mask2);
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Res = DAG.getNode(ISD::SRL, DL, VT, N1.getOperand(0),
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DAG.getConstant(amt, DL, MVT::i32));
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Res = DAG.getNode(ARMISD::BFI, DL, VT, N00, Res,
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DAG.getConstant(Mask, DL, MVT::i32));
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// Do not add new nodes to DAG combiner worklist.
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DCI.CombineTo(N, Res, false);
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return SDValue();
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} else if (ARM::isBitFieldInvertedMask(~Mask) &&
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(~Mask == Mask2)) {
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// The pack halfword instruction works better for masks that fit it,
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// so use that when it's available.
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if (Subtarget->hasDSP() &&
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(Mask2 == 0xffff || Mask2 == 0xffff0000))
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return SDValue();
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// 2b
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unsigned lsb = countTrailingZeros(Mask);
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Res = DAG.getNode(ISD::SRL, DL, VT, N00,
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DAG.getConstant(lsb, DL, MVT::i32));
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Res = DAG.getNode(ARMISD::BFI, DL, VT, N1.getOperand(0), Res,
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DAG.getConstant(Mask2, DL, MVT::i32));
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// Do not add new nodes to DAG combiner worklist.
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DCI.CombineTo(N, Res, false);
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return SDValue();
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}
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}
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if (DAG.MaskedValueIsZero(N1, MaskC->getAPIntValue()) &&
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N00.getOpcode() == ISD::SHL && isa<ConstantSDNode>(N00.getOperand(1)) &&
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ARM::isBitFieldInvertedMask(~Mask)) {
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// Case (3): or (and (shl A, #shamt), mask), B => ARMbfi B, A, ~mask
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// where lsb(mask) == #shamt and masked bits of B are known zero.
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SDValue ShAmt = N00.getOperand(1);
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unsigned ShAmtC = cast<ConstantSDNode>(ShAmt)->getZExtValue();
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unsigned LSB = countTrailingZeros(Mask);
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if (ShAmtC != LSB)
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return SDValue();
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Res = DAG.getNode(ARMISD::BFI, DL, VT, N1, N00.getOperand(0),
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DAG.getConstant(~Mask, DL, MVT::i32));
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// Do not add new nodes to DAG combiner worklist.
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DCI.CombineTo(N, Res, false);
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}
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if (SDValue Res = PerformORCombineToBFI(N, DCI, Subtarget))
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return Res;
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return SDValue();
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}
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