From 1f5d9941192d9a5876c44d6c274b4447b9bf2099 Mon Sep 17 00:00:00 2001
From: Amara Emerson <aemerson@apple.com>
Date: Wed, 25 Apr 2018 14:43:59 +0000
Subject: [PATCH] [AArch64][GlobalISel] Implement selection for the llvm.trap
 intrinsic.

rdar://38674040

llvm-svn: 330831
---
 .../AArch64/AArch64InstructionSelector.cpp    |  9 ++++++
 .../AArch64/GlobalISel/select-trap.mir        | 32 +++++++++++++++++++
 2 files changed, 41 insertions(+)
 create mode 100644 llvm/test/CodeGen/AArch64/GlobalISel/select-trap.mir

diff --git a/llvm/lib/Target/AArch64/AArch64InstructionSelector.cpp b/llvm/lib/Target/AArch64/AArch64InstructionSelector.cpp
index 309f6128e5b4..4124302e8abe 100644
--- a/llvm/lib/Target/AArch64/AArch64InstructionSelector.cpp
+++ b/llvm/lib/Target/AArch64/AArch64InstructionSelector.cpp
@@ -1466,6 +1466,15 @@ bool AArch64InstructionSelector::select(MachineInstr &I,
   case TargetOpcode::G_VASTART:
     return STI.isTargetDarwin() ? selectVaStartDarwin(I, MF, MRI)
                                 : selectVaStartAAPCS(I, MF, MRI);
+  case TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS:
+    if (!I.getOperand(0).isIntrinsicID())
+      return false;
+    if (I.getOperand(0).getIntrinsicID() != Intrinsic::trap)
+      return false;
+    BuildMI(MBB, I, I.getDebugLoc(), TII.get(AArch64::BRK))
+      .addImm(1);
+    I.eraseFromParent();
+    return true;
   case TargetOpcode::G_IMPLICIT_DEF:
     I.setDesc(TII.get(TargetOpcode::IMPLICIT_DEF));
     const LLT DstTy = MRI.getType(I.getOperand(0).getReg());
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-trap.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-trap.mir
new file mode 100644
index 000000000000..31c42bbcb853
--- /dev/null
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-trap.mir
@@ -0,0 +1,32 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -mtriple=aarch64-- -run-pass=instruction-select -verify-machineinstrs -global-isel %s -o - | FileCheck %s
+--- |
+  target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"
+  target triple = "aarch64"
+
+  ; Function Attrs: noreturn nounwind
+  declare void @llvm.trap() #0
+
+  define void @foo() {
+    call void @llvm.trap()
+    ret void
+  }
+
+  attributes #0 = { noreturn nounwind }
+
+...
+---
+name:            foo
+alignment:       2
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+body:             |
+  bb.1 (%ir-block.0):
+    ; CHECK-LABEL: name: foo
+    ; CHECK: BRK 1
+    ; CHECK: RET_ReallyLR
+    G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.trap)
+    RET_ReallyLR
+
+...