forked from OSchip/llvm-project
[x86] Clean up and generate detailed FileCheck assertions for
avx-sext.ll using my new script. Also add an AVX2 mode to this test. Part of cleaning up the test suite before enabling the new vector shuffle lowering. This also highlights some of the abysmal failures of the old shuffle lowering. Check out those 'pinsrw' and 'pextrw' sequences! llvm-svn: 218794
This commit is contained in:
Chandler Carruth
parent
c7b719fc03
commit
1f569b05b6
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@ -1,198 +1,440 @@
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; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=corei7-avx | FileCheck %s -check-prefix=AVX
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; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=core2 | FileCheck %s -check-prefix=SSSE3
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; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=pentium4 | FileCheck %s -check-prefix=SSE2
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; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=corei7-avx | FileCheck %s --check-prefix=AVX --check-prefix=AVX1
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; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=core-avx2 | FileCheck %s --check-prefix=AVX --check-prefix=AVX2
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; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=core2 | FileCheck %s --check-prefix=SSE --check-prefix=SSSE3
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; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=pentium4 | FileCheck %s --check-prefix=SSE --check-prefix=SSE2
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define <8 x i32> @sext_8i16_to_8i32(<8 x i16> %A) nounwind uwtable readnone ssp {
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; AVX: sext_8i16_to_8i32
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; AVX: vpmovsxwd
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; AVX1-LABEL: sext_8i16_to_8i32:
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; AVX1: ## BB#0:
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; AVX1-NEXT: vpmovsxwd %xmm0, %xmm1
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; AVX1-NEXT: vmovhlps {{.*#+}} xmm0 = xmm0[1,1]
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; AVX1-NEXT: vpmovsxwd %xmm0, %xmm0
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; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0
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; AVX1-NEXT: retq
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;
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; AVX2-LABEL: sext_8i16_to_8i32:
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; AVX2: ## BB#0:
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; AVX2-NEXT: vpmovsxwd %xmm0, %ymm0
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; AVX2-NEXT: retq
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;
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; SSE-LABEL: sext_8i16_to_8i32:
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; SSE: ## BB#0:
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; SSE-NEXT: movdqa %xmm0, %xmm1
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; SSE-NEXT: ## kill: XMM0<def> XMM1<kill>
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; SSE-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3]
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; SSE-NEXT: pslld $16, %xmm0
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; SSE-NEXT: psrad $16, %xmm0
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; SSE-NEXT: punpckhwd {{.*#+}} xmm1 = xmm1[4],xmm0[4],xmm1[5],xmm0[5],xmm1[6],xmm0[6],xmm1[7],xmm0[7]
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; SSE-NEXT: pslld $16, %xmm1
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; SSE-NEXT: psrad $16, %xmm1
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; SSE-NEXT: retq
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%B = sext <8 x i16> %A to <8 x i32>
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ret <8 x i32>%B
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}
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define <4 x i64> @sext_4i32_to_4i64(<4 x i32> %A) nounwind uwtable readnone ssp {
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; AVX: sext_4i32_to_4i64
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; AVX: vpmovsxdq
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; AVX1-LABEL: sext_4i32_to_4i64:
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; AVX1: ## BB#0:
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; AVX1-NEXT: vpmovsxdq %xmm0, %xmm1
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; AVX1-NEXT: vmovhlps {{.*#+}} xmm0 = xmm0[1,1]
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; AVX1-NEXT: vpmovsxdq %xmm0, %xmm0
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; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0
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; AVX1-NEXT: retq
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;
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; AVX2-LABEL: sext_4i32_to_4i64:
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; AVX2: ## BB#0:
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; AVX2-NEXT: vpmovsxdq %xmm0, %ymm0
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; AVX2-NEXT: retq
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;
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; SSE-LABEL: sext_4i32_to_4i64:
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; SSE: ## BB#0:
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; SSE-NEXT: pshufd {{.*#+}} xmm1 = xmm0[0,0,1,0]
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; SSE-NEXT: movd %xmm1, %rax
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; SSE-NEXT: cltq
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; SSE-NEXT: movd %rax, %xmm2
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; SSE-NEXT: punpckhqdq {{.*#+}} xmm1 = xmm1[1,1]
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; SSE-NEXT: movd %xmm1, %rax
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; SSE-NEXT: cltq
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; SSE-NEXT: movd %rax, %xmm1
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; SSE-NEXT: punpcklqdq {{.*#+}} xmm2 = xmm2[0],xmm1[0]
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; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[2,0,3,0]
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; SSE-NEXT: movd %xmm0, %rax
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; SSE-NEXT: cltq
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; SSE-NEXT: movd %rax, %xmm1
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; SSE-NEXT: punpckhqdq {{.*#+}} xmm0 = xmm0[1,1]
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; SSE-NEXT: movd %xmm0, %rax
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; SSE-NEXT: cltq
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; SSE-NEXT: movd %rax, %xmm0
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; SSE-NEXT: punpcklqdq {{.*#+}} xmm1 = xmm1[0],xmm0[0]
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; SSE-NEXT: movdqa %xmm2, %xmm0
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; SSE-NEXT: retq
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%B = sext <4 x i32> %A to <4 x i64>
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ret <4 x i64>%B
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}
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; AVX: load_sext_test1
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; AVX: vpmovsxwd (%r{{[^,]*}}), %xmm{{.*}}
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; AVX: ret
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; SSSE3: load_sext_test1
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; SSSE3: movq
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; SSSE3: punpcklwd %xmm{{.*}}, %xmm{{.*}}
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; SSSE3: psrad $16
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; SSSE3: ret
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; SSE2: load_sext_test1
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; SSE2: movq
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; SSE2: punpcklwd %xmm{{.*}}, %xmm{{.*}}
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; SSE2: psrad $16
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; SSE2: ret
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define <4 x i32> @load_sext_test1(<4 x i16> *%ptr) {
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; AVX-LABEL: load_sext_test1:
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; AVX: ## BB#0:
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; AVX-NEXT: vpmovsxwd (%rdi), %xmm0
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; AVX-NEXT: retq
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;
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; SSE-LABEL: load_sext_test1:
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; SSE: ## BB#0:
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; SSE-NEXT: movq (%rdi), %xmm0
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; SSE-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3]
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; SSE-NEXT: psrad $16, %xmm0
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; SSE-NEXT: retq
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%X = load <4 x i16>* %ptr
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%Y = sext <4 x i16> %X to <4 x i32>
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ret <4 x i32>%Y
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}
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; AVX: load_sext_test2
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; AVX: vpmovsxbd (%r{{[^,]*}}), %xmm{{.*}}
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; AVX: ret
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; SSSE3: load_sext_test2
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; SSSE3: movd
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; SSSE3: pshufb
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; SSSE3: psrad $24
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; SSSE3: ret
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; SSE2: load_sext_test2
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; SSE2: movl
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; SSE2: psrad $24
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; SSE2: ret
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define <4 x i32> @load_sext_test2(<4 x i8> *%ptr) {
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; AVX-LABEL: load_sext_test2:
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; AVX: ## BB#0:
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; AVX-NEXT: vpmovsxbd (%rdi), %xmm0
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; AVX-NEXT: retq
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;
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; SSSE3-LABEL: load_sext_test2:
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; SSSE3: ## BB#0:
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; SSSE3-NEXT: movd (%rdi), %xmm0
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; SSSE3-NEXT: pshufb {{.*#+}} xmm0 = zero,zero,zero,xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero,xmm0[2],zero,zero,zero,xmm0[3]
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; SSSE3-NEXT: psrad $24, %xmm0
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; SSSE3-NEXT: retq
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;
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; SSE2-LABEL: load_sext_test2:
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; SSE2: ## BB#0:
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; SSE2-NEXT: movl (%rdi), %eax
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; SSE2-NEXT: movl %eax, %ecx
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; SSE2-NEXT: shll $8, %ecx
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; SSE2-NEXT: movd %eax, %xmm0
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; SSE2-NEXT: pextrw $1, %xmm0, %edx
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; SSE2-NEXT: pinsrw $1, %ecx, %xmm0
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; SSE2-NEXT: pinsrw $3, %eax, %xmm0
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; SSE2-NEXT: movl %edx, %eax
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; SSE2-NEXT: shll $8, %eax
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; SSE2-NEXT: pinsrw $5, %eax, %xmm0
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; SSE2-NEXT: pinsrw $7, %edx, %xmm0
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; SSE2-NEXT: psrad $24, %xmm0
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; SSE2-NEXT: retq
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%X = load <4 x i8>* %ptr
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%Y = sext <4 x i8> %X to <4 x i32>
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ret <4 x i32>%Y
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}
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; AVX: load_sext_test3
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; AVX: vpmovsxbq (%r{{[^,]*}}), %xmm{{.*}}
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; AVX: ret
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; SSSE3: load_sext_test3
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; SSSE3: movsbq
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; SSSE3: movsbq
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; SSSE3: punpcklqdq
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; SSSE3: ret
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; SSE2: load_sext_test3
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; SSE2: movsbq
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; SSE2: movsbq
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; SSE2: punpcklqdq
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; SSE2: ret
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define <2 x i64> @load_sext_test3(<2 x i8> *%ptr) {
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; AVX-LABEL: load_sext_test3:
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; AVX: ## BB#0:
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; AVX-NEXT: vpmovsxbq (%rdi), %xmm0
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; AVX-NEXT: retq
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;
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; SSE-LABEL: load_sext_test3:
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; SSE: ## BB#0:
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; SSE-NEXT: movsbq 1(%rdi), %rax
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; SSE-NEXT: movd %rax, %xmm1
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; SSE-NEXT: movsbq (%rdi), %rax
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; SSE-NEXT: movd %rax, %xmm0
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; SSE-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
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; SSE-NEXT: retq
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%X = load <2 x i8>* %ptr
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%Y = sext <2 x i8> %X to <2 x i64>
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ret <2 x i64>%Y
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}
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; AVX: load_sext_test4
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; AVX: vpmovsxwq (%r{{[^,]*}}), %xmm{{.*}}
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; AVX: ret
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; SSSE3: load_sext_test4
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; SSSE3: movswq
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; SSSE3: movswq
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; SSSE3: punpcklqdq
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; SSSE3: ret
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; SSE2: load_sext_test4
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; SSE2: movswq
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; SSE2: movswq
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; SSE2: punpcklqdq
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; SSE2: ret
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define <2 x i64> @load_sext_test4(<2 x i16> *%ptr) {
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; AVX-LABEL: load_sext_test4:
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; AVX: ## BB#0:
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; AVX-NEXT: vpmovsxwq (%rdi), %xmm0
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; AVX-NEXT: retq
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;
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; SSE-LABEL: load_sext_test4:
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; SSE: ## BB#0:
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; SSE-NEXT: movswq 2(%rdi), %rax
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; SSE-NEXT: movd %rax, %xmm1
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; SSE-NEXT: movswq (%rdi), %rax
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; SSE-NEXT: movd %rax, %xmm0
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; SSE-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
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; SSE-NEXT: retq
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%X = load <2 x i16>* %ptr
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%Y = sext <2 x i16> %X to <2 x i64>
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ret <2 x i64>%Y
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}
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; AVX: load_sext_test5
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; AVX: vpmovsxdq (%r{{[^,]*}}), %xmm{{.*}}
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; AVX: ret
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; SSSE3: load_sext_test5
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; SSSE3: movslq
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; SSSE3: movslq
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; SSSE3: punpcklqdq
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; SSSE3: ret
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; SSE2: load_sext_test5
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; SSE2: movslq
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; SSE2: movslq
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; SSE2: punpcklqdq
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; SSE2: ret
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define <2 x i64> @load_sext_test5(<2 x i32> *%ptr) {
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; AVX-LABEL: load_sext_test5:
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; AVX: ## BB#0:
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; AVX-NEXT: vpmovsxdq (%rdi), %xmm0
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; AVX-NEXT: retq
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;
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; SSE-LABEL: load_sext_test5:
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; SSE: ## BB#0:
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; SSE-NEXT: movslq 4(%rdi), %rax
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; SSE-NEXT: movd %rax, %xmm1
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; SSE-NEXT: movslq (%rdi), %rax
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; SSE-NEXT: movd %rax, %xmm0
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; SSE-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
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; SSE-NEXT: retq
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%X = load <2 x i32>* %ptr
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%Y = sext <2 x i32> %X to <2 x i64>
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ret <2 x i64>%Y
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}
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; AVX: load_sext_test6
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; AVX: vpmovsxbw (%r{{[^,]*}}), %xmm{{.*}}
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; AVX: ret
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; SSSE3: load_sext_test6
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; SSSE3: movq
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; SSSE3: punpcklbw
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; SSSE3: psraw $8
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; SSSE3: ret
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; SSE2: load_sext_test6
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; SSE2: movq
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; SSE2: punpcklbw
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; SSE2: psraw $8
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; SSE2: ret
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define <8 x i16> @load_sext_test6(<8 x i8> *%ptr) {
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; AVX-LABEL: load_sext_test6:
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; AVX: ## BB#0:
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; AVX-NEXT: vpmovsxbw (%rdi), %xmm0
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; AVX-NEXT: retq
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;
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; SSE-LABEL: load_sext_test6:
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; SSE: ## BB#0:
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; SSE-NEXT: movq (%rdi), %xmm0
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; SSE-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7]
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; SSE-NEXT: psraw $8, %xmm0
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; SSE-NEXT: retq
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%X = load <8 x i8>* %ptr
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%Y = sext <8 x i8> %X to <8 x i16>
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ret <8 x i16>%Y
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}
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; AVX: sext_4i1_to_4i64
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; AVX: vpslld $31
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; AVX: vpsrad $31
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; AVX: vpmovsxdq
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; AVX: vpmovsxdq
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; AVX: ret
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define <4 x i64> @sext_4i1_to_4i64(<4 x i1> %mask) {
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; AVX1-LABEL: sext_4i1_to_4i64:
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; AVX1: ## BB#0:
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; AVX1-NEXT: vpslld $31, %xmm0, %xmm0
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; AVX1-NEXT: vpsrad $31, %xmm0, %xmm0
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; AVX1-NEXT: vpmovsxdq %xmm0, %xmm1
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; AVX1-NEXT: vmovhlps {{.*#+}} xmm0 = xmm0[1,1]
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; AVX1-NEXT: vpmovsxdq %xmm0, %xmm0
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; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0
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; AVX1-NEXT: retq
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;
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; AVX2-LABEL: sext_4i1_to_4i64:
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; AVX2: ## BB#0:
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; AVX2-NEXT: vpslld $31, %xmm0, %xmm0
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; AVX2-NEXT: vpsrad $31, %xmm0, %xmm0
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; AVX2-NEXT: vpmovsxdq %xmm0, %ymm0
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; AVX2-NEXT: retq
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;
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; SSE-LABEL: sext_4i1_to_4i64:
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; SSE: ## BB#0:
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; SSE-NEXT: pslld $31, %xmm0
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; SSE-NEXT: psrad $31, %xmm0
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; SSE-NEXT: pshufd {{.*#+}} xmm1 = xmm0[0,0,1,0]
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; SSE-NEXT: movd %xmm1, %rax
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; SSE-NEXT: cltq
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; SSE-NEXT: movd %rax, %xmm2
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; SSE-NEXT: punpckhqdq {{.*#+}} xmm1 = xmm1[1,1]
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; SSE-NEXT: movd %xmm1, %rax
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; SSE-NEXT: cltq
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; SSE-NEXT: movd %rax, %xmm1
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; SSE-NEXT: punpcklqdq {{.*#+}} xmm2 = xmm2[0],xmm1[0]
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; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[2,0,3,0]
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; SSE-NEXT: movd %xmm0, %rax
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; SSE-NEXT: cltq
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; SSE-NEXT: movd %rax, %xmm1
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; SSE-NEXT: punpckhqdq {{.*#+}} xmm0 = xmm0[1,1]
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; SSE-NEXT: movd %xmm0, %rax
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; SSE-NEXT: cltq
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; SSE-NEXT: movd %rax, %xmm0
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; SSE-NEXT: punpcklqdq {{.*#+}} xmm1 = xmm1[0],xmm0[0]
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; SSE-NEXT: movdqa %xmm2, %xmm0
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; SSE-NEXT: retq
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%extmask = sext <4 x i1> %mask to <4 x i64>
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ret <4 x i64> %extmask
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}
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; AVX-LABEL: sext_16i8_to_16i16
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; AVX: vpmovsxbw
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; AVX: vmovhlps
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; AVX: vpmovsxbw
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; AVX: ret
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define <16 x i16> @sext_16i8_to_16i16(<16 x i8> *%ptr) {
|
||||
; AVX1-LABEL: sext_16i8_to_16i16:
|
||||
; AVX1: ## BB#0:
|
||||
; AVX1-NEXT: vmovdqa (%rdi), %xmm0
|
||||
; AVX1-NEXT: vpmovsxbw %xmm0, %xmm1
|
||||
; AVX1-NEXT: vmovhlps {{.*#+}} xmm0 = xmm0[1,1]
|
||||
; AVX1-NEXT: vpmovsxbw %xmm0, %xmm0
|
||||
; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0
|
||||
; AVX1-NEXT: retq
|
||||
;
|
||||
; AVX2-LABEL: sext_16i8_to_16i16:
|
||||
; AVX2: ## BB#0:
|
||||
; AVX2-NEXT: vmovdqa (%rdi), %xmm0
|
||||
; AVX2-NEXT: vpmovsxbw %xmm0, %ymm0
|
||||
; AVX2-NEXT: retq
|
||||
;
|
||||
; SSE-LABEL: sext_16i8_to_16i16:
|
||||
; SSE: ## BB#0:
|
||||
; SSE-NEXT: movdqa (%rdi), %xmm1
|
||||
; SSE-NEXT: movdqa %xmm1, %xmm0
|
||||
; SSE-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7]
|
||||
; SSE-NEXT: psllw $8, %xmm0
|
||||
; SSE-NEXT: psraw $8, %xmm0
|
||||
; SSE-NEXT: punpckhbw {{.*#+}} xmm1 = xmm1[8],xmm0[8],xmm1[9],xmm0[9],xmm1[10],xmm0[10],xmm1[11],xmm0[11],xmm1[12],xmm0[12],xmm1[13],xmm0[13],xmm1[14],xmm0[14],xmm1[15],xmm0[15]
|
||||
; SSE-NEXT: psllw $8, %xmm1
|
||||
; SSE-NEXT: psraw $8, %xmm1
|
||||
; SSE-NEXT: retq
|
||||
%X = load <16 x i8>* %ptr
|
||||
%Y = sext <16 x i8> %X to <16 x i16>
|
||||
ret <16 x i16> %Y
|
||||
}
|
||||
|
||||
; AVX: sext_4i8_to_4i64
|
||||
; AVX: vpslld $24
|
||||
; AVX: vpsrad $24
|
||||
; AVX: vpmovsxdq
|
||||
; AVX: vpmovsxdq
|
||||
; AVX: ret
|
||||
define <4 x i64> @sext_4i8_to_4i64(<4 x i8> %mask) {
|
||||
; AVX1-LABEL: sext_4i8_to_4i64:
|
||||
; AVX1: ## BB#0:
|
||||
; AVX1-NEXT: vpslld $24, %xmm0, %xmm0
|
||||
; AVX1-NEXT: vpsrad $24, %xmm0, %xmm0
|
||||
; AVX1-NEXT: vpmovsxdq %xmm0, %xmm1
|
||||
; AVX1-NEXT: vmovhlps {{.*#+}} xmm0 = xmm0[1,1]
|
||||
; AVX1-NEXT: vpmovsxdq %xmm0, %xmm0
|
||||
; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0
|
||||
; AVX1-NEXT: retq
|
||||
;
|
||||
; AVX2-LABEL: sext_4i8_to_4i64:
|
||||
; AVX2: ## BB#0:
|
||||
; AVX2-NEXT: vpslld $24, %xmm0, %xmm0
|
||||
; AVX2-NEXT: vpsrad $24, %xmm0, %xmm0
|
||||
; AVX2-NEXT: vpmovsxdq %xmm0, %ymm0
|
||||
; AVX2-NEXT: retq
|
||||
;
|
||||
; SSE-LABEL: sext_4i8_to_4i64:
|
||||
; SSE: ## BB#0:
|
||||
; SSE-NEXT: pslld $24, %xmm0
|
||||
; SSE-NEXT: psrad $24, %xmm0
|
||||
; SSE-NEXT: pshufd {{.*#+}} xmm1 = xmm0[0,0,1,0]
|
||||
; SSE-NEXT: movd %xmm1, %rax
|
||||
; SSE-NEXT: cltq
|
||||
; SSE-NEXT: movd %rax, %xmm2
|
||||
; SSE-NEXT: punpckhqdq {{.*#+}} xmm1 = xmm1[1,1]
|
||||
; SSE-NEXT: movd %xmm1, %rax
|
||||
; SSE-NEXT: cltq
|
||||
; SSE-NEXT: movd %rax, %xmm1
|
||||
; SSE-NEXT: punpcklqdq {{.*#+}} xmm2 = xmm2[0],xmm1[0]
|
||||
; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[2,0,3,0]
|
||||
; SSE-NEXT: movd %xmm0, %rax
|
||||
; SSE-NEXT: cltq
|
||||
; SSE-NEXT: movd %rax, %xmm1
|
||||
; SSE-NEXT: punpckhqdq {{.*#+}} xmm0 = xmm0[1,1]
|
||||
; SSE-NEXT: movd %xmm0, %rax
|
||||
; SSE-NEXT: cltq
|
||||
; SSE-NEXT: movd %rax, %xmm0
|
||||
; SSE-NEXT: punpcklqdq {{.*#+}} xmm1 = xmm1[0],xmm0[0]
|
||||
; SSE-NEXT: movdqa %xmm2, %xmm0
|
||||
; SSE-NEXT: retq
|
||||
%extmask = sext <4 x i8> %mask to <4 x i64>
|
||||
ret <4 x i64> %extmask
|
||||
}
|
||||
|
||||
; AVX: sext_4i8_to_4i64
|
||||
; AVX: vpmovsxbd
|
||||
; AVX: vpmovsxdq
|
||||
; AVX: vpmovsxdq
|
||||
; AVX: ret
|
||||
define <4 x i64> @load_sext_4i8_to_4i64(<4 x i8> *%ptr) {
|
||||
; AVX1-LABEL: load_sext_4i8_to_4i64:
|
||||
; AVX1: ## BB#0:
|
||||
; AVX1-NEXT: vpmovsxbd (%rdi), %xmm0
|
||||
; AVX1-NEXT: vpmovsxdq %xmm0, %xmm1
|
||||
; AVX1-NEXT: vmovhlps {{.*#+}} xmm0 = xmm0[1,1]
|
||||
; AVX1-NEXT: vpmovsxdq %xmm0, %xmm0
|
||||
; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0
|
||||
; AVX1-NEXT: retq
|
||||
;
|
||||
; AVX2-LABEL: load_sext_4i8_to_4i64:
|
||||
; AVX2: ## BB#0:
|
||||
; AVX2-NEXT: vpmovsxbq (%rdi), %ymm0
|
||||
; AVX2-NEXT: retq
|
||||
;
|
||||
; SSSE3-LABEL: load_sext_4i8_to_4i64:
|
||||
; SSSE3: ## BB#0:
|
||||
; SSSE3-NEXT: movd (%rdi), %xmm1
|
||||
; SSSE3-NEXT: pshufb {{.*#+}} xmm1 = xmm1[0],zero,zero,zero,xmm1[1],zero,zero,zero,xmm1[2],zero,zero,zero,xmm1[3],zero,zero,zero
|
||||
; SSSE3-NEXT: pshufd {{.*#+}} xmm2 = xmm1[0,0,1,0]
|
||||
; SSSE3-NEXT: movd %xmm2, %rax
|
||||
; SSSE3-NEXT: movsbq %al, %rax
|
||||
; SSSE3-NEXT: movd %rax, %xmm0
|
||||
; SSSE3-NEXT: punpckhqdq {{.*#+}} xmm2 = xmm2[1,1]
|
||||
; SSSE3-NEXT: movd %xmm2, %rax
|
||||
; SSSE3-NEXT: movsbq %al, %rax
|
||||
; SSSE3-NEXT: movd %rax, %xmm2
|
||||
; SSSE3-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm2[0]
|
||||
; SSSE3-NEXT: pshufd {{.*#+}} xmm2 = xmm1[2,0,3,0]
|
||||
; SSSE3-NEXT: movd %xmm2, %rax
|
||||
; SSSE3-NEXT: movsbq %al, %rax
|
||||
; SSSE3-NEXT: movd %rax, %xmm1
|
||||
; SSSE3-NEXT: punpckhqdq {{.*#+}} xmm2 = xmm2[1,1]
|
||||
; SSSE3-NEXT: movd %xmm2, %rax
|
||||
; SSSE3-NEXT: movsbq %al, %rax
|
||||
; SSSE3-NEXT: movd %rax, %xmm2
|
||||
; SSSE3-NEXT: punpcklqdq {{.*#+}} xmm1 = xmm1[0],xmm2[0]
|
||||
; SSSE3-NEXT: retq
|
||||
;
|
||||
; SSE2-LABEL: load_sext_4i8_to_4i64:
|
||||
; SSE2: ## BB#0:
|
||||
; SSE2-NEXT: movl (%rdi), %eax
|
||||
; SSE2-NEXT: movd %eax, %xmm1
|
||||
; SSE2-NEXT: pextrw $1, %xmm1, %ecx
|
||||
; SSE2-NEXT: pinsrw $0, %eax, %xmm1
|
||||
; SSE2-NEXT: movzbl %ah, %eax
|
||||
; SSE2-NEXT: pinsrw $2, %eax, %xmm1
|
||||
; SSE2-NEXT: pinsrw $4, %ecx, %xmm1
|
||||
; SSE2-NEXT: shrl $8, %ecx
|
||||
; SSE2-NEXT: pinsrw $6, %ecx, %xmm1
|
||||
; SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm1[0,0,1,0]
|
||||
; SSE2-NEXT: movd %xmm2, %rax
|
||||
; SSE2-NEXT: movsbq %al, %rax
|
||||
; SSE2-NEXT: movd %rax, %xmm0
|
||||
; SSE2-NEXT: punpckhqdq {{.*#+}} xmm2 = xmm2[1,1]
|
||||
; SSE2-NEXT: movd %xmm2, %rax
|
||||
; SSE2-NEXT: movsbq %al, %rax
|
||||
; SSE2-NEXT: movd %rax, %xmm2
|
||||
; SSE2-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm2[0]
|
||||
; SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm1[2,0,3,0]
|
||||
; SSE2-NEXT: movd %xmm2, %rax
|
||||
; SSE2-NEXT: movsbq %al, %rax
|
||||
; SSE2-NEXT: movd %rax, %xmm1
|
||||
; SSE2-NEXT: punpckhqdq {{.*#+}} xmm2 = xmm2[1,1]
|
||||
; SSE2-NEXT: movd %xmm2, %rax
|
||||
; SSE2-NEXT: movsbq %al, %rax
|
||||
; SSE2-NEXT: movd %rax, %xmm2
|
||||
; SSE2-NEXT: punpcklqdq {{.*#+}} xmm1 = xmm1[0],xmm2[0]
|
||||
; SSE2-NEXT: retq
|
||||
%X = load <4 x i8>* %ptr
|
||||
%Y = sext <4 x i8> %X to <4 x i64>
|
||||
ret <4 x i64>%Y
|
||||
}
|
||||
|
||||
; AVX: sext_4i16_to_4i64
|
||||
; AVX: vpmovsxwd
|
||||
; AVX: vpmovsxdq
|
||||
; AVX: vpmovsxdq
|
||||
; AVX: ret
|
||||
define <4 x i64> @load_sext_4i16_to_4i64(<4 x i16> *%ptr) {
|
||||
; AVX1-LABEL: load_sext_4i16_to_4i64:
|
||||
; AVX1: ## BB#0:
|
||||
; AVX1-NEXT: vpmovsxwd (%rdi), %xmm0
|
||||
; AVX1-NEXT: vpmovsxdq %xmm0, %xmm1
|
||||
; AVX1-NEXT: vmovhlps {{.*#+}} xmm0 = xmm0[1,1]
|
||||
; AVX1-NEXT: vpmovsxdq %xmm0, %xmm0
|
||||
; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0
|
||||
; AVX1-NEXT: retq
|
||||
;
|
||||
; AVX2-LABEL: load_sext_4i16_to_4i64:
|
||||
; AVX2: ## BB#0:
|
||||
; AVX2-NEXT: vpmovsxwq (%rdi), %ymm0
|
||||
; AVX2-NEXT: retq
|
||||
;
|
||||
; SSE-LABEL: load_sext_4i16_to_4i64:
|
||||
; SSE: ## BB#0:
|
||||
; SSE-NEXT: movq (%rdi), %xmm1
|
||||
; SSE-NEXT: punpcklwd {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3]
|
||||
; SSE-NEXT: pshufd {{.*#+}} xmm2 = xmm1[0,0,1,0]
|
||||
; SSE-NEXT: movd %xmm2, %rax
|
||||
; SSE-NEXT: movswq %ax, %rax
|
||||
; SSE-NEXT: movd %rax, %xmm0
|
||||
; SSE-NEXT: punpckhqdq {{.*#+}} xmm2 = xmm2[1,1]
|
||||
; SSE-NEXT: movd %xmm2, %rax
|
||||
; SSE-NEXT: movswq %ax, %rax
|
||||
; SSE-NEXT: movd %rax, %xmm2
|
||||
; SSE-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm2[0]
|
||||
; SSE-NEXT: pshufd {{.*#+}} xmm2 = xmm1[2,0,3,0]
|
||||
; SSE-NEXT: movd %xmm2, %rax
|
||||
; SSE-NEXT: movswq %ax, %rax
|
||||
; SSE-NEXT: movd %rax, %xmm1
|
||||
; SSE-NEXT: punpckhqdq {{.*#+}} xmm2 = xmm2[1,1]
|
||||
; SSE-NEXT: movd %xmm2, %rax
|
||||
; SSE-NEXT: movswq %ax, %rax
|
||||
; SSE-NEXT: movd %rax, %xmm2
|
||||
; SSE-NEXT: punpcklqdq {{.*#+}} xmm1 = xmm1[0],xmm2[0]
|
||||
; SSE-NEXT: retq
|
||||
%X = load <4 x i16>* %ptr
|
||||
%Y = sext <4 x i16> %X to <4 x i64>
|
||||
ret <4 x i64>%Y
|
||||
|
|
|
|||
Loading…
Reference in New Issue