forked from OSchip/llvm-project
parent
1067ab0a1a
commit
1f32c313f1
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@ -7371,7 +7371,11 @@ X86TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const {
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if (V1IsUndef && V2IsUndef)
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return DAG.getUNDEF(VT);
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assert(!V1IsUndef && "Op 1 of shuffle should not be undef");
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// When we create a shuffle node we put the UNDEF node to second operand,
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// but in some cases the first operand may be transformed to UNDEF.
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// In this case we should just commute the node.
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if (V1IsUndef)
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return CommuteVectorShuffle(SVOp, DAG);
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// Vector shuffle lowering takes 3 steps:
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//
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@ -297,3 +297,12 @@ entry:
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}
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declare <2 x double> @llvm.x86.avx.vextractf128.pd.256(<4 x double>, i8) nounwind readnone
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declare <4 x double> @llvm.x86.avx.vinsertf128.pd.256(<4 x double>, <2 x double>, i8) nounwind readnone
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; this test case just should not fail
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define void @test20() {
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%a0 = insertelement <3 x double> <double 0.000000e+00, double 0.000000e+00, double undef>, double 0.000000e+00, i32 2
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store <3 x double> %a0, <3 x double>* undef, align 1
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%a1 = insertelement <3 x double> <double 0.000000e+00, double 0.000000e+00, double undef>, double undef, i32 2
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store <3 x double> %a1, <3 x double>* undef, align 1
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ret void
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}
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