From 1f070c334c7cc35e0a4ed6ed9816af3f34f81ea3 Mon Sep 17 00:00:00 2001
From: Simon Pilgrim <llvm-dev@redking.me.uk>
Date: Thu, 12 Apr 2018 22:57:34 +0000
Subject: [PATCH] [X86] Remove unused MoveLoadStoreItins/ShiftOpndItins
 schedule class wrappers.

Was being used to move around empty/unused itineraries...

llvm-svn: 329970
---
 llvm/lib/Target/X86/X86InstrAVX512.td | 28 +++++++++++++--------------
 llvm/lib/Target/X86/X86InstrSSE.td    | 22 ---------------------
 2 files changed, 14 insertions(+), 36 deletions(-)

diff --git a/llvm/lib/Target/X86/X86InstrAVX512.td b/llvm/lib/Target/X86/X86InstrAVX512.td
index 107289ada2ea..e97782b937bf 100644
--- a/llvm/lib/Target/X86/X86InstrAVX512.td
+++ b/llvm/lib/Target/X86/X86InstrAVX512.td
@@ -3170,7 +3170,7 @@ defm : operation_subvector_mask_lowering<VK32, v32i1, VK64, v64i1>;
 //
 
 
-multiclass avx512_load<bits<8> opc, string OpcodeStr, MoveLoadStoreItins itins,
+multiclass avx512_load<bits<8> opc, string OpcodeStr,
                        X86VectorVTInfo _, PatFrag ld_frag, PatFrag mload,
                        SchedWrite SchedRR, SchedWrite SchedRM,
                        bit NoRMPattern = 0,
@@ -3239,15 +3239,15 @@ multiclass avx512_alignedload_vl<bits<8> opc, string OpcodeStr,
                                   Predicate prd, SchedWrite SchedRR,
                                   SchedWrite SchedRM, bit NoRMPattern = 0> {
   let Predicates = [prd] in
-  defm Z : avx512_load<opc, OpcodeStr, SSE_MOVA, _.info512,
+  defm Z : avx512_load<opc, OpcodeStr, _.info512,
                        _.info512.AlignedLdFrag, masked_load_aligned512,
                        SchedRR, SchedRM, NoRMPattern>, EVEX_V512;
 
   let Predicates = [prd, HasVLX] in {
-  defm Z256 : avx512_load<opc, OpcodeStr, SSE_MOVA, _.info256,
+  defm Z256 : avx512_load<opc, OpcodeStr, _.info256,
                           _.info256.AlignedLdFrag, masked_load_aligned256,
                           SchedRR, SchedRM, NoRMPattern>, EVEX_V256;
-  defm Z128 : avx512_load<opc, OpcodeStr, SSE_MOVA, _.info128,
+  defm Z128 : avx512_load<opc, OpcodeStr, _.info128,
                           _.info128.AlignedLdFrag, masked_load_aligned128,
                           SchedRR, SchedRM, NoRMPattern>, EVEX_V128;
   }
@@ -3259,21 +3259,21 @@ multiclass avx512_load_vl<bits<8> opc, string OpcodeStr,
                                   SchedWrite SchedRM, bit NoRMPattern = 0,
                                   SDPatternOperator SelectOprr = vselect> {
   let Predicates = [prd] in
-  defm Z : avx512_load<opc, OpcodeStr, SSE_MOVU, _.info512, _.info512.LdFrag,
+  defm Z : avx512_load<opc, OpcodeStr, _.info512, _.info512.LdFrag,
                        masked_load_unaligned, SchedRR, SchedRM, NoRMPattern,
                        SelectOprr>, EVEX_V512;
 
   let Predicates = [prd, HasVLX] in {
-  defm Z256 : avx512_load<opc, OpcodeStr, SSE_MOVU, _.info256, _.info256.LdFrag,
+  defm Z256 : avx512_load<opc, OpcodeStr, _.info256, _.info256.LdFrag,
                          masked_load_unaligned, SchedRR, SchedRM, NoRMPattern,
                          SelectOprr>, EVEX_V256;
-  defm Z128 : avx512_load<opc, OpcodeStr, SSE_MOVU, _.info128, _.info128.LdFrag,
+  defm Z128 : avx512_load<opc, OpcodeStr, _.info128, _.info128.LdFrag,
                          masked_load_unaligned, SchedRR, SchedRM, NoRMPattern,
                          SelectOprr>, EVEX_V128;
   }
 }
 
-multiclass avx512_store<bits<8> opc, string OpcodeStr, MoveLoadStoreItins itins,
+multiclass avx512_store<bits<8> opc, string OpcodeStr,
                         X86VectorVTInfo _, PatFrag st_frag, PatFrag mstore,
                         string Name, SchedWrite SchedRR, SchedWrite SchedMR,
                         bit NoMRPattern = 0> {
@@ -3318,14 +3318,14 @@ multiclass avx512_store_vl< bits<8> opc, string OpcodeStr,
                             string Name, SchedWrite SchedRR, SchedWrite SchedMR,
                             bit NoMRPattern = 0> {
   let Predicates = [prd] in
-  defm Z : avx512_store<opc, OpcodeStr, SSE_MOVU, _.info512, store,
+  defm Z : avx512_store<opc, OpcodeStr, _.info512, store,
                         masked_store_unaligned, Name#Z, SchedRR, SchedMR,
                         NoMRPattern>, EVEX_V512;
   let Predicates = [prd, HasVLX] in {
-    defm Z256 : avx512_store<opc, OpcodeStr, SSE_MOVU, _.info256, store,
+    defm Z256 : avx512_store<opc, OpcodeStr, _.info256, store,
                              masked_store_unaligned, Name#Z256, SchedRR,
                              SchedMR, NoMRPattern>, EVEX_V256;
-    defm Z128 : avx512_store<opc, OpcodeStr, SSE_MOVU, _.info128, store,
+    defm Z128 : avx512_store<opc, OpcodeStr, _.info128, store,
                              masked_store_unaligned, Name#Z128, SchedRR,
                              SchedMR, NoMRPattern>, EVEX_V128;
   }
@@ -3336,15 +3336,15 @@ multiclass avx512_alignedstore_vl<bits<8> opc, string OpcodeStr,
                                   string Name, SchedWrite SchedRR,
                                   SchedWrite SchedMR, bit NoMRPattern = 0> {
   let Predicates = [prd] in
-  defm Z : avx512_store<opc, OpcodeStr, SSE_MOVA, _.info512, alignedstore,
+  defm Z : avx512_store<opc, OpcodeStr, _.info512, alignedstore,
                         masked_store_aligned512, Name#Z, SchedRR, SchedMR,
                         NoMRPattern>, EVEX_V512;
 
   let Predicates = [prd, HasVLX] in {
-    defm Z256 : avx512_store<opc, OpcodeStr, SSE_MOVA, _.info256, alignedstore,
+    defm Z256 : avx512_store<opc, OpcodeStr, _.info256, alignedstore,
                              masked_store_aligned256, Name#Z256, SchedRR,
                              SchedMR, NoMRPattern>, EVEX_V256;
-    defm Z128 : avx512_store<opc, OpcodeStr, SSE_MOVA, _.info128, alignedstore,
+    defm Z128 : avx512_store<opc, OpcodeStr, _.info128, alignedstore,
                              masked_store_aligned128, Name#Z128, SchedRR,
                              SchedMR, NoMRPattern>, EVEX_V128;
   }
diff --git a/llvm/lib/Target/X86/X86InstrSSE.td b/llvm/lib/Target/X86/X86InstrSSE.td
index 15e8fc90670a..c1a92cf30efe 100644
--- a/llvm/lib/Target/X86/X86InstrSSE.td
+++ b/llvm/lib/Target/X86/X86InstrSSE.td
@@ -25,20 +25,6 @@ class SizeItins<OpndItins arg_s, OpndItins arg_d> {
   OpndItins d = arg_d;
 }
 
-class MoveLoadStoreItins<InstrItinClass arg_rr, InstrItinClass arg_rm,
-                         InstrItinClass arg_mr> {
-  InstrItinClass rr = arg_rr;
-  InstrItinClass rm = arg_rm;
-  InstrItinClass mr = arg_mr;
-}
-
-class ShiftOpndItins<InstrItinClass arg_rr, InstrItinClass arg_rm,
-                     InstrItinClass arg_ri> {
-  InstrItinClass rr = arg_rr;
-  InstrItinClass rm = arg_rm;
-  InstrItinClass ri = arg_ri;
-}
-
 // scalar
 let Sched = WriteFAdd in {
 def SSE_ALU_F32S : OpndItins<
@@ -154,18 +140,10 @@ def SSE_MOVA_ITINS : OpndItins<
   NoItinerary, NoItinerary
 >;
 
-def SSE_MOVA : MoveLoadStoreItins<
-  NoItinerary, NoItinerary, NoItinerary
->;
-
 def SSE_MOVU_ITINS : OpndItins<
   NoItinerary, NoItinerary
 >;
 
-def SSE_MOVU : MoveLoadStoreItins<
-  NoItinerary, NoItinerary, NoItinerary
->;
-
 def SSE_DPPD_ITINS : OpndItins<
   NoItinerary, NoItinerary
 >;