forked from OSchip/llvm-project
[X86] FixupLEAs, reduce number of calls to getOperand and use X86::AddrBaseReg/AddrIndexReg, etc. instead of hardcoded constants.
Makes the code a little more readable. llvm-svn: 349983
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7f41fe3a58
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1f02ac3451
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@ -333,13 +333,12 @@ static inline int getADDriFromLEA(int LEAOpcode, const MachineOperand &Offset) {
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static inline bool isLEASimpleIncOrDec(MachineInstr &LEA) {
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static inline bool isLEASimpleIncOrDec(MachineInstr &LEA) {
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unsigned SrcReg = LEA.getOperand(1 + X86::AddrBaseReg).getReg();
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unsigned SrcReg = LEA.getOperand(1 + X86::AddrBaseReg).getReg();
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unsigned DstReg = LEA.getOperand(0).getReg();
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unsigned DstReg = LEA.getOperand(0).getReg();
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unsigned AddrDispOp = 1 + X86::AddrDisp;
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const MachineOperand &AddrDisp = LEA.getOperand(1 + X86::AddrDisp);
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return SrcReg == DstReg &&
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return SrcReg == DstReg &&
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LEA.getOperand(1 + X86::AddrIndexReg).getReg() == 0 &&
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LEA.getOperand(1 + X86::AddrIndexReg).getReg() == 0 &&
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LEA.getOperand(1 + X86::AddrSegmentReg).getReg() == 0 &&
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LEA.getOperand(1 + X86::AddrSegmentReg).getReg() == 0 &&
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LEA.getOperand(AddrDispOp).isImm() &&
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AddrDisp.isImm() &&
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(LEA.getOperand(AddrDispOp).getImm() == 1 ||
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(AddrDisp.getImm() == 1 || AddrDisp.getImm() == -1);
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LEA.getOperand(AddrDispOp).getImm() == -1);
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}
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}
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bool FixupLEAPass::fixupIncDec(MachineBasicBlock::iterator &I,
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bool FixupLEAPass::fixupIncDec(MachineBasicBlock::iterator &I,
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@ -351,7 +350,7 @@ bool FixupLEAPass::fixupIncDec(MachineBasicBlock::iterator &I,
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if (isLEASimpleIncOrDec(MI) && TII->isSafeToClobberEFLAGS(*MFI, I)) {
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if (isLEASimpleIncOrDec(MI) && TII->isSafeToClobberEFLAGS(*MFI, I)) {
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int NewOpcode;
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int NewOpcode;
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bool isINC = MI.getOperand(4).getImm() == 1;
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bool isINC = MI.getOperand(1 + X86::AddrDisp).getImm() == 1;
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switch (Opcode) {
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switch (Opcode) {
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case X86::LEA16r:
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case X86::LEA16r:
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NewOpcode = isINC ? X86::INC16r : X86::DEC16r;
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NewOpcode = isINC ? X86::INC16r : X86::DEC16r;
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@ -368,7 +367,7 @@ bool FixupLEAPass::fixupIncDec(MachineBasicBlock::iterator &I,
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MachineInstr *NewMI =
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MachineInstr *NewMI =
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BuildMI(*MFI, I, MI.getDebugLoc(), TII->get(NewOpcode))
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BuildMI(*MFI, I, MI.getDebugLoc(), TII->get(NewOpcode))
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.add(MI.getOperand(0))
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.add(MI.getOperand(0))
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.add(MI.getOperand(1));
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.add(MI.getOperand(1 + X86::AddrBaseReg));
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MFI->erase(I);
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MFI->erase(I);
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I = static_cast<MachineBasicBlock::iterator>(NewMI);
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I = static_cast<MachineBasicBlock::iterator>(NewMI);
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return true;
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return true;
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@ -420,15 +419,23 @@ void FixupLEAPass::processInstructionForSlowLEA(MachineBasicBlock::iterator &I,
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const int Opcode = MI.getOpcode();
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const int Opcode = MI.getOpcode();
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if (!isLEA(Opcode))
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if (!isLEA(Opcode))
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return;
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return;
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if (MI.getOperand(5).getReg() != 0 || !MI.getOperand(4).isImm() ||
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const MachineOperand &Dst = MI.getOperand(0);
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const MachineOperand &Base = MI.getOperand(1 + X86::AddrBaseReg);
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const MachineOperand &Scale = MI.getOperand(1 + X86::AddrScaleAmt);
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const MachineOperand &Index = MI.getOperand(1 + X86::AddrIndexReg);
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const MachineOperand &Offset = MI.getOperand(1 + X86::AddrDisp);
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const MachineOperand &Segment = MI.getOperand(1 + X86::AddrSegmentReg);
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if (Segment.getReg() != 0 || !Offset.isImm() ||
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!TII->isSafeToClobberEFLAGS(*MFI, I))
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!TII->isSafeToClobberEFLAGS(*MFI, I))
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return;
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return;
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const unsigned DstR = MI.getOperand(0).getReg();
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const unsigned DstR = Dst.getReg();
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const unsigned SrcR1 = MI.getOperand(1).getReg();
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const unsigned SrcR1 = Base.getReg();
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const unsigned SrcR2 = MI.getOperand(3).getReg();
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const unsigned SrcR2 = Index.getReg();
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if ((SrcR1 == 0 || SrcR1 != DstR) && (SrcR2 == 0 || SrcR2 != DstR))
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if ((SrcR1 == 0 || SrcR1 != DstR) && (SrcR2 == 0 || SrcR2 != DstR))
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return;
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return;
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if (MI.getOperand(2).getImm() > 1)
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if (Scale.getImm() > 1)
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return;
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return;
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LLVM_DEBUG(dbgs() << "FixLEA: Candidate to replace:"; I->dump(););
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LLVM_DEBUG(dbgs() << "FixLEA: Candidate to replace:"; I->dump(););
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LLVM_DEBUG(dbgs() << "FixLEA: Replaced by: ";);
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LLVM_DEBUG(dbgs() << "FixLEA: Replaced by: ";);
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@ -436,19 +443,19 @@ void FixupLEAPass::processInstructionForSlowLEA(MachineBasicBlock::iterator &I,
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// Make ADD instruction for two registers writing to LEA's destination
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// Make ADD instruction for two registers writing to LEA's destination
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if (SrcR1 != 0 && SrcR2 != 0) {
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if (SrcR1 != 0 && SrcR2 != 0) {
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const MCInstrDesc &ADDrr = TII->get(getADDrrFromLEA(Opcode));
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const MCInstrDesc &ADDrr = TII->get(getADDrrFromLEA(Opcode));
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const MachineOperand &Src = MI.getOperand(SrcR1 == DstR ? 3 : 1);
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const MachineOperand &Src = SrcR1 == DstR ? Index : Base;
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NewMI =
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NewMI =
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BuildMI(*MFI, I, MI.getDebugLoc(), ADDrr, DstR).addReg(DstR).add(Src);
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BuildMI(*MFI, I, MI.getDebugLoc(), ADDrr, DstR).addReg(DstR).add(Src);
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LLVM_DEBUG(NewMI->dump(););
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LLVM_DEBUG(NewMI->dump(););
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}
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}
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// Make ADD instruction for immediate
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// Make ADD instruction for immediate
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if (MI.getOperand(4).getImm() != 0) {
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if (Offset.getImm() != 0) {
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const MCInstrDesc &ADDri =
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const MCInstrDesc &ADDri =
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TII->get(getADDriFromLEA(Opcode, MI.getOperand(4)));
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TII->get(getADDriFromLEA(Opcode, Offset));
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const MachineOperand &SrcR = MI.getOperand(SrcR1 == DstR ? 1 : 3);
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const MachineOperand &SrcR = SrcR1 == DstR ? Base : Index;
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NewMI = BuildMI(*MFI, I, MI.getDebugLoc(), ADDri, DstR)
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NewMI = BuildMI(*MFI, I, MI.getDebugLoc(), ADDri, DstR)
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.add(SrcR)
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.add(SrcR)
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.addImm(MI.getOperand(4).getImm());
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.addImm(Offset.getImm());
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LLVM_DEBUG(NewMI->dump(););
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LLVM_DEBUG(NewMI->dump(););
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}
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}
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if (NewMI) {
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if (NewMI) {
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@ -465,12 +472,12 @@ FixupLEAPass::processInstrForSlow3OpLEA(MachineInstr &MI,
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if (!isLEA(LEAOpcode))
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if (!isLEA(LEAOpcode))
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return nullptr;
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return nullptr;
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const MachineOperand &Dst = MI.getOperand(0);
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const MachineOperand &Dst = MI.getOperand(0);
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const MachineOperand &Base = MI.getOperand(1);
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const MachineOperand &Base = MI.getOperand(1 + X86::AddrBaseReg);
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const MachineOperand &Scale = MI.getOperand(2);
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const MachineOperand &Scale = MI.getOperand(1 + X86::AddrScaleAmt);
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const MachineOperand &Index = MI.getOperand(3);
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const MachineOperand &Index = MI.getOperand(1 + X86::AddrIndexReg);
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const MachineOperand &Offset = MI.getOperand(4);
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const MachineOperand &Offset = MI.getOperand(1 + X86::AddrDisp);
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const MachineOperand &Segment = MI.getOperand(5);
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const MachineOperand &Segment = MI.getOperand(1 + X86::AddrSegmentReg);
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if (!(TII->isThreeOperandsLEA(MI) ||
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if (!(TII->isThreeOperandsLEA(MI) ||
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hasInefficientLEABaseReg(Base, Index)) ||
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hasInefficientLEABaseReg(Base, Index)) ||
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