forked from OSchip/llvm-project
[Hexagon] Add support for "new" circular buffer intrinsics
These instructions have been around for a long time, but we haven't supported intrinsics for them. The "new" vesrions use the CSx register for the start of the buffer instead of the K field in the Mx register. There is a related llvm patch. Patch by Brendon Cahoon. llvm-svn: 328725
This commit is contained in:
Krzysztof Parzyszek
parent
440ba3ae5c
commit
1ef2a1f414
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@ -39,6 +39,29 @@ BUILTIN(__builtin_circ_stw, "i*i*iiIi", "")
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BUILTIN(__builtin_circ_sth, "s*s*iiIi", "")
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BUILTIN(__builtin_circ_sthhi, "s*s*iiIi", "")
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BUILTIN(__builtin_circ_stb, "c*c*iiIi", "")
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BUILTIN(__builtin_HEXAGON_L2_loadrub_pci, "iv*IiivC*", "")
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BUILTIN(__builtin_HEXAGON_L2_loadrb_pci, "iv*IiivC*", "")
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BUILTIN(__builtin_HEXAGON_L2_loadruh_pci, "iv*IiivC*", "")
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BUILTIN(__builtin_HEXAGON_L2_loadrh_pci, "iv*IiivC*", "")
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BUILTIN(__builtin_HEXAGON_L2_loadri_pci, "iv*IiivC*", "")
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BUILTIN(__builtin_HEXAGON_L2_loadrd_pci, "LLiv*IiivC*", "")
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BUILTIN(__builtin_HEXAGON_L2_loadrub_pcr, "iv*ivC*", "")
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BUILTIN(__builtin_HEXAGON_L2_loadrb_pcr, "iv*ivC*", "")
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BUILTIN(__builtin_HEXAGON_L2_loadruh_pcr, "iv*ivC*", "")
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BUILTIN(__builtin_HEXAGON_L2_loadrh_pcr, "iv*ivC*", "")
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BUILTIN(__builtin_HEXAGON_L2_loadri_pcr, "iv*ivC*", "")
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BUILTIN(__builtin_HEXAGON_L2_loadrd_pcr, "LLiv*ivC*", "")
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BUILTIN(__builtin_HEXAGON_S2_storerb_pci, "vv*IiiivC*", "")
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BUILTIN(__builtin_HEXAGON_S2_storerh_pci, "vv*IiiivC*", "")
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BUILTIN(__builtin_HEXAGON_S2_storerf_pci, "vv*IiiivC*", "")
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BUILTIN(__builtin_HEXAGON_S2_storeri_pci, "vv*IiiivC*", "")
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BUILTIN(__builtin_HEXAGON_S2_storerd_pci, "vv*IiiLLivC*", "")
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BUILTIN(__builtin_HEXAGON_S2_storerb_pcr, "vv*iivC*", "")
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BUILTIN(__builtin_HEXAGON_S2_storerh_pcr, "vv*iivC*", "")
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BUILTIN(__builtin_HEXAGON_S2_storerf_pcr, "vv*iivC*", "")
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BUILTIN(__builtin_HEXAGON_S2_storeri_pcr, "vv*iivC*", "")
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BUILTIN(__builtin_HEXAGON_S2_storerd_pcr, "vv*iLLivC*", "")
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// The builtins above are not autogenerated from iset.py.
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// Make sure you do not overwrite these.
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@ -10772,6 +10772,54 @@ Value *CodeGenFunction::EmitHexagonBuiltinExpr(unsigned BuiltinID,
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SmallVector<llvm::Value *, 4> Ops;
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Intrinsic::ID ID = Intrinsic::not_intrinsic;
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auto MakeCircLd = [&](unsigned IntID, bool HasImm = true) {
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// The base pointer is passed by address, so it needs to be loaded.
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Address BP = EmitPointerWithAlignment(E->getArg(0));
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BP = Address(Builder.CreateBitCast(BP.getPointer(), Int8PtrPtrTy),
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BP.getAlignment());
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llvm::Value *Base = Builder.CreateLoad(BP);
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// Operands are Base, Increment, Modifier, Start.
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if (HasImm)
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Ops = { Base, EmitScalarExpr(E->getArg(1)), EmitScalarExpr(E->getArg(2)),
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EmitScalarExpr(E->getArg(3)) };
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else
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Ops = { Base, EmitScalarExpr(E->getArg(1)),
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EmitScalarExpr(E->getArg(2)) };
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llvm::Value *Result = Builder.CreateCall(CGM.getIntrinsic(IntID), Ops);
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llvm::Value *NewBase = Builder.CreateExtractValue(Result, 1);
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llvm::Value *LV = Builder.CreateBitCast(EmitScalarExpr(E->getArg(0)),
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NewBase->getType()->getPointerTo());
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Address Dest = EmitPointerWithAlignment(E->getArg(0));
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// The intrinsic generates two results. The new value for the base pointer
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// needs to be stored.
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Builder.CreateAlignedStore(NewBase, LV, Dest.getAlignment());
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return Builder.CreateExtractValue(Result, 0);
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};
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auto MakeCircSt = [&](unsigned IntID, bool HasImm = true) {
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// The base pointer is passed by address, so it needs to be loaded.
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Address BP = EmitPointerWithAlignment(E->getArg(0));
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BP = Address(Builder.CreateBitCast(BP.getPointer(), Int8PtrPtrTy),
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BP.getAlignment());
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llvm::Value *Base = Builder.CreateLoad(BP);
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// Operands are Base, Increment, Modifier, Value, Start.
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if (HasImm)
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Ops = { Base, EmitScalarExpr(E->getArg(1)), EmitScalarExpr(E->getArg(2)),
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EmitScalarExpr(E->getArg(3)), EmitScalarExpr(E->getArg(4)) };
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else
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Ops = { Base, EmitScalarExpr(E->getArg(1)),
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EmitScalarExpr(E->getArg(2)), EmitScalarExpr(E->getArg(3)) };
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llvm::Value *NewBase = Builder.CreateCall(CGM.getIntrinsic(IntID), Ops);
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llvm::Value *LV = Builder.CreateBitCast(EmitScalarExpr(E->getArg(0)),
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NewBase->getType()->getPointerTo());
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Address Dest = EmitPointerWithAlignment(E->getArg(0));
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// The intrinsic generates one result, which is the new value for the base
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// pointer. It needs to be stored.
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return Builder.CreateAlignedStore(NewBase, LV, Dest.getAlignment());
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};
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switch (BuiltinID) {
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case Hexagon::BI__builtin_HEXAGON_V6_vaddcarry:
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case Hexagon::BI__builtin_HEXAGON_V6_vaddcarry_128B: {
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@ -10817,6 +10865,52 @@ Value *CodeGenFunction::EmitHexagonBuiltinExpr(unsigned BuiltinID,
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Builder.CreateAlignedStore(Vprd, Base, Dest.getAlignment());
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return Builder.CreateExtractValue(Result, 0);
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}
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case Hexagon::BI__builtin_HEXAGON_L2_loadrub_pci:
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return MakeCircLd(Intrinsic::hexagon_L2_loadrub_pci);
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case Hexagon::BI__builtin_HEXAGON_L2_loadrb_pci:
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return MakeCircLd(Intrinsic::hexagon_L2_loadrb_pci);
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case Hexagon::BI__builtin_HEXAGON_L2_loadruh_pci:
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return MakeCircLd(Intrinsic::hexagon_L2_loadruh_pci);
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case Hexagon::BI__builtin_HEXAGON_L2_loadrh_pci:
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return MakeCircLd(Intrinsic::hexagon_L2_loadrh_pci);
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case Hexagon::BI__builtin_HEXAGON_L2_loadri_pci:
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return MakeCircLd(Intrinsic::hexagon_L2_loadri_pci);
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case Hexagon::BI__builtin_HEXAGON_L2_loadrd_pci:
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return MakeCircLd(Intrinsic::hexagon_L2_loadrd_pci);
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case Hexagon::BI__builtin_HEXAGON_L2_loadrub_pcr:
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return MakeCircLd(Intrinsic::hexagon_L2_loadrub_pcr, /*HasImm=*/false);
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case Hexagon::BI__builtin_HEXAGON_L2_loadrb_pcr:
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return MakeCircLd(Intrinsic::hexagon_L2_loadrb_pcr, /*HasImm=*/false);
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case Hexagon::BI__builtin_HEXAGON_L2_loadruh_pcr:
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return MakeCircLd(Intrinsic::hexagon_L2_loadruh_pcr, /*HasImm=*/false);
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case Hexagon::BI__builtin_HEXAGON_L2_loadrh_pcr:
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return MakeCircLd(Intrinsic::hexagon_L2_loadrh_pcr, /*HasImm=*/false);
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case Hexagon::BI__builtin_HEXAGON_L2_loadri_pcr:
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return MakeCircLd(Intrinsic::hexagon_L2_loadri_pcr, /*HasImm=*/false);
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case Hexagon::BI__builtin_HEXAGON_L2_loadrd_pcr:
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return MakeCircLd(Intrinsic::hexagon_L2_loadrd_pcr, /*HasImm=*/false);
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case Hexagon::BI__builtin_HEXAGON_S2_storerb_pci:
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return MakeCircSt(Intrinsic::hexagon_S2_storerb_pci);
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case Hexagon::BI__builtin_HEXAGON_S2_storerh_pci:
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return MakeCircSt(Intrinsic::hexagon_S2_storerh_pci);
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case Hexagon::BI__builtin_HEXAGON_S2_storerf_pci:
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return MakeCircSt(Intrinsic::hexagon_S2_storerf_pci);
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case Hexagon::BI__builtin_HEXAGON_S2_storeri_pci:
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return MakeCircSt(Intrinsic::hexagon_S2_storeri_pci);
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case Hexagon::BI__builtin_HEXAGON_S2_storerd_pci:
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return MakeCircSt(Intrinsic::hexagon_S2_storerd_pci);
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case Hexagon::BI__builtin_HEXAGON_S2_storerb_pcr:
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return MakeCircSt(Intrinsic::hexagon_S2_storerb_pcr, /*HasImm=*/false);
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case Hexagon::BI__builtin_HEXAGON_S2_storerh_pcr:
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return MakeCircSt(Intrinsic::hexagon_S2_storerh_pcr, /*HasImm=*/false);
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case Hexagon::BI__builtin_HEXAGON_S2_storerf_pcr:
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return MakeCircSt(Intrinsic::hexagon_S2_storerf_pcr, /*HasImm=*/false);
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case Hexagon::BI__builtin_HEXAGON_S2_storeri_pcr:
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return MakeCircSt(Intrinsic::hexagon_S2_storeri_pcr, /*HasImm=*/false);
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case Hexagon::BI__builtin_HEXAGON_S2_storerd_pcr:
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return MakeCircSt(Intrinsic::hexagon_S2_storerd_pcr, /*HasImm=*/false);
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default:
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break;
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} // switch
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return nullptr;
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@ -0,0 +1,156 @@
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// REQUIRES: hexagon-registered-target
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// RUN: %clang_cc1 -triple hexagon-unknown-elf -emit-llvm %s -o - | FileCheck %s
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// CHECK-LABEL: test1
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// CHECK: @llvm.hexagon.L2.loadrub.pci
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unsigned char test1(int mod, void *start) {
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unsigned char *base = start;
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return __builtin_HEXAGON_L2_loadrub_pci(&base, 4, mod, start);
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}
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// CHECK-LABEL: test2
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// CHECK: @llvm.hexagon.L2.loadrb.pci
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unsigned char test2(int mod, void *start) {
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char *base = start;
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return __builtin_HEXAGON_L2_loadrb_pci(&base, 4, mod, start);
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}
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// CHECK-LABEL: test3
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// CHECK: @llvm.hexagon.L2.loadruh.pci
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unsigned short test3(int mod, void *start) {
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unsigned short *base = start;
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return __builtin_HEXAGON_L2_loadruh_pci(&base, 4, mod, start);
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}
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// CHECK-LABEL: test4
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// CHECK: @llvm.hexagon.L2.loadrh.pci
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short test4(int mod, void *start) {
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short *base = start;
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return __builtin_HEXAGON_L2_loadrh_pci(&base, 4, mod, start);
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}
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// CHECK-LABEL: test5
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// CHECK: @llvm.hexagon.L2.loadri.pci
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int test5(int mod, void *start) {
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int *base = start;
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return __builtin_HEXAGON_L2_loadri_pci(&base, 4, mod, start);
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}
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// CHECK-LABEL: test6
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// CHECK: @llvm.hexagon.L2.loadrd.pci
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long long test6(int mod, void *start) {
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long long *base = start;
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return __builtin_HEXAGON_L2_loadrd_pci(&base, 8, mod, start);
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}
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// CHECK-LABEL: test7
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// CHECK: @llvm.hexagon.L2.loadrub.pcr
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unsigned char test7(int mod, void *start) {
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unsigned char *base = start;
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return __builtin_HEXAGON_L2_loadrub_pcr(&base, mod, start);
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}
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// CHECK-LABEL: test8
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// CHECK: @llvm.hexagon.L2.loadrb.pcr
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unsigned char test8(int mod, void *start) {
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char *base = start;
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return __builtin_HEXAGON_L2_loadrb_pcr(&base, mod, start);
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}
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// CHECK-LABEL: test9
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// CHECK: @llvm.hexagon.L2.loadruh.pcr
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unsigned short test9(int mod, void *start) {
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unsigned short *base = start;
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return __builtin_HEXAGON_L2_loadruh_pcr(&base, mod, start);
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}
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// CHECK-LABEL: test10
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// CHECK: @llvm.hexagon.L2.loadrh.pcr
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short test10(int mod, void *start) {
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short *base = start;
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return __builtin_HEXAGON_L2_loadrh_pcr(&base, mod, start);
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}
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// CHECK-LABEL: test11
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// CHECK: @llvm.hexagon.L2.loadri.pcr
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int test11(int mod, void *start) {
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int *base = start;
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return __builtin_HEXAGON_L2_loadri_pcr(&base, mod, start);
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}
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// CHECK-LABEL: test12
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// CHECK: @llvm.hexagon.L2.loadrd.pcr
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long long test12(int mod, void *start) {
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long long *base = start;
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return __builtin_HEXAGON_L2_loadrd_pcr(&base, mod, start);
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}
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// CHECK-LABEL: test13
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// CHECK: @llvm.hexagon.S2.storerb.pci
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void test13(int mod, void *start, char v) {
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void *base = start;
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__builtin_HEXAGON_S2_storerb_pci(&base, 4, mod, v, start);
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}
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// CHECK-LABEL: test14
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// CHECK: @llvm.hexagon.S2.storerh.pci
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void test14(int mod, void *start, short v) {
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void *base = start;
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__builtin_HEXAGON_S2_storerh_pci(&base, 4, mod, v, start);
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}
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// CHECK-LABEL: test15
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// CHECK: @llvm.hexagon.S2.storerf.pci
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void test15(int mod, void *start, short v) {
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void *base = start;
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__builtin_HEXAGON_S2_storerf_pci(&base, 4, mod, v, start);
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}
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// CHECK-LABEL: test16
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// CHECK: @llvm.hexagon.S2.storeri.pci
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void test16(int mod, void *start, int v) {
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void *base = start;
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__builtin_HEXAGON_S2_storeri_pci(&base, 4, mod, v, start);
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}
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// CHECK-LABEL: test17
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// CHECK: @llvm.hexagon.S2.storerd.pci
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void test17(int mod, void *start, long long v) {
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void *base = start;
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__builtin_HEXAGON_S2_storerd_pci(&base, 8, mod, v, start);
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}
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// CHECK-LABEL: test18
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// CHECK: @llvm.hexagon.S2.storerb.pcr
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void test18(int mod, void *start, char v) {
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void *base = start;
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__builtin_HEXAGON_S2_storerb_pcr(&base, mod, v, start);
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}
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// CHECK-LABEL: test19
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// CHECK: @llvm.hexagon.S2.storerh.pcr
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void test19(int mod, void *start, short v) {
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void *base = start;
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__builtin_HEXAGON_S2_storerh_pcr(&base, mod, v, start);
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}
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// CHECK-LABEL: test20
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// CHECK: @llvm.hexagon.S2.storerf.pcr
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void test20(int mod, void *start, short v) {
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void *base = start;
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__builtin_HEXAGON_S2_storerf_pcr(&base, mod, v, start);
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}
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// CHECK-LABEL: test21
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// CHECK: @llvm.hexagon.S2.storeri.pcr
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void test21(int mod, void *start, int v) {
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void *base = start;
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__builtin_HEXAGON_S2_storeri_pcr(&base, mod, v, start);
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}
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// CHECK-LABEL: test22
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// CHECK: @llvm.hexagon.S2.storerd.pcr
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void test22(int mod, void *start, long long v) {
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void *base = start;
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__builtin_HEXAGON_S2_storerd_pcr(&base, mod, v, start);
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}
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