forked from OSchip/llvm-project
[PowerPC][Power10] Add Vector Multiply/Mod/Divide Instruction Definitions and MC Tests
This patch adds the td definitions and asm/disasm tests for the following instructions: - Vector Multiply Low Doubleword: vmulld - Vector Modulus Word/Doubleword: vmodsw, vmoduw, vmodsd, vmodud - Vector Divide Word/Doubleword: vdivsw, vdivuw, vdivsd, vdivud - Vector Multiply High Word/Doubleword: vmulhsw, vmulhsd, vmulhuw, vmulhud - Vector Divide Extended Word/Doubleword: vdivesw, vdiveuw, vdivesd, vdiveud Differential Revision: https://reviews.llvm.org/D82929
This commit is contained in:
Amy Kwan
parent
791544422a
commit
1eb279d2a8
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@ -972,7 +972,40 @@ let Predicates = [IsISA3_1] in {
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"vclrrb $vD, $vA, $rB", IIC_VecGeneral,
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[(set v16i8:$vD,
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(int_ppc_altivec_vclrrb v16i8:$vA, i32:$rB))]>;
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def VMULLD : VXForm_1<457, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
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"vmulld $vD, $vA, $vB", IIC_VecGeneral, []>;
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def VMULHSW : VXForm_1<905, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
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"vmulhsw $vD, $vA, $vB", IIC_VecGeneral, []>;
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def VMULHUW : VXForm_1<649, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
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"vmulhuw $vD, $vA, $vB", IIC_VecGeneral, []>;
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def VMULHSD : VXForm_1<969, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
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"vmulhsd $vD, $vA, $vB", IIC_VecGeneral, []>;
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def VMULHUD : VXForm_1<713, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
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"vmulhud $vD, $vA, $vB", IIC_VecGeneral, []>;
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def VMODSW : VXForm_1<1931, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
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"vmodsw $vD, $vA, $vB", IIC_VecGeneral, []>;
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def VMODUW : VXForm_1<1675, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
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"vmoduw $vD, $vA, $vB", IIC_VecGeneral, []>;
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def VMODSD : VXForm_1<1995, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
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"vmodsd $vD, $vA, $vB", IIC_VecGeneral, []>;
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def VMODUD : VXForm_1<1739, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
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"vmodud $vD, $vA, $vB", IIC_VecGeneral, []>;
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def VDIVSW : VXForm_1<395, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
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"vdivsw $vD, $vA, $vB", IIC_VecGeneral, []>;
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def VDIVUW : VXForm_1<139, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
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"vdivuw $vD, $vA, $vB", IIC_VecGeneral, []>;
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def VDIVSD : VXForm_1<459, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
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"vdivsd $vD, $vA, $vB", IIC_VecGeneral, []>;
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def VDIVUD : VXForm_1<203, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
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"vdivud $vD, $vA, $vB", IIC_VecGeneral, []>;
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def VDIVESW : VXForm_1<907, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
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"vdivesw $vD, $vA, $vB", IIC_VecGeneral, []>;
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def VDIVEUW : VXForm_1<651, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
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"vdiveuw $vD, $vA, $vB", IIC_VecGeneral, []>;
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def VDIVESD : VXForm_1<971, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
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"vdivesd $vD, $vA, $vB", IIC_VecGeneral, []>;
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def VDIVEUD : VXForm_1<715, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
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"vdiveud $vD, $vA, $vB", IIC_VecGeneral, []>;
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def XVTLSBB : XX2_BF3_XO5_XB6_XO9<60, 2, 475, (outs crrc:$BF), (ins vsrc:$XB),
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"xvtlsbb $BF, $XB", IIC_VecGeneral, []>;
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@ -231,6 +231,57 @@
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# CHECK: vsrdbi 2, 3, 4, 5
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0x10 0x43 0x23 0x56
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# CHECK: vmulld 1, 2, 3
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0x10 0x22 0x19 0xc9
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# CHECK: vmodsw 21, 11, 10
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0x12 0xab 0x57 0x8b
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# CHECK: vmoduw 21, 11, 10
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0x12 0xab 0x56 0x8b
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# CHECK: vmodsd 21, 11, 10
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0x12 0xab 0x57 0xcb
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# CHECK: vmodud 21, 11, 10
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0x12 0xab 0x56 0xcb
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# CHECK: vdivsw 21, 11, 10
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0x12 0xab 0x51 0x8b
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# CHECK: vdivuw 21, 11, 10
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0x12 0xab 0x50 0x8b
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# CHECK: vdivsd 21, 11, 10
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0x12 0xab 0x51 0xcb
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# CHECK: vdivud 21, 11, 10
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0x12 0xab 0x50 0xcb
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# CHECK: vmulhsw 1, 2, 3
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0x10 0x22 0x1b 0x89
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# CHECK: vmulhuw 1, 2, 3
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0x10 0x22 0x1a 0x89
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# CHECK: vmulhsd 1, 2, 3
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0x10 0x22 0x1b 0xc9
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# CHECK: vmulhud 1, 2, 3
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0x10 0x22 0x1a 0xc9
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# CHECK: vdivesw 21, 11, 10
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0x12 0xab 0x53 0x8b
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# CHECK: vdiveuw 21, 11, 10
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0x12 0xab 0x52 0x8b
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# CHECK: vdivesd 21, 11, 10
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0x12 0xab 0x53 0xcb
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# CHECK: vdiveud 21, 11, 10
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0x12 0xab 0x52 0xcb
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# CHECK: vinsw 2, 3, 12
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0x10 0x4c 0x18 0xcf
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@ -357,6 +357,57 @@
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# CHECK-BE: vsrdbi 2, 3, 4, 5 # encoding: [0x10,0x43,0x23,0x56]
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# CHECK-LE: vsrdbi 2, 3, 4, 5 # encoding: [0x56,0x23,0x43,0x10]
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vsrdbi 2, 3, 4, 5
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# CHECK-BE: vmulld 1, 2, 3 # encoding: [0x10,0x22,0x19,0xc9]
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# CHECK-LE: vmulld 1, 2, 3 # encoding: [0xc9,0x19,0x22,0x10]
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vmulld 1, 2, 3
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# CHECK-BE: vmulhsw 1, 2, 3 # encoding: [0x10,0x22,0x1b,0x89]
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# CHECK-LE: vmulhsw 1, 2, 3 # encoding: [0x89,0x1b,0x22,0x10]
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vmulhsw 1, 2, 3
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# CHECK-BE: vmulhuw 1, 2, 3 # encoding: [0x10,0x22,0x1a,0x89]
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# CHECK-LE: vmulhuw 1, 2, 3 # encoding: [0x89,0x1a,0x22,0x10]
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vmulhuw 1, 2, 3
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# CHECK-BE: vmulhsd 1, 2, 3 # encoding: [0x10,0x22,0x1b,0xc9]
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# CHECK-LE: vmulhsd 1, 2, 3 # encoding: [0xc9,0x1b,0x22,0x10]
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vmulhsd 1, 2, 3
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# CHECK-BE: vmulhud 1, 2, 3 # encoding: [0x10,0x22,0x1a,0xc9]
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# CHECK-LE: vmulhud 1, 2, 3 # encoding: [0xc9,0x1a,0x22,0x10]
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vmulhud 1, 2, 3
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# CHECK-BE: vmodsw 21, 11, 10 # encoding: [0x12,0xab,0x57,0x8b]
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# CHECK-LE: vmodsw 21, 11, 10 # encoding: [0x8b,0x57,0xab,0x12]
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vmodsw 21, 11, 10
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# CHECK-BE: vmoduw 21, 11, 10 # encoding: [0x12,0xab,0x56,0x8b]
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# CHECK-LE: vmoduw 21, 11, 10 # encoding: [0x8b,0x56,0xab,0x12]
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vmoduw 21, 11, 10
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# CHECK-BE: vmodsd 21, 11, 10 # encoding: [0x12,0xab,0x57,0xcb]
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# CHECK-LE: vmodsd 21, 11, 10 # encoding: [0xcb,0x57,0xab,0x12]
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vmodsd 21, 11, 10
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# CHECK-BE: vmodud 21, 11, 10 # encoding: [0x12,0xab,0x56,0xcb]
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# CHECK-LE: vmodud 21, 11, 10 # encoding: [0xcb,0x56,0xab,0x12]
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vmodud 21, 11, 10
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# CHECK-BE: vdivsw 21, 11, 10 # encoding: [0x12,0xab,0x51,0x8b]
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# CHECK-LE: vdivsw 21, 11, 10 # encoding: [0x8b,0x51,0xab,0x12]
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vdivsw 21, 11, 10
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# CHECK-BE: vdivuw 21, 11, 10 # encoding: [0x12,0xab,0x50,0x8b]
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# CHECK-LE: vdivuw 21, 11, 10 # encoding: [0x8b,0x50,0xab,0x12]
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vdivuw 21, 11, 10
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# CHECK-BE: vdivsd 21, 11, 10 # encoding: [0x12,0xab,0x51,0xcb]
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# CHECK-LE: vdivsd 21, 11, 10 # encoding: [0xcb,0x51,0xab,0x12]
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vdivsd 21, 11, 10
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# CHECK-BE: vdivud 21, 11, 10 # encoding: [0x12,0xab,0x50,0xcb]
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# CHECK-LE: vdivud 21, 11, 10 # encoding: [0xcb,0x50,0xab,0x12]
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vdivud 21, 11, 10
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# CHECK-BE: vdivesw 21, 11, 10 # encoding: [0x12,0xab,0x53,0x8b]
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# CHECK-LE: vdivesw 21, 11, 10 # encoding: [0x8b,0x53,0xab,0x12]
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vdivesw 21, 11, 10
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# CHECK-BE: vdiveuw 21, 11, 10 # encoding: [0x12,0xab,0x52,0x8b]
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# CHECK-LE: vdiveuw 21, 11, 10 # encoding: [0x8b,0x52,0xab,0x12]
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vdiveuw 21, 11, 10
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# CHECK-BE: vdivesd 21, 11, 10 # encoding: [0x12,0xab,0x53,0xcb]
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# CHECK-LE: vdivesd 21, 11, 10 # encoding: [0xcb,0x53,0xab,0x12]
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vdivesd 21, 11, 10
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# CHECK-BE: vdiveud 21, 11, 10 # encoding: [0x12,0xab,0x52,0xcb]
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# CHECK-LE: vdiveud 21, 11, 10 # encoding: [0xcb,0x52,0xab,0x12]
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vdiveud 21, 11, 10
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# CHECK-BE: vinsw 2, 3, 12 # encoding: [0x10,0x4c,0x18,0xcf]
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# CHECK-LE: vinsw 2, 3, 12 # encoding: [0xcf,0x18,0x4c,0x10]
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vinsw 2, 3, 12
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