forked from OSchip/llvm-project
TableGen subtarget parser. Handle new machine model.
Collect processor resources from the subtarget defs. llvm-svn: 163953
This commit is contained in:
Andrew Trick
parent
33401e8469
commit
1e46d48814
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@ -74,6 +74,10 @@ CodeGenSchedModels::CodeGenSchedModels(RecordKeeper &RK,
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DEBUG(for (unsigned i = 0; i < SchedClasses.size(); ++i)
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SchedClasses[i].dump(this));
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// Populate each CodeGenProcModel's WriteResDefs, ReadAdvanceDefs, and
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// ProcResourceDefs.
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collectProcResources();
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}
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/// Gather all processor models.
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@ -1084,6 +1088,192 @@ void CodeGenSchedModels::inferFromRW(const IdxVec &OperWrites,
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inferFromTransitions(LastTransitions, FromClassIdx, ProcIndices, *this);
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}
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// Collect and sort WriteRes, ReadAdvance, and ProcResources.
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void CodeGenSchedModels::collectProcResources() {
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// Add any subtarget-specific SchedReadWrites that are directly associated
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// with processor resources. Refer to the parent SchedClass's ProcIndices to
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// determine which processors they apply to.
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for (SchedClassIter SCI = schedClassBegin(), SCE = schedClassEnd();
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SCI != SCE; ++SCI) {
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if (SCI->ItinClassDef)
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collectItinProcResources(SCI->ItinClassDef);
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else
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collectRWResources(SCI->Writes, SCI->Reads, SCI->ProcIndices);
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}
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// Add resources separately defined by each subtarget.
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RecVec WRDefs = Records.getAllDerivedDefinitions("WriteRes");
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for (RecIter WRI = WRDefs.begin(), WRE = WRDefs.end(); WRI != WRE; ++WRI) {
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Record *ModelDef = (*WRI)->getValueAsDef("SchedModel");
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addWriteRes(*WRI, getProcModel(ModelDef).Index);
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}
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RecVec RADefs = Records.getAllDerivedDefinitions("ReadAdvance");
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for (RecIter RAI = RADefs.begin(), RAE = RADefs.end(); RAI != RAE; ++RAI) {
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Record *ModelDef = (*RAI)->getValueAsDef("SchedModel");
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addReadAdvance(*RAI, getProcModel(ModelDef).Index);
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}
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// Finalize each ProcModel by sorting the record arrays.
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for (unsigned PIdx = 0, PEnd = ProcModels.size(); PIdx != PEnd; ++PIdx) {
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CodeGenProcModel &PM = ProcModels[PIdx];
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std::sort(PM.WriteResDefs.begin(), PM.WriteResDefs.end(),
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LessRecord());
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std::sort(PM.ReadAdvanceDefs.begin(), PM.ReadAdvanceDefs.end(),
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LessRecord());
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std::sort(PM.ProcResourceDefs.begin(), PM.ProcResourceDefs.end(),
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LessRecord());
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DEBUG(
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PM.dump();
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dbgs() << "WriteResDefs: ";
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for (RecIter RI = PM.WriteResDefs.begin(),
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RE = PM.WriteResDefs.end(); RI != RE; ++RI) {
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if ((*RI)->isSubClassOf("WriteRes"))
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dbgs() << (*RI)->getValueAsDef("WriteType")->getName() << " ";
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else
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dbgs() << (*RI)->getName() << " ";
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}
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dbgs() << "\nReadAdvanceDefs: ";
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for (RecIter RI = PM.ReadAdvanceDefs.begin(),
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RE = PM.ReadAdvanceDefs.end(); RI != RE; ++RI) {
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if ((*RI)->isSubClassOf("ReadAdvance"))
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dbgs() << (*RI)->getValueAsDef("ReadType")->getName() << " ";
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else
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dbgs() << (*RI)->getName() << " ";
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}
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dbgs() << "\nProcResourceDefs: ";
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for (RecIter RI = PM.ProcResourceDefs.begin(),
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RE = PM.ProcResourceDefs.end(); RI != RE; ++RI) {
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dbgs() << (*RI)->getName() << " ";
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}
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dbgs() << '\n');
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}
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}
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// Collect itinerary class resources for each processor.
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void CodeGenSchedModels::collectItinProcResources(Record *ItinClassDef) {
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for (unsigned PIdx = 0, PEnd = ProcModels.size(); PIdx != PEnd; ++PIdx) {
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const CodeGenProcModel &PM = ProcModels[PIdx];
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// For all ItinRW entries.
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bool HasMatch = false;
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for (RecIter II = PM.ItinRWDefs.begin(), IE = PM.ItinRWDefs.end();
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II != IE; ++II) {
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RecVec Matched = (*II)->getValueAsListOfDefs("MatchedItinClasses");
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if (!std::count(Matched.begin(), Matched.end(), ItinClassDef))
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continue;
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if (HasMatch)
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throw TGError((*II)->getLoc(), "Duplicate itinerary class "
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+ ItinClassDef->getName()
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+ " in ItinResources for " + PM.ModelName);
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HasMatch = true;
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IdxVec Writes, Reads;
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findRWs((*II)->getValueAsListOfDefs("OperandReadWrites"), Writes, Reads);
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IdxVec ProcIndices(1, PIdx);
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collectRWResources(Writes, Reads, ProcIndices);
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}
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}
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}
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// Collect resources for a set of read/write types and processor indices.
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void CodeGenSchedModels::collectRWResources(const IdxVec &Writes,
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const IdxVec &Reads,
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const IdxVec &ProcIndices) {
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for (IdxIter WI = Writes.begin(), WE = Writes.end(); WI != WE; ++WI) {
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const CodeGenSchedRW &SchedRW = getSchedRW(*WI, /*IsRead=*/false);
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if (SchedRW.TheDef && SchedRW.TheDef->isSubClassOf("SchedWriteRes")) {
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for (IdxIter PI = ProcIndices.begin(), PE = ProcIndices.end();
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PI != PE; ++PI) {
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addWriteRes(SchedRW.TheDef, *PI);
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}
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}
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}
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for (IdxIter RI = Reads.begin(), RE = Reads.end(); RI != RE; ++RI) {
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const CodeGenSchedRW &SchedRW = getSchedRW(*RI, /*IsRead=*/true);
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if (SchedRW.TheDef && SchedRW.TheDef->isSubClassOf("SchedReadAdvance")) {
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for (IdxIter PI = ProcIndices.begin(), PE = ProcIndices.end();
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PI != PE; ++PI) {
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addReadAdvance(SchedRW.TheDef, *PI);
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}
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}
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}
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}
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// Find the processor's resource units for this kind of resource.
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Record *CodeGenSchedModels::findProcResUnits(Record *ProcResKind,
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const CodeGenProcModel &PM) const {
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if (ProcResKind->isSubClassOf("ProcResourceUnits"))
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return ProcResKind;
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Record *ProcUnitDef = 0;
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RecVec ProcResourceDefs =
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Records.getAllDerivedDefinitions("ProcResourceUnits");
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for (RecIter RI = ProcResourceDefs.begin(), RE = ProcResourceDefs.end();
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RI != RE; ++RI) {
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if ((*RI)->getValueAsDef("Kind") == ProcResKind
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&& (*RI)->getValueAsDef("SchedModel") == PM.ModelDef) {
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if (ProcUnitDef) {
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throw TGError((*RI)->getLoc(),
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"Multiple ProcessorResourceUnits associated with "
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+ ProcResKind->getName());
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}
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ProcUnitDef = *RI;
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}
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}
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if (!ProcUnitDef) {
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throw TGError(ProcResKind->getLoc(),
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"No ProcessorResources associated with "
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+ ProcResKind->getName());
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}
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return ProcUnitDef;
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}
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// Iteratively add a resource and its super resources.
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void CodeGenSchedModels::addProcResource(Record *ProcResKind,
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CodeGenProcModel &PM) {
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for (;;) {
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Record *ProcResUnits = findProcResUnits(ProcResKind, PM);
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// See if this ProcResource is already associated with this processor.
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RecIter I = std::find(PM.ProcResourceDefs.begin(),
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PM.ProcResourceDefs.end(), ProcResUnits);
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if (I != PM.ProcResourceDefs.end())
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return;
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PM.ProcResourceDefs.push_back(ProcResUnits);
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if (!ProcResUnits->getValueInit("Super")->isComplete())
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return;
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ProcResKind = ProcResUnits->getValueAsDef("Super");
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}
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}
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// Add resources for a SchedWrite to this processor if they don't exist.
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void CodeGenSchedModels::addWriteRes(Record *ProcWriteResDef, unsigned PIdx) {
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RecVec &WRDefs = ProcModels[PIdx].WriteResDefs;
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RecIter WRI = std::find(WRDefs.begin(), WRDefs.end(), ProcWriteResDef);
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if (WRI != WRDefs.end())
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return;
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WRDefs.push_back(ProcWriteResDef);
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// Visit ProcResourceKinds referenced by the newly discovered WriteRes.
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RecVec ProcResDefs = ProcWriteResDef->getValueAsListOfDefs("ProcResources");
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for (RecIter WritePRI = ProcResDefs.begin(), WritePRE = ProcResDefs.end();
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WritePRI != WritePRE; ++WritePRI) {
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addProcResource(*WritePRI, ProcModels[PIdx]);
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}
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}
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// Add resources for a ReadAdvance to this processor if they don't exist.
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void CodeGenSchedModels::addReadAdvance(Record *ProcReadAdvanceDef,
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unsigned PIdx) {
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RecVec &RADefs = ProcModels[PIdx].ReadAdvanceDefs;
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RecIter I = std::find(RADefs.begin(), RADefs.end(), ProcReadAdvanceDef);
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if (I != RADefs.end())
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return;
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RADefs.push_back(ProcReadAdvanceDef);
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}
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#ifndef NDEBUG
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void CodeGenProcModel::dump() const {
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dbgs() << Index << ": " << ModelName << " "
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@ -171,10 +171,23 @@ struct CodeGenProcModel {
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// This list is empty if no ItinRW refers to this Processor.
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RecVec ItinRWDefs;
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// All read/write resources associated with this processor.
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RecVec WriteResDefs;
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RecVec ReadAdvanceDefs;
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// Per-operand machine model resources associated with this processor.
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RecVec ProcResourceDefs;
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CodeGenProcModel(unsigned Idx, const std::string &Name, Record *MDef,
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Record *IDef) :
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Index(Idx), ModelName(Name), ModelDef(MDef), ItinsDef(IDef) {}
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bool hasInstrSchedModel() const {
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return !WriteResDefs.empty() || !ItinRWDefs.empty();
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}
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unsigned getProcResourceIdx(Record *PRDef) const;
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#ifndef NDEBUG
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void dump() const;
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#endif
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@ -326,6 +339,9 @@ public:
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unsigned findSchedClassIdx(const IdxVec &Writes, const IdxVec &Reads) const;
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Record *findProcResUnits(Record *ProcResKind,
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const CodeGenProcModel &PM) const;
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private:
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void collectProcModels();
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@ -354,6 +370,19 @@ private:
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unsigned FromClassIdx, const IdxVec &ProcIndices);
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void inferFromItinClass(Record *ItinClassDef, unsigned FromClassIdx);
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void inferFromInstRWs(unsigned SCIdx);
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void collectProcResources();
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void collectItinProcResources(Record *ItinClassDef);
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void collectRWResources(const IdxVec &Writes, const IdxVec &Reads,
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const IdxVec &ProcIndices);
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void addProcResource(Record *ProcResourceKind, CodeGenProcModel &PM);
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void addWriteRes(Record *ProcWriteResDef, unsigned PIdx);
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void addReadAdvance(Record *ProcReadAdvanceDef, unsigned PIdx);
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};
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} // namespace llvm
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