forked from OSchip/llvm-project
Shrink down code and add for free AVX {MIN,MAX}P{S,D}{rm,rr} instructions
llvm-svn: 106366
This commit is contained in:
Bruno Cardoso Lopes
parent
c60cecd88b
commit
1e205f6b1c
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@ -788,6 +788,24 @@ multiclass sse12_fp_binop_rm<bits<8> opc, string OpcodeStr,
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defm V#NAME#SD : sse12_fp_scalar<opc,
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!strconcat(OpcodeStr, "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
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OpNode, FR64, f64mem>, XD, VEX_4V;
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defm V#NAME#PS : sse12_fp_packed<opc, !strconcat(OpcodeStr,
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"ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"), OpNode,
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VR128, v4f32, f128mem, memopv4f32, SSEPackedSingle>,
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VEX_4V;
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defm V#NAME#PD : sse12_fp_packed<opc, !strconcat(OpcodeStr,
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"pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), OpNode,
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VR128, v2f64, f128mem, memopv2f64, SSEPackedDouble>,
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OpSize, VEX_4V;
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defm V#NAME#SS : sse12_fp_scalar_int<opc, OpcodeStr, VR128,
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!strconcat(OpcodeStr, "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
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"", "_ss", ssmem, sse_load_f32>, XS, VEX_4V;
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defm V#NAME#SD : sse12_fp_scalar_int<opc, OpcodeStr, VR128,
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!strconcat(OpcodeStr, "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
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"2", "_sd", sdmem, sse_load_f64>, XD, VEX_4V;
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}
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let Constraints = "$src1 = $dst" in {
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@ -798,72 +816,23 @@ multiclass sse12_fp_binop_rm<bits<8> opc, string OpcodeStr,
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defm SD : sse12_fp_scalar<opc,
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!strconcat(OpcodeStr, "sd\t{$src2, $dst|$dst, $src2}"),
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OpNode, FR64, f64mem>, XD;
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}
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defm PS : sse12_fp_packed<opc, !strconcat(OpcodeStr,
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"ps\t{$src2, $dst|$dst, $src2}"), OpNode, VR128, v4f32,
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f128mem, memopv4f32, SSEPackedSingle>, TB;
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// Vector operation, reg+reg.
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def PSrr : PSI<opc, MRMSrcReg, (outs VR128:$dst),
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(ins VR128:$src1, VR128:$src2),
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!strconcat(OpcodeStr, "ps\t{$src2, $dst|$dst, $src2}"),
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[(set VR128:$dst, (v4f32 (OpNode VR128:$src1, VR128:$src2)))]> {
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let isCommutable = Commutable;
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}
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defm PD : sse12_fp_packed<opc, !strconcat(OpcodeStr,
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"pd\t{$src2, $dst|$dst, $src2}"), OpNode, VR128, v2f64,
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f128mem, memopv2f64, SSEPackedDouble>, TB, OpSize;
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def PDrr : PDI<opc, MRMSrcReg, (outs VR128:$dst),
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(ins VR128:$src1, VR128:$src2),
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!strconcat(OpcodeStr, "pd\t{$src2, $dst|$dst, $src2}"),
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[(set VR128:$dst, (v2f64 (OpNode VR128:$src1, VR128:$src2)))]> {
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let isCommutable = Commutable;
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}
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// Vector operation, reg+mem.
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def PSrm : PSI<opc, MRMSrcMem, (outs VR128:$dst),
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(ins VR128:$src1, f128mem:$src2),
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!strconcat(OpcodeStr, "ps\t{$src2, $dst|$dst, $src2}"),
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[(set VR128:$dst, (OpNode VR128:$src1, (memopv4f32 addr:$src2)))]>;
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def PDrm : PDI<opc, MRMSrcMem, (outs VR128:$dst),
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(ins VR128:$src1, f128mem:$src2),
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!strconcat(OpcodeStr, "pd\t{$src2, $dst|$dst, $src2}"),
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[(set VR128:$dst, (OpNode VR128:$src1, (memopv2f64 addr:$src2)))]>;
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// Intrinsic operation, reg+reg.
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def SSrr_Int : SSI<opc, MRMSrcReg, (outs VR128:$dst),
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(ins VR128:$src1, VR128:$src2),
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defm SS : sse12_fp_scalar_int<opc, OpcodeStr, VR128,
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!strconcat(OpcodeStr, "ss\t{$src2, $dst|$dst, $src2}"),
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[(set VR128:$dst, (!nameconcat<Intrinsic>("int_x86_sse_",
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!strconcat(OpcodeStr, "_ss")) VR128:$src1,
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VR128:$src2))]> {
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// int_x86_sse_xxx_ss
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let isCommutable = Commutable;
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}
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"", "_ss", ssmem, sse_load_f32>, XS;
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def SDrr_Int : SDI<opc, MRMSrcReg, (outs VR128:$dst),
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(ins VR128:$src1, VR128:$src2),
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defm SD : sse12_fp_scalar_int<opc, OpcodeStr, VR128,
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!strconcat(OpcodeStr, "sd\t{$src2, $dst|$dst, $src2}"),
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[(set VR128:$dst, (!nameconcat<Intrinsic>("int_x86_sse2_",
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!strconcat(OpcodeStr, "_sd")) VR128:$src1,
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VR128:$src2))]> {
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// int_x86_sse2_xxx_sd
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let isCommutable = Commutable;
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"2", "_sd", sdmem, sse_load_f64>, XD;
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}
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// Intrinsic operation, reg+mem.
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def SSrm_Int : SSI<opc, MRMSrcMem, (outs VR128:$dst),
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(ins VR128:$src1, ssmem:$src2),
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!strconcat(OpcodeStr, "ss\t{$src2, $dst|$dst, $src2}"),
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[(set VR128:$dst, (!nameconcat<Intrinsic>("int_x86_sse_",
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!strconcat(OpcodeStr, "_ss")) VR128:$src1,
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sse_load_f32:$src2))]>;
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// int_x86_sse_xxx_ss
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def SDrm_Int : SDI<opc, MRMSrcMem, (outs VR128:$dst),
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(ins VR128:$src1, sdmem:$src2),
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!strconcat(OpcodeStr, "sd\t{$src2, $dst|$dst, $src2}"),
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[(set VR128:$dst, (!nameconcat<Intrinsic>("int_x86_sse2_",
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!strconcat(OpcodeStr, "_sd")) VR128:$src1,
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sse_load_f64:$src2))]>;
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// int_x86_sse2_xxx_sd
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// Vector intrinsic operation, reg+reg.
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def PSrr_Int : PSI<opc, MRMSrcReg, (outs VR128:$dst),
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(ins VR128:$src1, VR128:$src2),
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@ -10212,3 +10212,35 @@ pshufb CPI1_0(%rip), %xmm1
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// CHECK: encoding: [0xc5,0xeb,0x5d,0x6c,0xcb,0xfc]
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vminsd -4(%ebx,%ecx,8), %xmm2, %xmm5
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// CHECK: vmaxps %xmm2, %xmm4, %xmm6
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// CHECK: encoding: [0xc5,0xd8,0x5f,0xf2]
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vmaxps %xmm2, %xmm4, %xmm6
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// CHECK: vmaxpd %xmm2, %xmm4, %xmm6
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// CHECK: encoding: [0xc5,0xd9,0x5f,0xf2]
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vmaxpd %xmm2, %xmm4, %xmm6
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// CHECK: vminps %xmm2, %xmm4, %xmm6
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// CHECK: encoding: [0xc5,0xd8,0x5d,0xf2]
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vminps %xmm2, %xmm4, %xmm6
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// CHECK: vminpd %xmm2, %xmm4, %xmm6
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// CHECK: encoding: [0xc5,0xd9,0x5d,0xf2]
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vminpd %xmm2, %xmm4, %xmm6
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// CHECK: vmaxps -4(%ebx,%ecx,8), %xmm2, %xmm5
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// CHECK: encoding: [0xc5,0xe8,0x5f,0x6c,0xcb,0xfc]
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vmaxps -4(%ebx,%ecx,8), %xmm2, %xmm5
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// CHECK: vmaxpd -4(%ebx,%ecx,8), %xmm2, %xmm5
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// CHECK: encoding: [0xc5,0xe9,0x5f,0x6c,0xcb,0xfc]
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vmaxpd -4(%ebx,%ecx,8), %xmm2, %xmm5
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// CHECK: vminps -4(%ebx,%ecx,8), %xmm2, %xmm5
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// CHECK: encoding: [0xc5,0xe8,0x5d,0x6c,0xcb,0xfc]
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vminps -4(%ebx,%ecx,8), %xmm2, %xmm5
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// CHECK: vminpd -4(%ebx,%ecx,8), %xmm2, %xmm5
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// CHECK: encoding: [0xc5,0xe9,0x5d,0x6c,0xcb,0xfc]
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vminpd -4(%ebx,%ecx,8), %xmm2, %xmm5
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@ -264,3 +264,35 @@ vdivpd -4(%rcx,%rbx,8), %xmm10, %xmm11
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// CHECK: encoding: [0xc5,0x1b,0x5d,0x54,0xcb,0xfc]
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vminsd -4(%rbx,%rcx,8), %xmm12, %xmm10
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// CHECK: vmaxps %xmm10, %xmm14, %xmm12
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// CHECK: encoding: [0xc4,0x41,0x08,0x5f,0xe2]
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vmaxps %xmm10, %xmm14, %xmm12
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// CHECK: vmaxpd %xmm10, %xmm14, %xmm12
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// CHECK: encoding: [0xc4,0x41,0x09,0x5f,0xe2]
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vmaxpd %xmm10, %xmm14, %xmm12
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// CHECK: vminps %xmm10, %xmm14, %xmm12
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// CHECK: encoding: [0xc4,0x41,0x08,0x5d,0xe2]
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vminps %xmm10, %xmm14, %xmm12
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// CHECK: vminpd %xmm10, %xmm14, %xmm12
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// CHECK: encoding: [0xc4,0x41,0x09,0x5d,0xe2]
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vminpd %xmm10, %xmm14, %xmm12
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// CHECK: vmaxps -4(%rbx,%rcx,8), %xmm12, %xmm10
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// CHECK: encoding: [0xc5,0x18,0x5f,0x54,0xcb,0xfc]
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vmaxps -4(%rbx,%rcx,8), %xmm12, %xmm10
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// CHECK: vmaxpd -4(%rbx,%rcx,8), %xmm12, %xmm10
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// CHECK: encoding: [0xc5,0x19,0x5f,0x54,0xcb,0xfc]
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vmaxpd -4(%rbx,%rcx,8), %xmm12, %xmm10
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// CHECK: vminps -4(%rbx,%rcx,8), %xmm12, %xmm10
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// CHECK: encoding: [0xc5,0x18,0x5d,0x54,0xcb,0xfc]
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vminps -4(%rbx,%rcx,8), %xmm12, %xmm10
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// CHECK: vminpd -4(%rbx,%rcx,8), %xmm12, %xmm10
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// CHECK: encoding: [0xc5,0x19,0x5d,0x54,0xcb,0xfc]
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vminpd -4(%rbx,%rcx,8), %xmm12, %xmm10
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