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AMDGPU/GlobalISel: Implement select() for G_BITCAST s32 <--> <2 x s16> 

Reviewers: arsenm, nhaehnle

Subscribers: kzhuravl, wdng, yaxunl, rovka, kristof.beyls, dstuttard, tpr, t-tye, llvm-commits

Differential Revision: https://reviews.llvm.org/D45881

llvm-svn: 332042
This commit is contained in:
Tom Stellard 2018-05-10 21:20:10 +00:00
parent 4b0084bfcf
commit 1e0edad4bb
3 changed files with 47 additions and 0 deletions
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20
llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
View File

@ -57,6 +57,24 @@ AMDGPUInstructionSelector::AMDGPUInstructionSelector(
const char *AMDGPUInstructionSelector::getName() { return DEBUG_TYPE; }
bool AMDGPUInstructionSelector::selectCOPY(MachineInstr &I) const {
MachineBasicBlock *BB = I.getParent();
MachineFunction *MF = BB->getParent();
MachineRegisterInfo &MRI = MF->getRegInfo();
I.setDesc(TII.get(TargetOpcode::COPY));
for (const MachineOperand &MO : I.operands()) {
if (TargetRegisterInfo::isPhysicalRegister(MO.getReg()))
continue;
const TargetRegisterClass *RC =
TRI.getConstrainedRegClassForOperand(MO, MRI);
if (!RC)
continue;
RBI.constrainGenericRegister(MO.getReg(), *RC, MRI);
}
return true;
}
MachineOperand
AMDGPUInstructionSelector::getSubOperand64(MachineOperand &MO,
unsigned SubIdx) const {
@ -441,6 +459,8 @@ bool AMDGPUInstructionSelector::select(MachineInstr &I,
return selectImpl(I, CoverageInfo);
case TargetOpcode::G_ADD:
return selectG_ADD(I);
case TargetOpcode::G_BITCAST:
return selectCOPY(I);
case TargetOpcode::G_CONSTANT:
return selectG_CONSTANT(I);
case TargetOpcode::G_GEP:

1
llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.h
View File

@ -59,6 +59,7 @@ private:
bool selectImpl(MachineInstr &I, CodeGenCoverage &CoverageInfo) const;
MachineOperand getSubOperand64(MachineOperand &MO, unsigned SubIdx) const;
bool selectCOPY(MachineInstr &I) const;
bool selectG_CONSTANT(MachineInstr &I) const;
bool selectG_ADD(MachineInstr &I) const;
bool selectG_GEP(MachineInstr &I) const;

26
llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-bitcast.mir Normal file
View File

@ -0,0 +1,26 @@
# RUN: llc -march=amdgcn -run-pass=instruction-select -verify-machineinstrs -global-isel %s -o - | FileCheck %s -check-prefixes=GCN
--- |
define amdgpu_kernel void @bitcast(i32 addrspace(1)* %global0) {ret void}
...
---
name: bitcast
legalized: true
regBankSelected: true
# GCN-LABEL: name: bitcast
# GCN: [[A:%[0-9]+]]:vgpr_32 = COPY $vgpr0
# GCN: [[B:%[0-9]+]]:vreg_64 = COPY $vgpr3_vgpr4
# GCN: FLAT_STORE_DWORD [[B]], [[A]]
body: |
bb.0:
liveins: $sgpr0, $vgpr3_vgpr4
%0:vgpr(s32) = COPY $vgpr0
%1:vgpr(s64) = COPY $vgpr3_vgpr4
%2:vgpr(<2 x s16>) = G_BITCAST %0
%3:vgpr(s32) = G_BITCAST %2
G_STORE %3, %1 :: (store 4 into %ir.global0)
...
---