forked from OSchip/llvm-project
[ARM] Use rGPR for writeback vldrs
From what I can tell, a writeback is unpredictable with LR for both loads and stores. This changes the operand from a gprnopc to a rGPR in both cases (which I believe is essentially a NFC due to the tied-def already being a rGPR.) Differential Revision: https://reviews.llvm.org/D96723
This commit is contained in:
parent
a7455d7b7c
commit
1e007cf43c
llvm
lib/Target/ARM
test/CodeGen/Thumb2
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@ -6264,11 +6264,7 @@ multiclass MVE_VLDRSTR_cs_m<MVE_ldst_direction dir, MVE_memsz memsz,
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def _post : MVE_VLDRSTR_cs<
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dir, memsz, 0, 1,
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!con((outs rGPR:$wb), dir.Oops),
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// We need an !if here to select the base register class,
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// because it's legal to write back to SP in a load of this
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// type, but not in a store.
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!con(dir.Iops, (ins !if(dir.load, t2_addr_offset_none,
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t2_nosp_addr_offset_none):$Rn,
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!con(dir.Iops, (ins t2_nosp_addr_offset_none:$Rn,
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t2am_imm7_offset<memsz.shift>:$addr)),
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asm, suffix, IndexModePost, "$Qd, $Rn$addr", "$Rn.base = $wb"> {
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bits<4> Rn;
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@ -62,8 +62,8 @@ tracksRegLiveness: true
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registers:
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- { id: 0, class: rgpr, preferred-register: '' }
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- { id: 1, class: gpr, preferred-register: '' }
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- { id: 2, class: gprnopc, preferred-register: '' }
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- { id: 3, class: gprnopc, preferred-register: '' }
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- { id: 2, class: rgpr, preferred-register: '' }
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- { id: 3, class: rgpr, preferred-register: '' }
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- { id: 4, class: tgpreven, preferred-register: '' }
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- { id: 5, class: gprlr, preferred-register: '' }
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- { id: 6, class: rgpr, preferred-register: '' }
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@ -129,8 +129,8 @@ body: |
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; CHECK: [[t2DoLoopStartTP:%[0-9]+]]:gprlr = t2DoLoopStartTP [[COPY4]], [[COPY6]]
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; CHECK: bb.3.vector.body:
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; CHECK: successors: %bb.3(0x7c000000), %bb.4(0x04000000)
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; CHECK: [[PHI:%[0-9]+]]:gprnopc = PHI [[COPY2]], %bb.2, %10, %bb.3
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; CHECK: [[PHI1:%[0-9]+]]:gprnopc = PHI [[COPY1]], %bb.2, %9, %bb.3
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; CHECK: [[PHI:%[0-9]+]]:rgpr = PHI [[COPY2]], %bb.2, %10, %bb.3
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; CHECK: [[PHI1:%[0-9]+]]:rgpr = PHI [[COPY1]], %bb.2, %9, %bb.3
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; CHECK: [[PHI2:%[0-9]+]]:tgpreven = PHI [[COPY5]], %bb.2, %8, %bb.3
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; CHECK: [[PHI3:%[0-9]+]]:gprlr = PHI [[t2DoLoopStartTP]], %bb.2, %33, %bb.3
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; CHECK: [[PHI4:%[0-9]+]]:rgpr = PHI [[COPY6]], %bb.2, %7, %bb.3
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@ -184,8 +184,8 @@ body: |
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bb.2.vector.body:
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successors: %bb.2(0x7c000000), %bb.3(0x04000000)
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%2:gprnopc = PHI %13, %bb.1, %10, %bb.2
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%3:gprnopc = PHI %14, %bb.1, %9, %bb.2
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%2:rgpr = PHI %13, %bb.1, %10, %bb.2
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%3:rgpr = PHI %14, %bb.1, %9, %bb.2
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%4:tgpreven = PHI %23, %bb.1, %8, %bb.2
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%5:gprlr = PHI %1, %bb.1, %11, %bb.2
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%6:rgpr = PHI %35, %bb.1, %7, %bb.2
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@ -87,7 +87,7 @@ body: |
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; CHECK-LABEL: name: MVE_VLDRWU32
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; CHECK: liveins: $r0, $q0
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; CHECK: [[COPY:%[0-9]+]]:gprnopc = COPY $r0
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; CHECK: [[COPY:%[0-9]+]]:rgpr = COPY $r0
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; CHECK: [[MVE_VLDRWU32_post:%[0-9]+]]:rgpr, [[MVE_VLDRWU32_post1:%[0-9]+]]:mqpr = MVE_VLDRWU32_post [[COPY]], 32, 0, $noreg :: (load 16, align 8)
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; CHECK: $r0 = COPY [[MVE_VLDRWU32_post]]
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; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0
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@ -114,7 +114,7 @@ body: |
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; CHECK-LABEL: name: MVE_VLDRHU16
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; CHECK: liveins: $r0, $q0
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; CHECK: [[COPY:%[0-9]+]]:gprnopc = COPY $r0
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; CHECK: [[COPY:%[0-9]+]]:rgpr = COPY $r0
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; CHECK: [[MVE_VLDRHU16_post:%[0-9]+]]:rgpr, [[MVE_VLDRHU16_post1:%[0-9]+]]:mqpr = MVE_VLDRHU16_post [[COPY]], 32, 0, $noreg :: (load 16, align 8)
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; CHECK: $r0 = COPY [[MVE_VLDRHU16_post]]
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; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0
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@ -141,7 +141,7 @@ body: |
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; CHECK-LABEL: name: MVE_VLDRBU8
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; CHECK: liveins: $r0, $q0
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; CHECK: [[COPY:%[0-9]+]]:gprnopc = COPY $r0
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; CHECK: [[COPY:%[0-9]+]]:rgpr = COPY $r0
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; CHECK: [[MVE_VLDRBU8_post:%[0-9]+]]:rgpr, [[MVE_VLDRBU8_post1:%[0-9]+]]:mqpr = MVE_VLDRBU8_post [[COPY]], 32, 0, $noreg :: (load 16, align 8)
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; CHECK: $r0 = COPY [[MVE_VLDRBU8_post]]
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; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0
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@ -505,7 +505,7 @@ body: |
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; CHECK-LABEL: name: ld0ld4
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; CHECK: liveins: $r0, $q0
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; CHECK: [[COPY:%[0-9]+]]:gprnopc = COPY $r0
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; CHECK: [[COPY:%[0-9]+]]:rgpr = COPY $r0
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; CHECK: [[MVE_VLDRWU32_post:%[0-9]+]]:rgpr, [[MVE_VLDRWU32_post1:%[0-9]+]]:mqpr = MVE_VLDRWU32_post [[COPY]], 32, 0, $noreg :: (load 16, align 8)
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; CHECK: [[MVE_VLDRWU32_:%[0-9]+]]:mqpr = MVE_VLDRWU32 [[MVE_VLDRWU32_post]], -28, 0, $noreg :: (load 16, align 8)
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; CHECK: $r0 = COPY [[MVE_VLDRWU32_post]]
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@ -535,7 +535,7 @@ body: |
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; CHECK-LABEL: name: ld4ld0
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; CHECK: liveins: $r0, $q0
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; CHECK: [[COPY:%[0-9]+]]:gprnopc = COPY $r0
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; CHECK: [[COPY:%[0-9]+]]:rgpr = COPY $r0
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; CHECK: [[MVE_VLDRWU32_:%[0-9]+]]:mqpr = MVE_VLDRWU32 [[COPY]], 4, 0, $noreg :: (load 16, align 8)
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; CHECK: [[MVE_VLDRWU32_post:%[0-9]+]]:rgpr, [[MVE_VLDRWU32_post1:%[0-9]+]]:mqpr = MVE_VLDRWU32_post [[COPY]], 32, 0, $noreg :: (load 16, align 8)
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; CHECK: $r0 = COPY [[MVE_VLDRWU32_post]]
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@ -566,7 +566,7 @@ body: |
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; CHECK-LABEL: name: ld0ld4ld0
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; CHECK: liveins: $r0, $q0
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; CHECK: [[COPY:%[0-9]+]]:gprnopc = COPY $r0
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; CHECK: [[COPY:%[0-9]+]]:rgpr = COPY $r0
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; CHECK: [[MVE_VLDRWU32_:%[0-9]+]]:mqpr = MVE_VLDRWU32 [[COPY]], 0, 0, $noreg :: (load 16, align 8)
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; CHECK: [[MVE_VLDRWU32_1:%[0-9]+]]:mqpr = MVE_VLDRWU32 [[COPY]], 4, 0, $noreg :: (load 16, align 8)
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; CHECK: [[MVE_VLDRWU32_post:%[0-9]+]]:rgpr, [[MVE_VLDRWU32_post1:%[0-9]+]]:mqpr = MVE_VLDRWU32_post [[COPY]], 32, 0, $noreg :: (load 16, align 8)
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@ -599,7 +599,7 @@ body: |
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; CHECK-LABEL: name: ld4ld0ld4
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; CHECK: liveins: $r0, $q0
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; CHECK: [[COPY:%[0-9]+]]:gprnopc = COPY $r0
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; CHECK: [[COPY:%[0-9]+]]:rgpr = COPY $r0
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; CHECK: [[MVE_VLDRWU32_:%[0-9]+]]:mqpr = MVE_VLDRWU32 [[COPY]], 4, 0, $noreg :: (load 16, align 8)
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; CHECK: [[MVE_VLDRWU32_post:%[0-9]+]]:rgpr, [[MVE_VLDRWU32_post1:%[0-9]+]]:mqpr = MVE_VLDRWU32_post [[COPY]], 32, 0, $noreg :: (load 16, align 8)
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; CHECK: [[MVE_VLDRWU32_1:%[0-9]+]]:mqpr = MVE_VLDRWU32 [[MVE_VLDRWU32_post]], -28, 0, $noreg :: (load 16, align 8)
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@ -631,7 +631,7 @@ body: |
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; CHECK-LABEL: name: addload
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; CHECK: liveins: $r0, $q0
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; CHECK: [[COPY:%[0-9]+]]:gprnopc = COPY $r0
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; CHECK: [[COPY:%[0-9]+]]:rgpr = COPY $r0
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; CHECK: [[MVE_VLDRWU32_post:%[0-9]+]]:rgpr, [[MVE_VLDRWU32_post1:%[0-9]+]]:mqpr = MVE_VLDRWU32_post [[COPY]], 32, 0, $noreg :: (load 16, align 8)
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; CHECK: [[MVE_VLDRWU32_:%[0-9]+]]:mqpr = MVE_VLDRWU32 [[MVE_VLDRWU32_post]], -28, 0, $noreg :: (load 16, align 8)
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; CHECK: $r0 = COPY [[MVE_VLDRWU32_post]]
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@ -661,7 +661,7 @@ body: |
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; CHECK-LABEL: name: sub
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; CHECK: liveins: $r0, $q0
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; CHECK: [[COPY:%[0-9]+]]:gprnopc = COPY $r0
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; CHECK: [[COPY:%[0-9]+]]:rgpr = COPY $r0
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; CHECK: [[MVE_VLDRWU32_post:%[0-9]+]]:rgpr, [[MVE_VLDRWU32_post1:%[0-9]+]]:mqpr = MVE_VLDRWU32_post [[COPY]], -32, 0, $noreg :: (load 16, align 8)
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; CHECK: [[MVE_VLDRWU32_:%[0-9]+]]:mqpr = MVE_VLDRWU32 [[MVE_VLDRWU32_post]], 36, 0, $noreg :: (load 16, align 8)
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; CHECK: $r0 = COPY [[MVE_VLDRWU32_post]]
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@ -711,7 +711,7 @@ body: |
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name: postincUse
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tracksRegLiveness: true
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registers:
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- { id: 0, class: gprnopc, preferred-register: '' }
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- { id: 0, class: rgpr, preferred-register: '' }
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- { id: 1, class: mqpr, preferred-register: '' }
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- { id: 2, class: rgpr, preferred-register: '' }
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- { id: 3, class: mqpr, preferred-register: '' }
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@ -725,13 +725,13 @@ body: |
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; CHECK-LABEL: name: postincUse
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; CHECK: liveins: $r0, $q0
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; CHECK: [[COPY:%[0-9]+]]:gprnopc = COPY $r0
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; CHECK: [[COPY:%[0-9]+]]:rgpr = COPY $r0
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; CHECK: [[t2ADDri:%[0-9]+]]:rgpr = nuw t2ADDri [[COPY]], 32, 14 /* CC::al */, $noreg, $noreg
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; CHECK: [[MVE_VLDRWU32_:%[0-9]+]]:mqpr = MVE_VLDRWU32 [[COPY]], 0, 0, $noreg :: (load 16, align 8)
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; CHECK: [[MVE_VLDRWU32_post:%[0-9]+]]:rgpr, [[MVE_VLDRWU32_post1:%[0-9]+]]:mqpr = MVE_VLDRWU32_post [[COPY]], 4, 0, $noreg :: (load 16, align 8)
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; CHECK: $r0 = COPY [[t2ADDri]]
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; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0
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%0:gprnopc = COPY $r0
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%0:rgpr = COPY $r0
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%2:rgpr = nuw t2ADDri %0, 32, 14, $noreg, $noreg
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%1:mqpr = MVE_VLDRWU32 %0, 0, 0, $noreg :: (load 16, align 8)
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%4:rgpr, %3:mqpr = MVE_VLDRWU32_post %0, 4, 0, $noreg :: (load 16, align 8)
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@ -819,7 +819,7 @@ body: |
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; CHECK-LABEL: name: addUseOK
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; CHECK: liveins: $r0, $q0
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; CHECK: [[COPY:%[0-9]+]]:gprnopc = COPY $r0
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; CHECK: [[COPY:%[0-9]+]]:rgpr = COPY $r0
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; CHECK: [[MVE_VLDRWU32_post:%[0-9]+]]:rgpr, [[MVE_VLDRWU32_post1:%[0-9]+]]:mqpr = MVE_VLDRWU32_post [[COPY]], -32, 0, $noreg :: (load 16, align 8)
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; CHECK: [[MVE_VLDRWU32_:%[0-9]+]]:mqpr = MVE_VLDRWU32 [[MVE_VLDRWU32_post]], 36, 0, $noreg :: (load 16, align 8)
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; CHECK: [[t2LSRri:%[0-9]+]]:rgpr = nuw t2LSRri [[MVE_VLDRWU32_post]], 2, 14 /* CC::al */, $noreg, $noreg
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@ -886,7 +886,7 @@ body: |
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; CHECK-LABEL: name: addUseKilled
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; CHECK: liveins: $r0, $q0
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; CHECK: [[COPY:%[0-9]+]]:gprnopc = COPY $r0
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; CHECK: [[COPY:%[0-9]+]]:rgpr = COPY $r0
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; CHECK: [[MVE_VLDRWU32_post:%[0-9]+]]:rgpr, [[MVE_VLDRWU32_post1:%[0-9]+]]:mqpr = MVE_VLDRWU32_post [[COPY]], -32, 0, $noreg :: (load 16, align 8)
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; CHECK: [[t2LSRri:%[0-9]+]]:rgpr = nuw t2LSRri [[MVE_VLDRWU32_post]], 2, 14 /* CC::al */, $noreg, $noreg
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; CHECK: [[MVE_VLDRWU32_:%[0-9]+]]:mqpr = MVE_VLDRWU32 [[MVE_VLDRWU32_post]], 36, 0, $noreg :: (load 16, align 8)
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@ -905,7 +905,7 @@ body: |
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name: MVE_VLDRWU32_post
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tracksRegLiveness: true
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registers:
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- { id: 0, class: gprnopc, preferred-register: '' }
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- { id: 0, class: rgpr, preferred-register: '' }
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- { id: 1, class: mqpr, preferred-register: '' }
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- { id: 2, class: rgpr, preferred-register: '' }
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liveins:
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@ -917,12 +917,12 @@ body: |
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; CHECK-LABEL: name: MVE_VLDRWU32_post
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; CHECK: liveins: $r0, $q0
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; CHECK: [[COPY:%[0-9]+]]:gprnopc = COPY $r0
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; CHECK: [[COPY:%[0-9]+]]:rgpr = COPY $r0
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; CHECK: [[MVE_VLDRWU32_post:%[0-9]+]]:rgpr, [[MVE_VLDRWU32_post1:%[0-9]+]]:mqpr = MVE_VLDRWU32_post [[COPY]], 32, 0, $noreg :: (load 16, align 8)
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; CHECK: [[MVE_VLDRWU32_:%[0-9]+]]:mqpr = MVE_VLDRWU32 [[MVE_VLDRWU32_post]], -16, 0, $noreg :: (load 16, align 8)
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; CHECK: $r0 = COPY [[MVE_VLDRWU32_post]]
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; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0
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%0:gprnopc = COPY $r0
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%0:rgpr = COPY $r0
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%2:rgpr, %1:mqpr = MVE_VLDRWU32_post %0, 32, 0, $noreg :: (load 16, align 8)
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%1:mqpr = MVE_VLDRWU32 %0, 16, 0, $noreg :: (load 16, align 8)
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$r0 = COPY %2
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@ -933,7 +933,7 @@ body: |
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name: MVE_VLDRHU16_post
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tracksRegLiveness: true
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registers:
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- { id: 0, class: gprnopc, preferred-register: '' }
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- { id: 0, class: rgpr, preferred-register: '' }
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- { id: 1, class: mqpr, preferred-register: '' }
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- { id: 2, class: rgpr, preferred-register: '' }
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liveins:
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@ -945,12 +945,12 @@ body: |
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; CHECK-LABEL: name: MVE_VLDRHU16_post
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; CHECK: liveins: $r0, $q0
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; CHECK: [[COPY:%[0-9]+]]:gprnopc = COPY $r0
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; CHECK: [[COPY:%[0-9]+]]:rgpr = COPY $r0
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; CHECK: [[MVE_VLDRHU16_post:%[0-9]+]]:rgpr, [[MVE_VLDRHU16_post1:%[0-9]+]]:mqpr = MVE_VLDRHU16_post [[COPY]], 32, 0, $noreg :: (load 16, align 8)
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; CHECK: [[MVE_VLDRHU16_:%[0-9]+]]:mqpr = MVE_VLDRHU16 [[MVE_VLDRHU16_post]], -16, 0, $noreg :: (load 16, align 8)
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; CHECK: $r0 = COPY [[MVE_VLDRHU16_post]]
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; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0
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%0:gprnopc = COPY $r0
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%0:rgpr = COPY $r0
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%2:rgpr, %1:mqpr = MVE_VLDRHU16_post %0, 32, 0, $noreg :: (load 16, align 8)
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%1:mqpr = MVE_VLDRHU16 %0, 16, 0, $noreg :: (load 16, align 8)
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$r0 = COPY %2
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@ -961,7 +961,7 @@ body: |
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name: MVE_VLDRBU8_post
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tracksRegLiveness: true
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registers:
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- { id: 0, class: gprnopc, preferred-register: '' }
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- { id: 0, class: rgpr, preferred-register: '' }
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- { id: 1, class: mqpr, preferred-register: '' }
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- { id: 2, class: rgpr, preferred-register: '' }
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liveins:
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@ -973,12 +973,12 @@ body: |
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; CHECK-LABEL: name: MVE_VLDRBU8_post
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; CHECK: liveins: $r0, $q0
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; CHECK: [[COPY:%[0-9]+]]:gprnopc = COPY $r0
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; CHECK: [[COPY:%[0-9]+]]:rgpr = COPY $r0
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; CHECK: [[MVE_VLDRBU8_post:%[0-9]+]]:rgpr, [[MVE_VLDRBU8_post1:%[0-9]+]]:mqpr = MVE_VLDRBU8_post [[COPY]], 32, 0, $noreg :: (load 16, align 8)
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; CHECK: [[MVE_VLDRBU8_:%[0-9]+]]:mqpr = MVE_VLDRBU8 [[MVE_VLDRBU8_post]], -16, 0, $noreg :: (load 16, align 8)
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; CHECK: $r0 = COPY [[MVE_VLDRBU8_post]]
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; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $r0
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%0:gprnopc = COPY $r0
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%0:rgpr = COPY $r0
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%2:rgpr, %1:mqpr = MVE_VLDRBU8_post %0, 32, 0, $noreg :: (load 16, align 8)
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%1:mqpr = MVE_VLDRBU8 %0, 16, 0, $noreg :: (load 16, align 8)
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$r0 = COPY %2
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