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[X86] Rename some instructions from 'rb' to 'rrb' to make 'b' a proper suffix. Fix the scheduling information for some of them. 

Some of the scheduling information was only present for the 'rb' version' and not the 'rr' version. Now we match 'rr(b?)'

llvm-svn: 320320
This commit is contained in:
Craig Topper 2017-12-10 17:42:44 +00:00
parent c7445f2cdc
commit 1de942b2d1
3 changed files with 18 additions and 18 deletions
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18
llvm/lib/Target/X86/X86InstrAVX512.td
View File

@ -6534,11 +6534,11 @@ multiclass avx512_cvt_s_int_round<bits<8> opc, X86VectorVTInfo SrcVT,
!strconcat(asm,"\t{$src, $dst|$dst, $src}"),
[(set DstVT.RC:$dst, (OpNode (SrcVT.VT SrcVT.RC:$src),(i32 FROUND_CURRENT)))],
itins.rr>, EVEX, VEX_LIG, Sched<[itins.Sched]>;
def rb : SI<opc, MRMSrcReg, (outs DstVT.RC:$dst), (ins SrcVT.RC:$src, AVX512RC:$rc),
!strconcat(asm,"\t{$rc, $src, $dst|$dst, $src, $rc}"),
[(set DstVT.RC:$dst, (OpNode (SrcVT.VT SrcVT.RC:$src),(i32 imm:$rc)))],
itins.rr>, EVEX, VEX_LIG, EVEX_B, EVEX_RC,
Sched<[itins.Sched]>;
def rrb : SI<opc, MRMSrcReg, (outs DstVT.RC:$dst), (ins SrcVT.RC:$src, AVX512RC:$rc),
!strconcat(asm,"\t{$rc, $src, $dst|$dst, $src, $rc}"),
[(set DstVT.RC:$dst, (OpNode (SrcVT.VT SrcVT.RC:$src),(i32 imm:$rc)))],
itins.rr>, EVEX, VEX_LIG, EVEX_B, EVEX_RC,
Sched<[itins.Sched]>;
def rm : SI<opc, MRMSrcMem, (outs DstVT.RC:$dst), (ins SrcVT.IntScalarMemOp:$src),
!strconcat(asm,"\t{$src, $dst|$dst, $src}"),
[(set DstVT.RC:$dst, (OpNode
@ -6652,7 +6652,7 @@ let Predicates = [HasAVX512] in {
[(set _DstRC.RC:$dst, (OpNode _SrcRC.FRC:$src))], itins.rr>,
EVEX, Sched<[itins.Sched]>;
let hasSideEffects = 0 in
def rb : AVX512<opc, MRMSrcReg, (outs _DstRC.RC:$dst), (ins _SrcRC.FRC:$src),
def rrb : AVX512<opc, MRMSrcReg, (outs _DstRC.RC:$dst), (ins _SrcRC.FRC:$src),
!strconcat(asm,"\t{{sae}, $src, $dst|$dst, $src, {sae}}"),
[], itins.rr>, EVEX, EVEX_B, Sched<[itins.Sched]>;
def rm : AVX512<opc, MRMSrcMem, (outs _DstRC.RC:$dst), (ins _SrcRC.ScalarMemOp:$src),
@ -6663,7 +6663,7 @@ let Predicates = [HasAVX512] in {
def : InstAlias<asm # aliasStr # "\t{$src, $dst|$dst, $src}",
(!cast<Instruction>(NAME # "rr") _DstRC.RC:$dst, _SrcRC.FRC:$src), 0>;
def : InstAlias<asm # aliasStr # "\t\t{{sae}, $src, $dst|$dst, $src, {sae}}",
(!cast<Instruction>(NAME # "rb") _DstRC.RC:$dst, _SrcRC.FRC:$src), 0>;
(!cast<Instruction>(NAME # "rrb") _DstRC.RC:$dst, _SrcRC.FRC:$src), 0>;
def : InstAlias<asm # aliasStr # "\t{$src, $dst|$dst, $src}",
(!cast<Instruction>(NAME # "rm") _DstRC.RC:$dst,
_SrcRC.ScalarMemOp:$src), 0>;
@ -6674,7 +6674,7 @@ let Predicates = [HasAVX512] in {
[(set _DstRC.RC:$dst, (OpNodeRnd (_SrcRC.VT _SrcRC.RC:$src),
(i32 FROUND_CURRENT)))], itins.rr>,
EVEX, VEX_LIG, Sched<[itins.Sched]>;
def rb_Int : AVX512<opc, MRMSrcReg, (outs _DstRC.RC:$dst), (ins _SrcRC.RC:$src),
def rrb_Int : AVX512<opc, MRMSrcReg, (outs _DstRC.RC:$dst), (ins _SrcRC.RC:$src),
!strconcat(asm,"\t{{sae}, $src, $dst|$dst, $src, {sae}}"),
[(set _DstRC.RC:$dst, (OpNodeRnd (_SrcRC.VT _SrcRC.RC:$src),
(i32 FROUND_NO_EXC)))], itins.rr>,
@ -7542,7 +7542,7 @@ multiclass avx512_cvtps2ph<X86VectorVTInfo _dest, X86VectorVTInfo _src,
multiclass avx512_cvtps2ph_sae<X86VectorVTInfo _dest, X86VectorVTInfo _src,
OpndItins itins> {
let hasSideEffects = 0 in
defm rb : AVX512_maskable_in_asm<0x1D, MRMDestReg, _dest,
defm rrb : AVX512_maskable_in_asm<0x1D, MRMDestReg, _dest,
(outs _dest.RC:$dst),
(ins _src.RC:$src1, i32u8imm:$src2),
"vcvtps2ph", "$src2, {sae}, $src1", "$src1, {sae}, $src2",

16
llvm/lib/Target/X86/X86SchedSkylakeServer.td
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@ -3369,13 +3369,13 @@ def: InstRW<[SKXWriteResGroup74], (instregex "VCVTSS2SI64rr")>;
def: InstRW<[SKXWriteResGroup74], (instregex "VCVTSS2SIZrr(b?)(k?)(z?)")>;
def: InstRW<[SKXWriteResGroup74], (instregex "VCVTSS2SIrr")>;
def: InstRW<[SKXWriteResGroup74], (instregex "VCVTSS2USIZrr(b?)(k?)(z?)")>;
def: InstRW<[SKXWriteResGroup74], (instregex "VCVTTSD2SI64Zrb")>;
def: InstRW<[SKXWriteResGroup74], (instregex "VCVTTSD2SI64Zrr(b?)")>;
def: InstRW<[SKXWriteResGroup74], (instregex "VCVTTSD2SI64rr")>;
def: InstRW<[SKXWriteResGroup74], (instregex "VCVTTSD2SIZrb")>;
def: InstRW<[SKXWriteResGroup74], (instregex "VCVTTSD2SIZrr(b?)")>;
def: InstRW<[SKXWriteResGroup74], (instregex "VCVTTSD2SIrr")>;
def: InstRW<[SKXWriteResGroup74], (instregex "VCVTTSD2USI64Zrb")>;
def: InstRW<[SKXWriteResGroup74], (instregex "VCVTTSD2USIZrb")>;
def: InstRW<[SKXWriteResGroup74], (instregex "VCVTTSS2USIZrb")>;
def: InstRW<[SKXWriteResGroup74], (instregex "VCVTTSD2USI64Zrr(b?)")>;
def: InstRW<[SKXWriteResGroup74], (instregex "VCVTTSD2USIZrr(b?)")>;
def: InstRW<[SKXWriteResGroup74], (instregex "VCVTTSS2USIZrr(b?)")>;
def SKXWriteResGroup75 : SchedWriteRes<[SKXPort5,SKXPort23]> {
let Latency = 6;
@ -4174,11 +4174,11 @@ def SKXWriteResGroup100 : SchedWriteRes<[SKXPort0,SKXPort5,SKXPort015]> {
def: InstRW<[SKXWriteResGroup100], (instregex "CVTTSS2SI64rr")>;
def: InstRW<[SKXWriteResGroup100], (instregex "CVTTSS2SIrr")>;
def: InstRW<[SKXWriteResGroup100], (instregex "VCVTSS2USI64Zrr(b?)(k?)(z?)")>;
def: InstRW<[SKXWriteResGroup100], (instregex "VCVTTSS2SI64Zrb")>;
def: InstRW<[SKXWriteResGroup100], (instregex "VCVTTSS2SI64Zrr(b?)")>;
def: InstRW<[SKXWriteResGroup100], (instregex "VCVTTSS2SI64rr")>;
def: InstRW<[SKXWriteResGroup100], (instregex "VCVTTSS2SIZrb")>;
def: InstRW<[SKXWriteResGroup100], (instregex "VCVTTSS2SIZrr(b?)")>;
def: InstRW<[SKXWriteResGroup100], (instregex "VCVTTSS2SIrr")>;
def: InstRW<[SKXWriteResGroup100], (instregex "VCVTTSS2USI64Zrb")>;
def: InstRW<[SKXWriteResGroup100], (instregex "VCVTTSS2USI64Zrr(b?)")>;
def SKXWriteResGroup101 : SchedWriteRes<[SKXPort0,SKXPort23,SKXPort05]> {
let Latency = 7;

2
llvm/test/CodeGen/X86/avx512-schedule.ll
View File

@ -2322,7 +2322,7 @@ define i32 @fptoui(float %a) nounwind {
;
; SKX-LABEL: fptoui:
; SKX: # %bb.0:
; SKX-NEXT: vcvttss2usi %xmm0, %eax # sched: [3:1.00]
; SKX-NEXT: vcvttss2usi %xmm0, %eax # sched: [6:1.00]
; SKX-NEXT: retq # sched: [7:1.00]
%b = fptoui float %a to i32
ret i32 %b