forked from OSchip/llvm-project
[Hexagon] Updating many V4 intrinsic patterns. Adding missing instruction and deleting unused classes.
llvm-svn: 227353
This commit is contained in:
Colin LeMahieu
parent
be09eb75aa
commit
1de7e0d923
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@ -3289,6 +3289,7 @@ let Defs = [USR_OVF], isCodeGenOnly = 0 in {
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def A2_satub : T_S2op_1_ii <"satub", 0b11, 0b110>;
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def A2_sath : T_S2op_1_ii <"sath", 0b11, 0b100>;
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def A2_satuh : T_S2op_1_ii <"satuh", 0b11, 0b101>;
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def A2_roundsat : T_S2op_1_id <"round", 0b11, 0b001, 0b1>;
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}
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let Itinerary = S_2op_tc_2_SLOT23, isCodeGenOnly = 0 in {
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@ -97,6 +97,10 @@ class T_PII_pat <InstHexagon MI, Intrinsic IntID>
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: Pat <(IntID I64:$Rs, imm:$It, imm:$Iu),
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(MI DoubleRegs:$Rs, imm:$It, imm:$Iu)>;
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class T_PPP_pat <InstHexagon MI, Intrinsic IntID>
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: Pat <(IntID I64:$Rs, I64:$Rt, I64:$Ru),
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(MI DoubleRegs:$Rs, DoubleRegs:$Rt, DoubleRegs:$Ru)>;
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class T_PPR_pat <InstHexagon MI, Intrinsic IntID>
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: Pat <(IntID I64:$Rs, I64:$Rt, I32:$Ru),
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(MI DoubleRegs:$Rs, DoubleRegs:$Rt, I32:$Ru)>;
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@ -42,6 +42,10 @@ def: T_RR_pat<C4_nbitsset, int_hexagon_C4_nbitsset>;
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def: T_RR_pat<C4_nbitsclr, int_hexagon_C4_nbitsclr>;
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def: T_RI_pat<C4_nbitsclri, int_hexagon_C4_nbitsclri>;
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def : T_RP_pat <A4_boundscheck, int_hexagon_A4_boundscheck>;
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def : T_PR_pat<A4_tlbmatch, int_hexagon_A4_tlbmatch>;
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def : Pat <(int_hexagon_M4_mpyrr_addr IntRegs:$src1, IntRegs:$src2,
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IntRegs:$src3),
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(M4_mpyrr_addr IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>;
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@ -54,6 +58,9 @@ def : T_RRI_pat <M4_mpyri_addr, int_hexagon_M4_mpyri_addr>;
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def : T_RRR_pat <M4_mac_up_s1_sat, int_hexagon_M4_mac_up_s1_sat>;
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def : T_RRR_pat <M4_nac_up_s1_sat, int_hexagon_M4_nac_up_s1_sat>;
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def : T_PP_pat<A4_andnp, int_hexagon_A4_andnp>;
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def : T_PP_pat<A4_ornp, int_hexagon_A4_ornp>;
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// Extract bitfield
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def : T_PP_pat <S4_extractp_rp, int_hexagon_S4_extractp_rp>;
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def : T_RP_pat <S4_extract_rp, int_hexagon_S4_extract_rp>;
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@ -63,6 +70,9 @@ def : T_RII_pat <S4_extract, int_hexagon_S4_extract>;
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// Shift an immediate left by register amount
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def : T_IR_pat<S4_lsli, int_hexagon_S4_lsli>;
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// Logical xor with xor accumulation
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def : T_PPP_pat<M4_xor_xacc, int_hexagon_M4_xor_xacc>;
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// Shift and add/sub/and/or
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def : T_IRI_pat <S4_andi_asl_ri, int_hexagon_S4_andi_asl_ri>;
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def : T_IRI_pat <S4_ori_asl_ri, int_hexagon_S4_ori_asl_ri>;
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@ -86,24 +96,75 @@ def: T_RI_pat<S4_clbaddi, int_hexagon_S4_clbaddi>;
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def: T_PI_pat<S4_clbpaddi, int_hexagon_S4_clbpaddi>;
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def: T_P_pat <S4_clbpnorm, int_hexagon_S4_clbpnorm>;
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//
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// ALU 32 types.
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//
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/********************************************************************
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* ALU32/ALU *
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*********************************************************************/
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class si_ALU32_sisi_not<string opc, Intrinsic IntID>
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: ALU32_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
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!strconcat("$dst = ", !strconcat(opc , "($src1, ~$src2)")),
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[(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
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// ALU32 / ALU / Logical Operations.
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def: T_RR_pat<A4_andn, int_hexagon_A4_andn>;
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def: T_RR_pat<A4_orn, int_hexagon_A4_orn>;
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class di_ALU32_s8si<string opc, Intrinsic IntID>
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: ALU32_rr<(outs DoubleRegs:$dst), (ins s8Imm:$src1, IntRegs:$src2),
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!strconcat("$dst = ", !strconcat(opc , "(#$src1, $src2)")),
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[(set DoubleRegs:$dst, (IntID imm:$src1, IntRegs:$src2))]>;
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/********************************************************************
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* ALU32/PERM *
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*********************************************************************/
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class di_ALU32_sis8<string opc, Intrinsic IntID>
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: ALU32_rr<(outs DoubleRegs:$dst), (ins IntRegs:$src1, s8Imm:$src2),
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!strconcat("$dst = ", !strconcat(opc , "($src1, #$src2)")),
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[(set DoubleRegs:$dst, (IntID IntRegs:$src1, imm:$src2))]>;
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// Combine Words Into Doublewords.
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def: T_RI_pat<A4_combineri, int_hexagon_A4_combineri, s8ExtPred>;
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def: T_IR_pat<A4_combineir, int_hexagon_A4_combineir, s8ExtPred>;
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/********************************************************************
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* ALU32/PRED *
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*********************************************************************/
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def: T_RR_pat<A4_rcmpeq, int_hexagon_A4_rcmpeq>;
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def: T_RR_pat<A4_rcmpneq, int_hexagon_A4_rcmpneq>;
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def: T_RI_pat<A4_rcmpeqi, int_hexagon_A4_rcmpeqi>;
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def: T_RI_pat<A4_rcmpneqi, int_hexagon_A4_rcmpneqi>;
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/********************************************************************
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* XTYPE/ALU *
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*********************************************************************/
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// Add And Accumulate.
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def : T_RRI_pat <S4_addaddi, int_hexagon_S4_addaddi>;
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def : T_RIR_pat <S4_subaddi, int_hexagon_S4_subaddi>;
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// XTYPE / ALU / Logical-logical Words.
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def : T_RRR_pat <M4_or_xor, int_hexagon_M4_or_xor>;
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def : T_RRR_pat <M4_and_xor, int_hexagon_M4_and_xor>;
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def : T_RRR_pat <M4_or_and, int_hexagon_M4_or_and>;
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def : T_RRR_pat <M4_and_and, int_hexagon_M4_and_and>;
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def : T_RRR_pat <M4_xor_and, int_hexagon_M4_xor_and>;
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def : T_RRR_pat <M4_or_or, int_hexagon_M4_or_or>;
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def : T_RRR_pat <M4_and_or, int_hexagon_M4_and_or>;
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def : T_RRR_pat <M4_xor_or, int_hexagon_M4_xor_or>;
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def : T_RRR_pat <M4_or_andn, int_hexagon_M4_or_andn>;
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def : T_RRR_pat <M4_and_andn, int_hexagon_M4_and_andn>;
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def : T_RRR_pat <M4_xor_andn, int_hexagon_M4_xor_andn>;
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def : T_RRI_pat <S4_or_andi, int_hexagon_S4_or_andi>;
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def : T_RRI_pat <S4_or_andix, int_hexagon_S4_or_andix>;
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def : T_RRI_pat <S4_or_ori, int_hexagon_S4_or_ori>;
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// Modulo wrap.
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def : T_RR_pat <A4_modwrapu, int_hexagon_A4_modwrapu>;
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// Arithmetic/Convergent round
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// Rd=[cround|round](Rs,Rt)[:sat]
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// Rd=[cround|round](Rs,#u5)[:sat]
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def : T_RI_pat <A4_cround_ri, int_hexagon_A4_cround_ri>;
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def : T_RR_pat <A4_cround_rr, int_hexagon_A4_cround_rr>;
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def : T_RI_pat <A4_round_ri, int_hexagon_A4_round_ri>;
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def : T_RR_pat <A4_round_rr, int_hexagon_A4_round_rr>;
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def : T_RI_pat <A4_round_ri_sat, int_hexagon_A4_round_ri_sat>;
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def : T_RR_pat <A4_round_rr_sat, int_hexagon_A4_round_rr_sat>;
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def : T_P_pat <A2_roundsat, int_hexagon_A2_roundsat>;
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class qi_neg_ALU32_sisi<string opc, Intrinsic IntID>
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: ALU32_rr<(outs PredRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
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@ -120,22 +181,6 @@ class qi_neg_ALU32_siu9<string opc, Intrinsic IntID>
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!strconcat("$dst = !", !strconcat(opc , "($src1, #$src2)")),
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[(set PredRegs:$dst, (IntID IntRegs:$src1, imm:$src2))]>;
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class si_neg_ALU32_sisi<string opc, Intrinsic IntID>
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: ALU32_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
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!strconcat("$dst = !", !strconcat(opc , "($src1, $src2)")),
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[(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
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class si_neg_ALU32_sis8<string opc, Intrinsic IntID>
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: ALU32_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, s8Imm:$src2),
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!strconcat("$dst = !", !strconcat(opc , "($src1, #$src2)")),
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[(set IntRegs:$dst, (IntID IntRegs:$src1, imm:$src2))]>;
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class si_ALU32_sis8<string opc, Intrinsic IntID>
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: ALU32_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, s8Imm:$src2),
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!strconcat("$dst = ", !strconcat(opc , "($src1, #$src2)")),
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[(set IntRegs:$dst, (IntID IntRegs:$src1, imm:$src2))]>;
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//
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// SInst Classes.
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//
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@ -176,112 +221,6 @@ class qi_SInst_qi_orqiqi<string opc, Intrinsic IntID>
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[(set PredRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2,
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IntRegs:$src3))]>;
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class si_SInst_si_addsis6<string opc, Intrinsic IntID>
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: SInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2, s6Imm:$src3),
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!strconcat("$dst = ", !strconcat(opc ,
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"($src1, add($src2, #$src3)")),
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[(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2,
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imm:$src3))]>;
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class si_SInst_si_subs6si<string opc, Intrinsic IntID>
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: SInst<(outs IntRegs:$dst), (ins IntRegs:$src1, s6Imm:$src2, IntRegs:$src3),
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!strconcat("$dst = ", !strconcat(opc ,
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"($src1, sub(#$src2, $src3)")),
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[(set IntRegs:$dst, (IntID IntRegs:$src1, imm:$src2,
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IntRegs:$src3))]>;
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class di_ALU64_didi_neg<string opc, Intrinsic IntID>
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: ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, DoubleRegs:$src2),
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!strconcat("$dst = ", !strconcat(opc , "($src1, ~$src2)")),
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[(set DoubleRegs:$dst, (IntID DoubleRegs:$src1, DoubleRegs:$src2))]>;
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class di_MInst_dididi_xacc<string opc, Intrinsic IntID>
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: MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, DoubleRegs:$src1,
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DoubleRegs:$src2),
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!strconcat("$dst ^= ", !strconcat(opc , "($src1, $src2)")),
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[(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, DoubleRegs:$src1,
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DoubleRegs:$src2))],
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"$dst2 = $dst">;
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class si_MInst_sisisi_and<string opc, Intrinsic IntID>
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: MInst<(outs IntRegs:$dst), (ins IntRegs:$dst1, IntRegs:$src2,
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IntRegs:$src3),
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!strconcat("$dst &= ", !strconcat(opc , "($src2, $src3)")),
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[(set IntRegs:$dst, (IntID IntRegs:$dst1, IntRegs:$src2,
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IntRegs:$src3))]>;
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class si_MInst_sisisi_andn<string opc, Intrinsic IntID>
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: MInst<(outs IntRegs:$dst), (ins IntRegs:$dst1, IntRegs:$src2,
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IntRegs:$src3),
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!strconcat("$dst &= ", !strconcat(opc , "($src2, ~$src3)")),
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[(set IntRegs:$dst, (IntID IntRegs:$dst1, IntRegs:$src2,
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IntRegs:$src3))]>;
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class si_SInst_sisis10_andi<string opc, Intrinsic IntID>
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: SInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2, s10Imm:$src3),
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!strconcat("$dst = ", !strconcat(opc ,
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"($src1, and($src2, #$src3))")),
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[(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2,
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imm:$src3))]>;
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class si_MInst_sisisi_xor<string opc, Intrinsic IntID>
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: MInst<(outs IntRegs:$dst), (ins IntRegs:$dst1, IntRegs:$src2,
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IntRegs:$src3),
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!strconcat("$dst ^= ", !strconcat(opc , "($src2, $src3)")),
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[(set IntRegs:$dst, (IntID IntRegs:$dst1, IntRegs:$src2,
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IntRegs:$src3))]>;
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class si_MInst_sisisi_xorn<string opc, Intrinsic IntID>
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: MInst<(outs IntRegs:$dst), (ins IntRegs:$dst1, IntRegs:$src2,
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IntRegs:$src3),
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!strconcat("$dst ^= ", !strconcat(opc , "($src2, ~$src3)")),
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[(set IntRegs:$dst, (IntID IntRegs:$dst1, IntRegs:$src2,
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IntRegs:$src3))]>;
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class si_SInst_sisis10_or<string opc, Intrinsic IntID>
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: SInst<(outs IntRegs:$dst), (ins IntRegs:$dst1, IntRegs:$src2, s10Imm:$src3),
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!strconcat("$dst |= ", !strconcat(opc , "($src2, #$src3)")),
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[(set IntRegs:$dst, (IntID IntRegs:$dst1, IntRegs:$src2,
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imm:$src3))]>;
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class si_MInst_sisisi_or<string opc, Intrinsic IntID>
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: MInst<(outs IntRegs:$dst), (ins IntRegs:$dst1, IntRegs:$src2,
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IntRegs:$src3),
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!strconcat("$dst |= ", !strconcat(opc , "($src2, $src3)")),
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[(set IntRegs:$dst, (IntID IntRegs:$dst1, IntRegs:$src2,
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IntRegs:$src3))]>;
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class si_MInst_sisisi_orn<string opc, Intrinsic IntID>
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: MInst<(outs IntRegs:$dst), (ins IntRegs:$dst1, IntRegs:$src2,
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IntRegs:$src3),
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!strconcat("$dst |= ", !strconcat(opc , "($src2, ~$src3)")),
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[(set IntRegs:$dst, (IntID IntRegs:$dst1, IntRegs:$src2,
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IntRegs:$src3))]>;
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class si_SInst_siu5_sat<string opc, Intrinsic IntID>
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: SInst<(outs IntRegs:$dst), (ins IntRegs:$src1, u5Imm:$src2),
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!strconcat("$dst = ", !strconcat(opc , "($src1, #$src2):sat")),
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[(set IntRegs:$dst, (IntID IntRegs:$src1, imm:$src2))]>;
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/********************************************************************
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* ALU32/ALU *
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*********************************************************************/
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// ALU32 / ALU / Logical Operations.
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def Hexagon_A4_orn : si_ALU32_sisi_not <"or", int_hexagon_A4_orn>;
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def Hexagon_A4_andn : si_ALU32_sisi_not <"and", int_hexagon_A4_andn>;
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/********************************************************************
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* ALU32/PERM *
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*********************************************************************/
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// ALU32 / PERM / Combine Words Into Doublewords.
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def Hexagon_A4_combineir : di_ALU32_s8si <"combine", int_hexagon_A4_combineir>;
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def Hexagon_A4_combineri : di_ALU32_sis8 <"combine", int_hexagon_A4_combineri>;
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/********************************************************************
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* ALU32/PRED *
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*********************************************************************/
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@ -298,12 +237,6 @@ def: T_RI_pat<C4_cmpneqi, int_hexagon_C4_cmpneqi>;
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def: T_RI_pat<C4_cmpltei, int_hexagon_C4_cmpltei>;
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def: T_RI_pat<C4_cmplteui, int_hexagon_C4_cmplteui>;
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// ALU32 / PRED / cmpare To General Register.
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def Hexagon_A4_rcmpneq : si_neg_ALU32_sisi <"cmp.eq", int_hexagon_A4_rcmpneq>;
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def Hexagon_A4_rcmpneqi: si_neg_ALU32_sis8 <"cmp.eq", int_hexagon_A4_rcmpneqi>;
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def Hexagon_A4_rcmpeq : si_ALU32_sisi <"cmp.eq", int_hexagon_A4_rcmpeq>;
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def Hexagon_A4_rcmpeqi : si_ALU32_sis8 <"cmp.eq", int_hexagon_A4_rcmpeqi>;
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/********************************************************************
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* CR *
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@ -332,112 +265,3 @@ def Hexagon_C4_or_orn:
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qi_SInst_qi_orqiqi_neg <"or", int_hexagon_C4_or_orn>;
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def Hexagon_C4_or_or:
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qi_SInst_qi_orqiqi <"or", int_hexagon_C4_or_or>;
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/********************************************************************
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* XTYPE/ALU *
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*********************************************************************/
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// XTYPE / ALU / Add And Accumulate.
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def Hexagon_S4_addaddi:
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si_SInst_si_addsis6 <"add", int_hexagon_S4_addaddi>;
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def Hexagon_S4_subaddi:
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si_SInst_si_subs6si <"add", int_hexagon_S4_subaddi>;
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// XTYPE / ALU / Logical Doublewords.
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def Hexagon_S4_andnp:
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di_ALU64_didi_neg <"and", int_hexagon_A4_andnp>;
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def Hexagon_S4_ornp:
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di_ALU64_didi_neg <"or", int_hexagon_A4_ornp>;
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// XTYPE / ALU / Logical-logical Doublewords.
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def Hexagon_M4_xor_xacc:
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di_MInst_dididi_xacc <"xor", int_hexagon_M4_xor_xacc>;
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// XTYPE / ALU / Logical-logical Words.
|
||||
def HEXAGON_M4_and_and:
|
||||
si_MInst_sisisi_and <"and", int_hexagon_M4_and_and>;
|
||||
def HEXAGON_M4_and_or:
|
||||
si_MInst_sisisi_and <"or", int_hexagon_M4_and_or>;
|
||||
def HEXAGON_M4_and_xor:
|
||||
si_MInst_sisisi_and <"xor", int_hexagon_M4_and_xor>;
|
||||
def HEXAGON_M4_and_andn:
|
||||
si_MInst_sisisi_andn <"and", int_hexagon_M4_and_andn>;
|
||||
def HEXAGON_M4_xor_and:
|
||||
si_MInst_sisisi_xor <"and", int_hexagon_M4_xor_and>;
|
||||
def HEXAGON_M4_xor_or:
|
||||
si_MInst_sisisi_xor <"or", int_hexagon_M4_xor_or>;
|
||||
def HEXAGON_M4_xor_andn:
|
||||
si_MInst_sisisi_xorn <"and", int_hexagon_M4_xor_andn>;
|
||||
def HEXAGON_M4_or_and:
|
||||
si_MInst_sisisi_or <"and", int_hexagon_M4_or_and>;
|
||||
def HEXAGON_M4_or_or:
|
||||
si_MInst_sisisi_or <"or", int_hexagon_M4_or_or>;
|
||||
def HEXAGON_M4_or_xor:
|
||||
si_MInst_sisisi_or <"xor", int_hexagon_M4_or_xor>;
|
||||
def HEXAGON_M4_or_andn:
|
||||
si_MInst_sisisi_orn <"and", int_hexagon_M4_or_andn>;
|
||||
def HEXAGON_S4_or_andix:
|
||||
si_SInst_sisis10_andi <"or", int_hexagon_S4_or_andix>;
|
||||
def HEXAGON_S4_or_andi:
|
||||
si_SInst_sisis10_or <"and", int_hexagon_S4_or_andi>;
|
||||
def HEXAGON_S4_or_ori:
|
||||
si_SInst_sisis10_or <"or", int_hexagon_S4_or_ori>;
|
||||
|
||||
// XTYPE / ALU / Modulo wrap.
|
||||
def HEXAGON_A4_modwrapu:
|
||||
si_ALU64_sisi <"modwrap", int_hexagon_A4_modwrapu>;
|
||||
|
||||
// XTYPE / ALU / Round.
|
||||
def HEXAGON_A4_cround_ri:
|
||||
si_SInst_siu5 <"cround", int_hexagon_A4_cround_ri>;
|
||||
def HEXAGON_A4_cround_rr:
|
||||
si_SInst_sisi <"cround", int_hexagon_A4_cround_rr>;
|
||||
def HEXAGON_A4_round_ri:
|
||||
si_SInst_siu5 <"round", int_hexagon_A4_round_ri>;
|
||||
def HEXAGON_A4_round_rr:
|
||||
si_SInst_sisi <"round", int_hexagon_A4_round_rr>;
|
||||
def HEXAGON_A4_round_ri_sat:
|
||||
si_SInst_siu5_sat <"round", int_hexagon_A4_round_ri_sat>;
|
||||
def HEXAGON_A4_round_rr_sat:
|
||||
si_SInst_sisi_sat <"round", int_hexagon_A4_round_rr_sat>;
|
||||
|
||||
// XTYPE / ALU / Vector reduce add unsigned halfwords.
|
||||
// XTYPE / ALU / Vector add bytes.
|
||||
// XTYPE / ALU / Vector conditional negate.
|
||||
// XTYPE / ALU / Vector maximum bytes.
|
||||
// XTYPE / ALU / Vector reduce maximum halfwords.
|
||||
// XTYPE / ALU / Vector reduce maximum words.
|
||||
// XTYPE / ALU / Vector minimum bytes.
|
||||
// XTYPE / ALU / Vector reduce minimum halfwords.
|
||||
// XTYPE / ALU / Vector reduce minimum words.
|
||||
// XTYPE / ALU / Vector subtract bytes.
|
||||
|
||||
|
||||
/********************************************************************
|
||||
* XTYPE/BIT *
|
||||
*********************************************************************/
|
||||
|
||||
// XTYPE / BIT / Count leading.
|
||||
// XTYPE / BIT / Count trailing.
|
||||
// XTYPE / BIT / Extract bitfield.
|
||||
// XTYPE / BIT / Masked parity.
|
||||
// XTYPE / BIT / Bit reverse.
|
||||
// XTYPE / BIT / Split bitfield.
|
||||
|
||||
|
||||
/********************************************************************
|
||||
* XTYPE/COMPLEX *
|
||||
*********************************************************************/
|
||||
|
||||
// XTYPE / COMPLEX / Complex add/sub halfwords.
|
||||
// XTYPE / COMPLEX / Complex add/sub words.
|
||||
// XTYPE / COMPLEX / Complex multiply 32x16.
|
||||
// XTYPE / COMPLEX / Vector reduce complex rotate.
|
||||
|
||||
|
||||
/********************************************************************
|
||||
* XTYPE/MPY *
|
||||
*********************************************************************/
|
||||
|
||||
// XTYPE / COMPLEX / Complex add/sub halfwords.
|
||||
|
|
|
|||
|
|
@ -120,6 +120,8 @@
|
|||
# CHECK: r17:16 = neg(r21:20)
|
||||
0xd1 0xc0 0x95 0x8c
|
||||
# CHECK: r17 = neg(r21):sat
|
||||
0x31 0xc0 0xd4 0x88
|
||||
# CHECK: r17 = round(r21:20):sat
|
||||
0x11 0xdf 0xf5 0x8c
|
||||
# CHECK: r17 = cround(r21, #31)
|
||||
0x91 0xdf 0xf5 0x8c
|
||||
|
|
|
|||
Loading…
Reference in New Issue