forked from OSchip/llvm-project
Revert "[AMDGPU] llvm-objdump: Minimal HSA Code Object disassembler support."
This reverts commit r265550. There're problems with endianness on dumping instruction bytes. Need to find out how to use support::ulittle32_t type properly. llvm-svn: 265554
This commit is contained in:
Valery Pykhtin
parent
89c33caee3
commit
1dcb91b4de
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@ -1,75 +0,0 @@
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// RUN: llvm-mc -arch=amdgcn -mcpu=tonga %s -filetype=obj | llvm-objdump -disassemble -arch-name=amdgcn -mcpu=tonga - | FileCheck %s
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.text
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.amdgpu_hsa_kernel hello_world
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hello_world:
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.amd_kernel_code_t
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.end_amd_kernel_code_t
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s_mov_b32 m0, 0x10000
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s_load_dwordx2 s[0:1], s[4:5], 0x8
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s_waitcnt lgkmcnt(0)
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s_add_u32 s0, s7, s0
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v_add_i32_e32 v1, vcc, s0, v1
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s_movk_i32 s0, 0x483
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v_cmp_ge_i32_e32 vcc, s0, v0
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s_and_saveexec_b64 s[0:1], vcc
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v_lshlrev_b32_e32 v4, 2, v0
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s_cbranch_execz 21
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s_mov_b64 s[2:3], exec
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s_mov_b64 s[10:11], exec
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v_mov_b32_e32 v3, v0
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s_endpgm
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.amdgpu_hsa_kernel hello_world2
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hello_world2:
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.amd_kernel_code_t
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.end_amd_kernel_code_t
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s_and_saveexec_b64 s[0:1], vcc
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s_cbranch_execz 85
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s_load_dwordx4 s[8:11], s[4:5], 0x40
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v_ashrrev_i32_e32 v77, 31, v76
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v_lshlrev_b64 v[10:11], 2, v[76:77]
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s_waitcnt lgkmcnt(0)
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v_add_i32_e32 v10, vcc, s8, v10
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v_mov_b32_e32 v6, s9
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v_addc_u32_e32 v11, vcc, v6, v11, vcc
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flat_load_dword v0, v[10:11]
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v_lshlrev_b32_e32 v6, 5, v8
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v_lshlrev_b32_e32 v7, 2, v7
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s_endpgm
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// CHECK: file format ELF64-amdgpu-hsacobj
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// CHECK: Disassembly of section .hsatext:
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// CHECK: hello_world:
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// CHECK: s_mov_b32 m0, 0x10000 // 000000000100: BEFC00FF 00010000
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// CHECK: s_load_dwordx2 s[0:1], s[4:5], 0x8 // 000000000108: C0060002 00000008
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// CHECK: s_waitcnt lgkmcnt(0) // 000000000110: BF8C007F
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// CHECK: s_add_u32 s0, s7, s0 // 000000000114: 80000007
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// CHECK: v_add_i32_e32 v1, vcc, s0, v1 // 000000000118: 32020200
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// CHECK: s_movk_i32 s0, 0x483 // 00000000011C: B0000483
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// CHECK: v_cmp_ge_i32_e32 vcc, s0, v0 // 000000000120: 7D8C0000
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// CHECK: s_and_saveexec_b64 s[0:1], vcc // 000000000124: BE80206A
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// CHECK: v_lshlrev_b32_e32 v4, 2, v0 // 000000000128: 24080082
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// CHECK: s_cbranch_execz 21 // 00000000012C: BF880015
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// CHECK: s_mov_b64 s[2:3], exec // 000000000130: BE82017E
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// CHECK: s_mov_b64 s[10:11], exec // 000000000134: BE8A017E
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// CHECK: v_mov_b32_e32 v3, v0 // 000000000138: 7E060300
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// CHECK: s_endpgm // 00000000013C: BF810000
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// CHECK: hello_world2:
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// CHECK: s_and_saveexec_b64 s[0:1], vcc // 000000000240: BE80206A
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// CHECK: s_cbranch_execz 85 // 000000000244: BF880055
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// CHECK: s_load_dwordx4 s[8:11], s[4:5], 0x40 // 000000000248: C00A0202 00000040
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// CHECK: v_ashrrev_i32_e32 v77, 31, v76 // 000000000250: 229A989F
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// CHECK: v_lshlrev_b64 v[10:11], 2, v[76:77] // 000000000254: D28F000A 00029882
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// CHECK: s_waitcnt lgkmcnt(0) // 00000000025C: BF8C007F
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// CHECK: v_add_i32_e32 v10, vcc, s8, v10 // 000000000260: 32141408
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// CHECK: v_mov_b32_e32 v6, s9 // 000000000264: 7E0C0209
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// CHECK: v_addc_u32_e32 v11, vcc, v6, v11, vcc // 000000000268: 38161706
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// CHECK: flat_load_dword v0, v[10:11] // 00000000026C: DC500000 0000000A
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// CHECK: v_lshlrev_b32_e32 v6, 5, v8 // 000000000274: 240C1085
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// CHECK: v_lshlrev_b32_e32 v7, 2, v7 // 000000000278: 240E0E82
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// CHECK: s_endpgm // 00000000027C: BF810000
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@ -384,41 +384,12 @@ public:
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}
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};
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HexagonPrettyPrinter HexagonPrettyPrinterInst;
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class AMDGCNPrettyPrinter : public PrettyPrinter {
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public:
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void printInst(MCInstPrinter &IP,
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const MCInst *MI,
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ArrayRef<uint8_t> Bytes,
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uint64_t Address,
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raw_ostream &OS,
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StringRef Annot,
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MCSubtargetInfo const &STI) override {
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SmallString<40> InstStr;
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raw_svector_ostream IS(InstStr);
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IP.printInst(MI, IS, "", STI);
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OS << left_justify(IS.str(), 60) << format("// %012X: ", Address);
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typedef support::ulittle32_t U32;
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for (auto D : makeArrayRef(reinterpret_cast<const U32*>(Bytes.data()),
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Bytes.size() / sizeof(U32)))
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OS << format("%08X ", D);
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if (!Annot.empty())
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OS << "// " << Annot;
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}
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};
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AMDGCNPrettyPrinter AMDGCNPrettyPrinterInst;
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PrettyPrinter &selectPrettyPrinter(Triple const &Triple) {
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switch(Triple.getArch()) {
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default:
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return PrettyPrinterInst;
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case Triple::hexagon:
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return HexagonPrettyPrinterInst;
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case Triple::amdgcn:
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return AMDGCNPrettyPrinterInst;
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}
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}
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}
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@ -1075,18 +1046,6 @@ static void DisassembleObject(const ObjectFile *Obj, bool InlineRelocs) {
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if (Start >= End)
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continue;
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if (Obj->isELF() && Obj->getArch() == Triple::amdgcn) {
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// make size 4 bytes folded
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End = Start + ((End - Start) & ~0x3ull);
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Start += 256; // add sizeof(amd_kernel_code_t)
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// cut trailing zeroes - up to 256 bytes (align)
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const uint64_t EndAlign = 256;
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const auto Limit = End - (std::min)(EndAlign, End - Start);
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while (End > Limit &&
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*reinterpret_cast<const support::ulittle32_t*>(&Bytes[End - 4]) == 0)
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End -= 4;
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}
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outs() << '\n' << Symbols[si].second << ":\n";
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#ifndef NDEBUG
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