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AMDGPU/GlobalISel: Tolerate copies with no type set 

isVCC has the same bug, but isn't used in a context where it can cause
a problem.

llvm-svn: 364784
This commit is contained in:
Matt Arsenault 2019-07-01 15:23:04 +00:00
parent fb99fc7a68
commit 1daad91af6
2 changed files with 62 additions and 3 deletions
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9
llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
View File

@ -65,9 +65,12 @@ static bool isSCC(unsigned Reg, const MachineRegisterInfo &MRI) {
auto &RegClassOrBank = MRI.getRegClassOrRegBank(Reg);
const TargetRegisterClass *RC =
RegClassOrBank.dyn_cast<const TargetRegisterClass*>();
if (RC)
return RC->getID() == AMDGPU::SReg_32_XM0RegClassID &&
MRI.getType(Reg).getSizeInBits() == 1;
if (RC) {
if (RC->getID() != AMDGPU::SReg_32_XM0RegClassID)
return false;
const LLT Ty = MRI.getType(Reg);
return Ty.isValid() && Ty.getSizeInBits() == 1;
}
const RegisterBank *RB = RegClassOrBank.get<const RegisterBank *>();
return RB->getID() == AMDGPU::SCCRegBankID;

56
llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-copy.mir
View File

@ -138,3 +138,59 @@ body: |
%5:vgpr(s32) = G_SELECT %3, %1, %2
G_STORE %5, %0 :: (store 4, addrspace 1)
...
---
name: copy_sgpr_no_type
legalized: true
regBankSelected: true
body: |
bb.0:
liveins: $sgpr0
; GCN-LABEL: name: copy_sgpr_no_type
; GCN: [[COPY:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0
; GCN: S_ENDPGM 0, implicit [[COPY]]
%0:sreg_32_xm0 = COPY $sgpr0
%1:sreg_32_xm0 = COPY %0
S_ENDPGM 0, implicit %1
...
---
name: copy_vgpr_no_type
legalized: true
regBankSelected: true
body: |
bb.0:
liveins: $vgpr0
; GCN-LABEL: name: copy_vgpr_no_type
; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GCN: S_ENDPGM 0, implicit [[COPY]]
%0:vgpr_32 = COPY $vgpr0
%1:vgpr_32 = COPY %0
S_ENDPGM 0, implicit %1
...
---
name: copy_maybe_vcc
legalized: true
regBankSelected: true
body: |
bb.0:
liveins: $sgpr0_sgpr1
; GCN-LABEL: name: copy_maybe_vcc
; GCN: [[COPY:%[0-9]+]]:sreg_64_xexec = COPY $sgpr0_sgpr1
; GCN: S_ENDPGM 0, implicit [[COPY]]
%0:sreg_64_xexec = COPY $sgpr0_sgpr1
%1:sreg_64_xexec = COPY %0
S_ENDPGM 0, implicit %1
...