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[ARM] Cleanup part of ARMBaseInstrInfo::optimizeCompareInstr (NFCI). 

As noted in another review, this loop is confusing.  This commit cleans it up
somewhat.

Differential Revision: https://reviews.llvm.org/D42312

llvm-svn: 323136
This commit is contained in:
Joel Galenson 2018-01-22 17:53:47 +00:00
parent 9d54d108a6
commit 1d89cd2bb4
1 changed files with 8 additions and 12 deletions
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20
llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
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@ -2736,35 +2736,31 @@ bool ARMBaseInstrInfo::optimizeCompareInstr(
}
I = CmpInstr;
E = MI;
} else if (E != B) {
// Allow the loop below to search E (which was initially MI). Since MI and
// SubAdd have different tests, even if that instruction could not be MI, it
// could still potentially be SubAdd.
--E;
}
// Check that CPSR isn't set between the comparison instruction and the one we
// want to change. At the same time, search for SubAdd.
const TargetRegisterInfo *TRI = &getRegisterInfo();
--I;
for (; I != E; --I) {
const MachineInstr &Instr = *I;
do {
const MachineInstr &Instr = *--I;
// Check whether CmpInstr can be made redundant by the current instruction.
if (isRedundantFlagInstr(&CmpInstr, SrcReg, SrcReg2, CmpValue, &*I)) {
if (isRedundantFlagInstr(&CmpInstr, SrcReg, SrcReg2, CmpValue, &Instr)) {
SubAdd = &*I;
break;
}
// Allow E (which was initially MI) to be SubAdd but do not search before E.
if (I == E)
break;
if (Instr.modifiesRegister(ARM::CPSR, TRI) ||
Instr.readsRegister(ARM::CPSR, TRI))
// This instruction modifies or uses CPSR after the one we want to
// change. We can't do this transformation.
return false;
if (I == B)
break;
}
} while (I != B);
// Return false if no candidates exist.
if (!MI && !SubAdd)